def test_simple(self):
sel, sel_vals = gen_in(2)
x1s, x1_vals = (list(x) for x in zip(*(gen_in(8) for i in range(4))))
x2s, x2_vals = (list(x) for x in zip(*(gen_in(8) for i in range(4))))
x3s, x3_vals = (list(x) for x in zip(*(gen_in(8) for i in range(4))))
i1_out = pyrtl.Output(name="i1_out")
i2_out = pyrtl.Output(name="i2_out")
i3_out = pyrtl.Output(name="i3_out")
with muxes.MultiSelector(sel, i1_out, i2_out, i3_out) as mu:
for i in range(4):
mu.option(i, x1s[i], x2s[i], x3s[i])
wires = [sel] + x1s + x2s + x3s
vals = [sel_vals] + x1_vals + x2_vals + x3_vals
actual_outputs = utils.sim_and_ret_outws(wires, vals)
expected_i1_out = [v[s] for s, v in zip(sel_vals, zip(*x1_vals))]
expected_i2_out = [v[s] for s, v in zip(sel_vals, zip(*x2_vals))]
expected_i3_out = [v[s] for s, v in zip(sel_vals, zip(*x3_vals))]
self.assertEqual(actual_outputs[i1_out], expected_i1_out)
self.assertEqual(actual_outputs[i2_out], expected_i2_out)
self.assertEqual(actual_outputs[i3_out], expected_i3_out)
def test_really_simple(self):
sel, sel_vals = gen_in(1)
i1_0, i1_0_vals = gen_in(8)
i2_0, i2_0_vals = gen_in(8)
i1_1, i1_1_vals = gen_in(8)
i2_1, i2_1_vals = gen_in(8)
i1_out = pyrtl.Output(name="i1_out")
i2_out = pyrtl.Output(name="i2_out")
with muxes.MultiSelector(sel, i1_out, i2_out) as mul_sel:
mul_sel.option(0, i1_0, i2_0)
mul_sel.option(1, i1_1, i2_1)
actual_outputs =\
utils.sim_and_ret_outws([sel, i1_0, i1_1, i2_0, i2_1],
[sel_vals, i1_0_vals, i1_1_vals, i2_0_vals, i2_1_vals])
expected_i1_out = [
v1 if s else v0
for s, v0, v1 in zip(sel_vals, i1_0_vals, i1_1_vals)
]
expected_i2_out = [
v1 if s else v0
for s, v0, v1 in zip(sel_vals, i2_0_vals, i2_1_vals)
]
self.assertEqual(actual_outputs[i1_out.name], expected_i1_out)
self.assertEqual(actual_outputs[i2_out.name], expected_i2_out)
def test_demux_2(self):
in_w, in_vals = utils.an_input_and_vals(1)
outs = (pyrtl.Output(name="output_" + str(i)) for i in range(2))
demux_outs = pyrtl.rtllib.muxes._demux_2(in_w)
for out_w, demux_out in zip(outs, demux_outs):
out_w <<= demux_out
traces = utils.sim_and_ret_outws((in_w,), (in_vals,))
for cycle in range(20):
for i, out_wire in enumerate(outs):
self.assertEqual(in_vals[i] == i, traces[out_wire][cycle])
def test_partition_sim(self):
pyrtl.reset_working_block()
wires, vals = utils.make_inputs_and_values(exact_bitwidth=32, num_wires=1)
out_wires = [pyrtl.Output(8, 'o' + str(i)) for i in range(4)]
partitioned_w = libutils.partition_wire(wires[0], 8)
for p_wire, o_wire in zip(partitioned_w, out_wires):
o_wire <<= p_wire
out_vals = utils.sim_and_ret_outws(wires, vals)
partitioned_vals = [[(val >> i) & 0xff for i in (0, 8, 16, 24)] for val in vals[0]]
true_vals = tuple(zip(*partitioned_vals))
for index, wire in enumerate(out_wires):
self.assertEqual(tuple(out_vals[wire.name]), true_vals[index])
def test_partition_sim(self):
pyrtl.reset_working_block()
wires, vals = utils.make_inputs_and_values(exact_bitwidth=32, num_wires=1)
out_wires = [pyrtl.Output(8, 'o' + str(i)) for i in range(4)]
partitioned_w = libutils.partition_wire(wires[0], 8)
for p_wire, o_wire in zip(partitioned_w, out_wires):
o_wire <<= p_wire
out_vals = utils.sim_and_ret_outws(wires, vals)
partitioned_vals = [[(val >> i) & 0xff for i in (0, 8, 16, 24)] for val in vals[0]]
true_vals = tuple(zip(*partitioned_vals))
for index, wire in enumerate(out_wires):
self.assertEqual(tuple(out_vals[wire]), true_vals[index])
def test_really_simple(self):
sel, sel_vals = gen_in(1)
i1_0, i1_0_vals = gen_in(8)
i2_0, i2_0_vals = gen_in(8)
i1_1, i1_1_vals = gen_in(8)
i2_1, i2_1_vals = gen_in(8)
i1_out = pyrtl.Output(name="i1_out")
i2_out = pyrtl.Output(name="i2_out")
with muxes.MultiSelector(sel, i1_out, i2_out) as mul_sel:
mul_sel.option(0, i1_0, i2_0)
mul_sel.option(1, i1_1, i2_1)
actual_outputs = utils.sim_and_ret_outws([sel, i1_0, i1_1, i2_0, i2_1],
[sel_vals, i1_0_vals, i1_1_vals, i2_0_vals, i2_1_vals])
expected_i1_out = [v1 if s else v0 for s, v0, v1 in zip(sel_vals, i1_0_vals, i1_1_vals )]
expected_i2_out = [v1 if s else v0 for s, v0, v1 in zip(sel_vals, i2_0_vals, i2_1_vals )]
self.assertEqual(actual_outputs[i1_out], expected_i1_out)
self.assertEqual(actual_outputs[i2_out], expected_i2_out)
