def everything_t_procedure(self, timing_val=None, opt_timing_val=None):
# if there is a nondefault timing val supplied, then it will check
# to make sure that the timing matches
# this is a subprocess to do the synth and timing
block = pyrtl.working_block()
timing_map = pyrtl.timing_analysis(block)
timing_max_length = pyrtl.timing_max_length(timing_map)
if timing_val is not None:
self.assertEqual(timing_max_length, timing_val)
critical_path = pyrtl.timing_critical_path(timing_map)
pyrtl.synthesize()
pyrtl.optimize()
block = pyrtl.working_block()
timing_map = pyrtl.timing_analysis(block)
timing_max_length = pyrtl.timing_max_length(timing_map)
if opt_timing_val is not None:
self.assertEqual(timing_max_length, opt_timing_val)
critical_path = pyrtl.timing_critical_path(timing_map)
pyrtl.and_inverter_synth()
pyrtl.optimize()
block = pyrtl.working_block()
timing_map = pyrtl.timing_analysis(block)
timing_max_length = pyrtl.timing_max_length(timing_map)
self.assertEqual(self.num_net_of_type('|', block), 0)
self.assertEqual(self.num_net_of_type('^', block), 0)
pyrtl.nand_synth()
pyrtl.optimize()
block = pyrtl.working_block()
timing_map = pyrtl.timing_analysis(block)
timing_max_length = pyrtl.timing_max_length(timing_map)
block.sanity_check()
self.assertEqual(self.num_net_of_type('|', block), 0)
self.assertEqual(self.num_net_of_type('&', block), 0)
self.assertEqual(self.num_net_of_type('^', block), 0)
def everything_t_procedure(self, timing_val=None, opt_timing_val=None):
# if there is a nondefault timing val supplied, then it will check
# to make sure that the timing matches
# this is a subprocess to do the synth and timing
block = pyrtl.working_block()
timing_map = pyrtl.timing_analysis(block)
timing_max_length = pyrtl.timing_max_length(timing_map)
if timing_val is not None:
self.assertEqual(timing_max_length, timing_val)
critical_path = pyrtl.timing_critical_path(timing_map)
pyrtl.synthesize()
pyrtl.optimize()
block = pyrtl.working_block()
timing_map = pyrtl.timing_analysis(block)
timing_max_length = pyrtl.timing_max_length(timing_map)
if opt_timing_val is not None:
self.assertEqual(timing_max_length, opt_timing_val)
critical_path = pyrtl.timing_critical_path(timing_map)
pyrtl.and_inverter_synth()
pyrtl.optimize()
block = pyrtl.working_block()
timing_map = pyrtl.timing_analysis(block)
timing_max_length = pyrtl.timing_max_length(timing_map)
self.assertEqual(self.num_net_of_type('|', block), 0)
self.assertEqual(self.num_net_of_type('^', block), 0)
pyrtl.nand_synth()
pyrtl.optimize()
block = pyrtl.working_block()
timing_map = pyrtl.timing_analysis(block)
timing_max_length = pyrtl.timing_max_length(timing_map)
block.sanity_check()
self.assertEqual(self.num_net_of_type('|', block), 0)
self.assertEqual(self.num_net_of_type('&', block), 0)
self.assertEqual(self.num_net_of_type('^', block), 0)
const_wire = pyrtl.Const(6, bitwidth=4)
in_wire2 = pyrtl.Input(bitwidth=4, name="input2")
out_wire = pyrtl.Output(bitwidth=5, name="output")
out_wire <<= const_wire + in_wire2
# Now we will do the timing analysis as well as print out the critical path
# Generating timing analysis information
timing_map = pyrtl.timing_analysis()
print("Pre Synthesis:")
pyrtl.print_max_length(timing_map)
# We are also able to print out the critical paths as well as get them
# back as an array.
critical_path_info = pyrtl.timing_critical_path(timing_map)
# --- Part 2: Area Analysis --------------------------------------------------
# PyRTL also provides estimates for the area that would be used up if the
# circuit was printed as an ASIC
est_area = pyrtl.area_estimation(tech_in_nm=65)
print("Estimated Area of block", est_area, "sq mm")
print()
# --- Part 3: Synthesis ------------------------------------------------------
# Synthesis is the operation of reducing the circuit into simpler components
# The base synthesis function breaks down the more complex logic operations
pyrtl.reset_working_block()
const_wire = pyrtl.Const(6, bitwidth=4)
in_wire2 = pyrtl.Input(bitwidth=4, name="input2")
out_wire = pyrtl.Output(bitwidth=5, name="output")
out_wire <<= const_wire + in_wire2
# Now we will do the timing analysis as well as print out the critical path
# Generating timing analysis information
timing_map = pyrtl.timing_analysis()
print("Pre Synthesis:")
pyrtl.print_max_length(timing_map)
# We are also able to print out the critical paths as well as get them
# back as an array.
critical_path_info = pyrtl.timing_critical_path(timing_map)
# --- Part 2: Area Analysis --------------------------------------------------
# PyRTL also provides estimates for the area that would be used up if the
# circuit was printed as an ASIC
est_area = pyrtl.area_estimation(tech_in_nm=65)
print("Estimated Area of block", est_area, "sq mm")
print()
# --- Part 3: Synthesis ------------------------------------------------------
# Synthesis is the operation of reducing the circuit into simpler components
# The base synthesis function breaks down the more complex logic operations
# into logic gates (keeps registers and memories intact) as well as reduces
