def __init__(self, topmodule, terms, binddict, resolved_terms, resolved_binddict, constlist, fsm_vars=('fsm', 'state', 'count', 'cnt', 'step', 'mode') ): VerilogSubset.__init__(self, topmodule, terms, binddict, resolved_terms, resolved_binddict, constlist) self.treewalker = VerilogDataflowWalker(topmodule, terms, binddict, resolved_terms, resolved_binddict, constlist) self.fsm_vars = fsm_vars
def __init__(self, topmodule, terms, binddict, resolved_terms, resolved_binddict, constlist, fsm_vars=('fsm', 'state', 'count', 'cnt', 'step', 'mode') ): VerilogSubset.__init__(self, topmodule, terms, binddict, resolved_terms, resolved_binddict, constlist) self.treewalker = VerilogDataflowWalker(topmodule, terms, binddict, resolved_terms, resolved_binddict, constlist) self.fsm_vars = fsm_vars
def __init__(self, topmodule, terms, binddict, resolved_terms, resolved_binddict, constlist, modulename='Subset', enable_name='HT_enable', num_indent=2, flat=True): VerilogSubset.__init__(self, topmodule, terms, binddict, resolved_terms, resolved_binddict, constlist) self.modulename = modulename self.enable_name = enable_name self.num_indent = num_indent self.flat = flat
def __init__(self, topmodule, terms, binddict, resolved_terms, resolved_binddict, constlist, modulename='Subset', enable_name='HT_enable', num_indent=2, flat=True): VerilogSubset.__init__(self, topmodule, terms, binddict, resolved_terms, resolved_binddict, constlist) self.modulename = modulename self.enable_name = enable_name self.num_indent = num_indent self.flat = flat
def __init__( self, topmodule, terms, binddict, resolved_terms, resolved_binddict, constlist, fsm_vars=("fsm", "state", "count", "cnt", "step", "mode"), ): VerilogSubset.__init__(self, topmodule, terms, binddict, resolved_terms, resolved_binddict, constlist) self.treewalker = VerilogDataflowWalker( topmodule, terms, binddict, resolved_terms, resolved_binddict, constlist ) self.fsm_vars = fsm_vars