return [self.built_filename(directory)]
def build(self, directory):
cwd = os.getcwd()
os.chdir(config.basedir)
command = ['sbt', 'run TestC {} --dataWidth {}'.format(
directory, self.width)]
subprocess.call(command)
os.chdir(cwd)
def get_testC_interface(params):
module_name = 'TestC'
width = params['width']
builder = TestCBuilder({'width': width})
wires_in = (
('io_i_valid', signal.std_logic_type),
('io_i_data', signal.StdLogicVector(width=width)),
)
wires_out = (
('io_o_valid', signal.std_logic_type),
('io_o_data', signal.StdLogicVector(width=width)),
)
iface = interface.Interface(
wires_in, wires_out, module_name=module_name,
builder=builder, parameters=params)
return iface
name = 'TestC'
interface.add_to_module_register(name, get_testC_interface)
"""
def __init__(self, params):
super().__init__(params)
self.simple_filenames = [os.path.join(config.hdldir, "test", "simple_module.vhd")]
def get_simple_module_interface(params):
"""
Creates an interface object that is used to generate the verification
wrappers.
"""
module_name = factory_name
data_width = params["data_width"]
builder = SimpleModuleBuilder({})
module_parameters = {"DATA_WIDTH": data_width}
wires_in = (("i_valid", signal.std_logic_type), ("i_data", signal.StdLogicVector(width=data_width)))
wires_out = (("o_valid", signal.std_logic_type), ("o_data", signal.StdLogicVector(width=data_width)))
iface = interface.Interface(
wires_in,
wires_out,
module_name=module_name,
parameters=params,
module_parameters=module_parameters,
builder=builder,
)
return iface
interface.add_to_module_register(factory_name, get_simple_module_interface)
class AddNumbersCommand(axi.CommCommand):
'''
A command that writes to the intA and intB registers
and then reads from the intC register.
The effect is the add the two inputs.
'''
def __init__(self, a, b, addresses):
super().__init__()
write_a_commands = self.set_unsigned_commands(
address=addresses['intA'], value=a)
write_b_commands = self.set_unsigned_commands(
address=addresses['intB'], value=b)
read_c_commands = self.get_unsigned_commands(
address=addresses['intC'])
self.axi_commands = (
write_a_commands + write_b_commands + read_c_commands)
def process_result(self, result):
'''
Return the third response (from the final read command)
Don't return any errors.
'''
c = result[2][0]
return None, c
name = 'axi_adder'
interface.add_to_module_register(name, get_axi_adder_interface)
from pyvivado import interface, signal, config, builder
logger = logging.getLogger(__name__)
TestBBuilder = builder.make_simple_builder(filenames=[
os.path.join(config.hdldir, 'test', 'testB.sv')])
def get_testB_interface(params):
module_name = 'TestB'
data_width = params['data_width']
builder = TestBBuilder({})
module_parameters = {
'DATA_WIDTH': data_width,
}
wires_in = (
('i_valid', signal.std_logic_type),
('i_data', signal.StdLogicVector(width=data_width)),
)
wires_out = (
('o_valid', signal.std_logic_type),
('o_data', signal.StdLogicVector(width=data_width)),
)
iface = interface.Interface(
wires_in, wires_out, module_name=module_name,
parameters=params, module_parameters=module_parameters,
builder=builder, language='systemverilog')
return iface
name = 'TestB'
interface.add_to_module_register(name, get_testB_interface)
def get_simple_module_interface(params):
'''
Creates an interface object that is used to generate the verification
wrappers.
'''
module_name = factory_name
data_width = params['data_width']
builder = SimpleModuleBuilder({})
module_parameters = {
'DATA_WIDTH': data_width,
}
wires_in = (
('i_valid', signal.std_logic_type),
('i_data', signal.StdLogicVector(width=data_width)),
)
wires_out = (
('o_valid', signal.std_logic_type),
('o_data', signal.StdLogicVector(width=data_width)),
)
iface = interface.Interface(wires_in,
wires_out,
module_name=module_name,
parameters=params,
module_parameters=module_parameters,
builder=builder)
return iface
interface.add_to_module_register(factory_name, get_simple_module_interface)
