def setUp(self) -> None:
"""Setup."""
super().setUp()
self.qubits = list(qiskit.QuantumRegister(2))
self.clbits = list(qiskit.ClassicalRegister(2))
self.instructions = [
types.ScheduledGate(t0=0, operand=library.U1Gate(0),
duration=0, bits=[self.qubits[0]], bit_position=0),
types.ScheduledGate(t0=0, operand=library.U2Gate(0, 0),
duration=10, bits=[self.qubits[0]], bit_position=0),
types.ScheduledGate(t0=10, operand=library.CXGate(),
duration=50, bits=[self.qubits[0], self.qubits[1]],
bit_position=0),
types.ScheduledGate(t0=100, operand=library.U3Gate(0, 0, 0),
duration=20, bits=[self.qubits[0]], bit_position=0),
types.ScheduledGate(t0=120, operand=library.Barrier(2),
duration=0, bits=[self.qubits[0], self.qubits[1]],
bit_position=0),
types.ScheduledGate(t0=120, operand=library.CXGate(),
duration=50, bits=[self.qubits[1], self.qubits[0]],
bit_position=1),
types.ScheduledGate(t0=200, operand=library.Barrier(1),
duration=0, bits=[self.qubits[0]], bit_position=0),
types.ScheduledGate(t0=200, operand=library.Measure(),
duration=100, bits=[self.qubits[0], self.clbits[0]],
bit_position=0),
]
def test_gate_output(self):
"""Test gate output."""
bit_event = events.BitEvents(self.qubits[0], self.instructions, 300)
gates = list(bit_event.get_gates())
ref_list = [
types.ScheduledGate(
t0=0, operand=library.U1Gate(0), duration=0, bits=[self.qubits[0]], bit_position=0
),
types.ScheduledGate(
t0=0,
operand=library.U2Gate(0, 0),
duration=10,
bits=[self.qubits[0]],
bit_position=0,
),
types.ScheduledGate(
t0=10,
operand=library.CXGate(),
duration=50,
bits=[self.qubits[0], self.qubits[1]],
bit_position=0,
),
types.ScheduledGate(
t0=100,
operand=library.U3Gate(0, 0, 0),
duration=20,
bits=[self.qubits[0]],
bit_position=0,
),
types.ScheduledGate(
t0=120,
operand=library.CXGate(),
duration=50,
bits=[self.qubits[1], self.qubits[0]],
bit_position=1,
),
types.ScheduledGate(
t0=200,
operand=library.Measure(),
duration=100,
bits=[self.qubits[0], self.clbits[0]],
bit_position=0,
),
]
self.assertListEqual(gates, ref_list)
def test_bit_link_output(self):
"""Test link output."""
bit_event = events.BitEvents(self.qubits[0], self.instructions, 250)
links = list(bit_event.get_gate_links())
ref_list = [
types.GateLink(t0=35.0, opname=library.CXGate().name,
bits=[self.qubits[0], self.qubits[1]]),
types.GateLink(t0=250.0, opname=library.Measure().name,
bits=[self.qubits[0], self.clbits[0]])
]
self.assertListEqual(links, ref_list)
def pretranspile_qiskit_circuit(circuit):
"""
Pre-transpiles the qiskit circuit to a set of gates that are supported by the Tket compiler.
This is only for compatibility reasons.
:param circuit:
:return:
"""
# Transpile the circuit without any optimizations (i.e. optimization_level=0)
return transpile(circuits=circuit,
basis_gates=[
qiskit_gates.IGate().name,
qiskit_gates.XGate().name,
qiskit_gates.YGate().name,
qiskit_gates.ZGate().name,
qiskit_gates.SGate().name,
qiskit_gates.SdgGate().name,
qiskit_gates.TGate().name,
qiskit_gates.TdgGate().name,
qiskit_gates.HGate().name,
'rx',
'ry',
'rz',
'u1',
'u2',
'u3',
qiskit_gates.CXGate().name,
qiskit_gates.CYGate().name,
qiskit_gates.CZGate().name,
qiskit_gates.CHGate().name,
qiskit_gates.SwapGate().name,
qiskit_gates.CCXGate().name,
qiskit_gates.CSwapGate().name,
'crz',
'cu1',
'cu3'
],
optimization_level=0)