def write(self, data):
''' transmits data and returns true or false whether it failed or not. data needs to be a bytes object '''
if not len(data):
return True
with self.radio_lock:
self.CE_pin.open()
is_receiving = False
self.is_transmitting = True
self.CE_pin.value = 0
reg = self.doOperation(duplex([CONFIG, NOP]))[0][1]
if not (reg & PWR_UP):
_bytes = [WRITE_REG | CONFIG]
_bytes.append(CFGMASK_IRQ | self.CFGMASK_CRC(reg) | PWR_UP)
self.doOperation(writing(_bytes))
time.sleep(0.005)
if reg & PRIM_RX:
is_receiving = True
_bytes = [WRITE_REG | CONFIG]
_bytes.append(CFGMASK_IRQ | self.CFGMASK_CRC(reg) | PWR_UP)
self.doOperation(writing(_bytes))
_bytes = [WR_TX_PLOAD]
_bytes.extend(data)
self.doOperation(writing(_bytes))
self.CE_pin.value = 1
time.sleep(0.00003)
self.CE_pin.value = 0
if not self.readLoopFlag:
self.epoll = select.epoll()
self.IRQ_pin.open()
self.epoll.register(self.IRQ_pin,
select.EPOLLIN | select.EPOLLET)
events = self.epoll.poll()
for fileno, event in events:
if fileno == self.IRQ_pin.fileno():
self.maintenanceHook()
if not self.readLoopFlag:
self.IRQ_pin.close()
self.CE_pin.value = 1
self.is_transmitting = False
if is_receiving:
self.CE_pin.close()
self.radio_lock.release()
self.enableRX()
self.radio_lock.acquire()
else:
self.CE_pin.close()
return self.lastTXfailed
def setChannel(self, channel):
''' set rf channel, channel being 2400+x '''
with self.radio_lock, self.CE_pin:
self.SET_RF_CH = channel
self.CE_pin.value = 0
_bytes = [WRITE_REG | RF_CH]
_bytes.append(self.SET_RF_CH)
self.doOperation(writing(_bytes))
self.CE_pin.value = 1
def setAddress(self, addr):
''' set RX and TX addresses '''
with self.radio_lock, self.CE_pin:
self.RX_ADDR_P1 = addr
self.TX_ADDRESS = addr
self.CE_pin.value = 0
_bytes = [WRITE_REG | RX_ADDR_P1]
_bytes.extend(self.RX_ADDR_P1)
self.doOperation(writing(_bytes))
self.CE_pin.value = 1
def enableRX(self):
''' enables receiver mode '''
with self.radio_lock, self.CE_pin:
self.CE_pin.value = 0
reg = self.doOperation(duplex([FIFO_STATUS, NOP]))[0][1]
_bytes = [WRITE_REG | CONFIG]
_bytes.append(CFGMASK_IRQ | self.CFGMASK_CRC(reg) | PWR_UP
| PRIM_RX)
self.doOperation(writing(_bytes))
if not (reg & PWR_UP):
# wait 5ms if PWR_UP was off
time.sleep(0.005)
self.CE_pin.value = 1
def maintenanceHook(self):
''' from spirilis's Enrf24 '''
lastirq = self.irq_getreason()
if lastirq & IRQ_TXFAILED:
self.lastTXfailed = True
self.doOperation(writing([FLUSH_TX]))
self.irq_clear(IRQ_TXFAILED)
if lastirq & IRQ_TX:
self.lastTXfailed = False
self.irq_clear(IRQ_TX)
if lastirq & IRQ_RX:
reg = self.doOperation(duplex([FIFO_STATUS, NOP]))[0][1]
if (reg & RX_FULL) == 0:
self.irq_clear(IRQ_RX)
reg = self.doOperation(duplex([R_RX_PL_WID, NOP]))[0]
self.rf_status = reg[0]
i = reg[1]
if i == 0 or i > 32 or ((self.rf_status & 0x0E) >> 1) == 0:
self.doOperation(writing([FLUSH_RX]))
self.irq_clear(IRQ_RX)
def setup(self):
''' set initial register values '''
with self.radio_lock, self.CE_pin:
self.CE_pin.value = 0
# clear the CONFIG register
_bytes = [WRITE_REG | CONFIG]
_bytes.append(0x00)
self.doOperation(writing(_bytes))
# set auto-ack
_bytes = [WRITE_REG | EN_AA]
_bytes.append(self.SET_EN_AA)
self.doOperation(writing(_bytes))
# set data pipes
_bytes = [WRITE_REG | EN_RXADDR]
_bytes.append(self.SET_EN_RXADDR)
self.doOperation(writing(_bytes))
# set radio settings
_bytes = [WRITE_REG | RF_SETUP]
_bytes.append(self.SET_RF_SETUP)
self.doOperation(writing(_bytes))
# reset the status register
_bytes = [WRITE_REG | STATUS]
_bytes.append(IRQ_MASK)
self.doOperation(writing(_bytes))
# set dynamic payloads
_bytes = [WRITE_REG | DYNPD]
_bytes.append(self.SET_DYNPD)
self.doOperation(writing(_bytes))
# set features
_bytes = [WRITE_REG | FEATURE]
_bytes.append(self.SET_FEATURE)
self.doOperation(writing(_bytes))
# flush RX Buffer
self.doOperation(writing([FLUSH_RX]))
# flush TX Buffer
self.doOperation(writing([FLUSH_TX]))
# reset the status register
_bytes = [WRITE_REG | STATUS]
_bytes.append(IRQ_MASK)
self.doOperation(writing(_bytes))
_bytes = [WRITE_REG | RF_CH]
_bytes.append(self.SET_RF_CH)
self.doOperation(writing(_bytes))
# set automatic retransmission settings
_bytes = [WRITE_REG | SETUP_RETR]
_bytes.append(self.SET_SETUP_RETR)
self.doOperation(writing(_bytes))
# set address width
_bytes = [WRITE_REG | SETUP_AW]
_bytes.append(self.SET_SETUP_AW)
self.doOperation(writing(_bytes))
# set the CONFIG register
_bytes = [WRITE_REG | CONFIG]
_bytes.append(self.SET_CONFIG)
self.doOperation(writing(_bytes))
# set transmitter address
_bytes = [WRITE_REG | TX_ADDR]
_bytes.extend(self.TX_ADDRESS)
self.doOperation(writing(_bytes))
# set receiver address on data pipe 1
_bytes = [WRITE_REG | RX_ADDR_P1]
_bytes.extend(self.RX_ADDR_P1)
self.doOperation(writing(_bytes))
self.CE_pin.value = 1
def irq_clear(self, irq):
_bytes = [WRITE_REG | STATUS]
_bytes.append(irq & IRQ_MASK)
self.doOperation(writing(_bytes))