def init_clock_sources(self): """ Add the clock sources (e.g. oscillators) to clock tree Some clocks (e.g HSE) are board dependent, and their frequency could not be set here. They have to be set, at runtime, using command line parameters or board file. """ FixedClock(tree=self.tree, name='LSI', freq=32000, en_field=self.RCC.CSR.LSION, rdy_field=self.RCC.CSR.LSIRDY) FixedClock(tree=self.tree, name='LSE', freq=32768, en_field=self.RCC.BDCR.LSEON, rdy_field=self.RCC.BDCR.LSERDY) FixedClock(tree=self.tree, name='HSI', freq=16000000, en_field=self.RCC.CR.HSION, rdy_field=self.RCC.CR.HSIRDY) FixedClock(tree=self.tree, name='HSE', en_field=self.RCC.CR.HSEON, rdy_field=self.RCC.CR.HSERDY) FixedClock(tree=self.tree, name='I2SCKIN')
def __init__(self, device): super(BL123ClockTree, self).__init__(device) device.tree = self clk0 = device.CLOCK0 FixedClock(tree=self, name='OSC0', freq=MHz(1), en_field=clk0.OSC0.EN) FixedClock(tree=self, name='OSC1', freq=MHz(8), en_field=clk0.OSC1.EN) FixedClock(tree=self, name='OSC2', freq=MHz(16), en_field=clk0.OSC2.EN) Mux(tree=self, name='PLLSRC', parents={0: 'OSC0', 1: 'OSC1', 2: 'OSC2'}, mux_field=clk0.PLL.SRC) PLL(tree=self, name='PLL', parent='PLLSRC', get_freq=pll_get_freq, en_field=clk0.PLL.EN) Mux(tree=self, name='BUS0SRC', mux_field=clk0.BUS0.SRC, parents={0: 'OSC0', 1: 'OSC1', 2: 'OSC2', 3: 'PLL'}) Divider(tree=self, name='BUS0DIV', parent='BUS0SRC', div_field=clk0.BUS0.DIV, div_type=Divider.POWER_OF_TWO) Divider(tree=self, name='BUS1DIV', parent='BUS0DIV', div_field=clk0.BUS1.DIV, div_type=Divider.POWER_OF_TWO) Gate(tree=self, name='UART0', parent='BUS0DIV', en_field=clk0.UART0.EN) Gate(tree=self, name='UART1', parent='BUS0DIV', en_field=clk0.UART1.EN) Gate(tree=self, name='GPIO0', parent='BUS1DIV', en_field=clk0.GPIO0.EN) Gate(tree=self, name='GPIO1', parent='BUS1DIV', en_field=clk0.GPIO1.EN) Gate(tree=self, name='GPIO2', parent='BUS1DIV', en_field=clk0.GPIO2.EN) Gate(tree=self, name='GPIO3', parent='BUS1DIV', en_field=clk0.GPIO3.EN)
def setUpClass(self): super(TestClockTree, self).setUpClass() FixedClock(name='osc1', tree=self.tree, freq=1234) FixedClock(name='osc2', tree=self.tree, freq=2345) FixedClock(name='osc3', tree=self.tree, freq=5432) Mux(name='mux1', tree=self.tree, mux_field=self.dev.TEST1.TESTA.A3, parents={ 0: 'osc1', 1: 'osc2', 2: 'osc3', 3: 'osc3' }) Divider(name='div1', tree=self.tree, div=2, parent='osc1') Divider(name='div2', tree=self.tree, div=4, parent='mux1') Gate(name='gate1', tree=self.tree, parent='div1', en_field=self.dev.TEST1.TESTA.A1) Gate(name='gate2', tree=self.tree, parent='div2', en_field=self.dev.TEST1.TESTA.A2) Divider(name='div3', tree=self.tree, div=2, parent='gate2')
def setUpClass(self): super(TestMux, self).setUpClass() self.mux_field = self.dev.TEST1.TESTA.A3 self.tree = ClockTree(self.dev) FixedClock(name='test0', tree=self.tree, freq=1234) FixedClock(name='test1', tree=self.tree, freq=123456) FixedClock(name='test3', tree=self.tree, freq=12345) self.mux_parents = {0: 'test0', 1: 'test1', 3: 'test3'} self.mux = Mux(name='muxe', tree=self.tree, parents=self.mux_parents, mux_field=self.mux_field)
def test_get_freq(self): freq = 123456 tree = ClockTree(self.dev) FixedClock(name='test', tree=self.tree, freq=freq) div = Divider(name='div', tree=self.tree, parent='test', div=2) self.assertEqual(div._get_freq(), freq / 2) div = Divider(name='div', tree=self.tree, parent='test', get_div=ext_get_div_none) self.assertEqual(div._get_freq(), 0) div = Divider(name='div', tree=self.tree, parent='test', get_div=ext_get_div_zero) with self.assertRaises(ZeroDivisionError): self.assertEqual(div._get_freq(), 0) div = Divider(name='div', tree=self.tree, parent='test', get_div=ext_get_div_zero, div_type=Divider.ZERO_TO_GATE) self.assertEqual(div._get_freq(), 0)
def test_get_div(self): tree = ClockTree(self.dev) FixedClock(name='test', tree=self.tree, freq=123456) div = Divider(name='div', tree=self.tree, parent='test', div=2) self.assertEqual(div._get_div(), 2) div = Divider(name='div', tree=self.tree, parent='test', div_field=self.dev.TEST1.TESTA.A3) self.assertEqual(int(div._get_div()), 3) div = Divider(name='div', tree=self.tree, parent='test', div_field=self.dev.TEST1.TESTA.A3, div_type=Divider.POWER_OF_TWO) self.assertEqual(int(div._get_div()), 8) div = Divider(name='div', tree=self.tree, parent='test', div_field=self.dev.TEST1.TESTA.A3, table={ 3: 12, 4: 16 }) self.assertEqual(int(div._get_div()), 12) self.dev.TEST1.TESTA.A3.write(2) with self.assertRaises(InvalidDivider): div._get_div() div = Divider(name='div', tree=self.tree, parent='test', div_field=self.dev.TEST1.TESTA.A3, div_type=9999) with self.assertRaises(InvalidDivider): div._get_div() div = Divider(name='div', tree=self.tree, parent='test', get_div=ext_get_div) self.assertTrue(div.build()) self.assertEqual(int(div._get_div()), 3)
def test_enabled(self): freq = 123456 tree = ClockTree(self.dev) FixedClock(name='test', tree=self.tree, freq=freq) div = Divider(name='div', tree=self.tree, parent='test', div=2) self.assertTrue(div.enabled()) div = Divider(name='div', tree=self.tree, parent='test', get_div=ext_get_div_zero, div_type=Divider.ZERO_TO_GATE) self.assertFalse(div.enabled()) div = Divider(name='div', tree=self.tree, parent='test', get_div=ext_get_div_none) self.assertFalse(div.enabled())
def test_build(self): clock = FixedClock() self.assertFalse(clock.build()) clock = FixedClock(freq=123456) self.assertTrue(clock.build())
def test_get_freq(self): clock = FixedClock(name='osc', tree=self.tree, freq=123456) self.assertEqual(clock.get_freq(), 123456) clock = FixedClock(name='osc', tree=self.tree, min=123, max=456) clock.freq = 12 with self.assertRaises(InvalidFrequency): clock.get_freq() clock.freq = 567 with self.assertRaises(InvalidFrequency): clock.get_freq() clock.freq = 123 self.assertEqual(clock.get_freq(), 123)
def test_fixed_clock(self): clock = FixedClock(freq=123456) self.assertEqual(clock.freq, 123456)