def create_reg_group(node): rg = reglib.register_group() rg.name = node.getAttribute("name") rg.addr_size = reglib.number(node.getAttribute("addr_sz")) rg.base_addr = reglib.number(node.getAttribute("base_addr")) return rg
def create_reg_group (node): rg = reglib.register_group() rg.name = node.getAttribute ("name") rg.addr_size = reglib.number(node.getAttribute ("addr_sz")) rg.base_addr = reglib.number(node.getAttribute ("base_addr")) return rg
def create_addr_decoder(node): rg = reglib.decoder_group() rg.name = node.getAttribute("name") rg.addr_size = reglib.number(node.getAttribute("addr_sz")) data_sz = node.getAttribute("data_sz") if (data_sz != ''): rg.data_size = reglib.number(data_sz) return rg
def create_addr_decoder (node): rg = reglib.decoder_group() rg.name = node.getAttribute ("name") rg.addr_size = reglib.number(node.getAttribute ("addr_sz")) data_sz = node.getAttribute ("data_sz") if (data_sz != ''): rg.data_size = reglib.number(data_sz) return rg
def create_register(rg, node): params = {} params['name'] = node.getAttribute("name") type = node.getAttribute("type") width = node.getAttribute("width") if (width == ''): params['width'] = 1 else: params['width'] = int(width) params['default'] = node.getAttribute("default") params['int_value'] = node.getAttribute("int_value") # May switch to this code later for a more general implementation #for anode in node.childNodes: # if anode.nodeType = anode.ATTRIBUTE_NODE: # params[anode.nodeName] = anode.nodeValue print "Reg:", params['name'], " width:", params['width'] fld_nodes = node.getElementsByTagName("field") fld_list = [] cum_width = 0 cum_default = 0L if (len(fld_nodes) != 0): for fld in fld_nodes: wstr = fld.getAttribute("width") if wstr == '': width = 1 else: width = int(wstr) fld_list.append(reglib.net('wire', fld.getAttribute("name"), width)) default = fld.getAttribute("default") if default == '': default = 0 else: default = long(reglib.number(default)) cum_default = cum_default | (default << cum_width) print "Fld: %20s CD: %x CW: %d D: %x" % ( fld.getAttribute("name"), cum_default, cum_width, default) cum_width += width params['width'] = cum_width params['default'] = cum_default fld_list.reverse() else: if params['default'] == '': params['default'] = 0 else: params['default'] = reglib.number(params['default']) if type == '': type = 'config' rg.add_register(type, params) rg.registers[-1].fields = fld_list
def create_register (rg, node): params = {} params['name'] = node.getAttribute ("name") type = node.getAttribute ("type") width = node.getAttribute ("width") if (width == ''): params['width'] = 1 else : params['width'] = int(width) params['default'] = node.getAttribute ("default") params['int_value'] = node.getAttribute ("int_value") # May switch to this code later for a more general implementation #for anode in node.childNodes: # if anode.nodeType = anode.ATTRIBUTE_NODE: # params[anode.nodeName] = anode.nodeValue print "Reg:",params['name'], " width:",params['width'] fld_nodes = node.getElementsByTagName ("field") fld_list = [] cum_width = 0 cum_default = 0L if (len(fld_nodes) != 0): for fld in fld_nodes: wstr = fld.getAttribute ("width") if wstr == '': width = 1 else: width = int(wstr) fld_list.append (reglib.net('wire',fld.getAttribute("name"),width)) default = fld.getAttribute ("default") if default == '': default = 0 else: default = long(reglib.number (default)) cum_default = cum_default | (default << cum_width) print "Fld: %20s CD: %x CW: %d D: %x" % (fld.getAttribute("name"),cum_default, cum_width, default) cum_width += width params['width'] = cum_width params['default'] = cum_default fld_list.reverse() else: if params['default'] == '': params['default'] = 0 else: params['default'] = reglib.number (params['default']) if type == '': type = 'config' rg.add_register (type, params) rg.registers[-1].fields = fld_list
def create_reg_group(node): rg = reglib.register_group() rg.name = node.getAttribute("name") rg.addr_size = reglib.number(node.getAttribute("addr_sz")) rg.base_addr = reglib.number(node.getAttribute("base_addr")) data_sz = node.getAttribute("data_sz") if (data_sz != ''): rg.data_size = reglib.number(data_sz) rread = node.getAttribute("registered_read") if (data_sz != ''): rg.registered_read = reglib.number(rread) return rg
def create_reg_group (node): rg = reglib.register_group() rg.name = node.getAttribute ("name") rg.addr_size = reglib.number(node.getAttribute ("addr_sz")) rg.base_addr = reglib.number(node.getAttribute ("base_addr")) data_sz = node.getAttribute ("data_sz") if (data_sz != ''): rg.data_size = reglib.number(data_sz) rread = node.getAttribute ("registered_read") if (data_sz != ''): rg.registered_read = reglib.number(rread) return rg
def create_decoder_verilog(top_node): dg = create_addr_decoder(top_node) # get list of address ranges range_nodes = top_node.getElementsByTagName("range") for rn in range_nodes: prefix = rn.getAttribute("prefix") base = reglib.number(rn.getAttribute("base")) bits = int(rn.getAttribute("bits")) r = reglib.decoder_range(prefix, base, bits) dg.add_range(r) fname = dg.name + ".v" fh = open(fname, 'w') fh.write(dg.verilog()) fh.close() create_addr_vh(dg.name + ".vh", dg)
def create_decoder_verilog (top_node): dg = create_addr_decoder (top_node) # get list of address ranges range_nodes = top_node.getElementsByTagName ("range") for rn in range_nodes: prefix = rn.getAttribute ("prefix") base = reglib.number(rn.getAttribute ("base")) bits = int(rn.getAttribute ("bits")) r = reglib.decoder_range (prefix, base, bits) dg.add_range (r) fname = dg.name + ".v" fh = open (fname, 'w') fh.write (dg.verilog()) fh.close() create_addr_vh (dg.name + ".vh", dg)
def create_register (rg, node): params = {} params['name'] = node.getAttribute ("name") type = node.getAttribute ("type") params['width'] = int(node.getAttribute ("width")) params['default'] = node.getAttribute ("default") params['int_value'] = node.getAttribute ("int_value") # May switch to this code later for a more general implementation #for anode in node.childNodes: # if anode.nodeType = anode.ATTRIBUTE_NODE: # params[anode.nodeName] = anode.nodeValue if type == '': type = 'config' if params['default'] == '': params['default'] = 0 else: params['default'] = reglib.number (params['default']) rg.add_register (type, params)
def create_register(rg, node): params = {} params['name'] = node.getAttribute("name") type = node.getAttribute("type") params['width'] = int(node.getAttribute("width")) params['default'] = node.getAttribute("default") params['int_value'] = node.getAttribute("int_value") # May switch to this code later for a more general implementation #for anode in node.childNodes: # if anode.nodeType = anode.ATTRIBUTE_NODE: # params[anode.nodeName] = anode.nodeValue if type == '': type = 'config' if params['default'] == '': params['default'] = 0 else: params['default'] = reglib.number(params['default']) rg.add_register(type, params)