def test_spi_cso_config(args=None): args = tb_default_args() # get an instance of the control-status object cso = spi_controller.cso() assert isinstance(cso, spi.cso.ControlStatus) # set a default configuration cso.loopback.initial_value = False cso.clock_polarity.initial_value = True cso.clock_phase.initial_value = True cso.clock_divisor.initial_value = 2 cso.slave_select.initial_value = 0x10 cso.isstatic = True def bench(): tbdut = cso.get_generators() @instance def tbstim(): yield delay(10) assert not cso.loopback assert cso.clock_polarity assert cso.clock_phase assert cso.clock_divisor == 2 assert cso.slave_select == 0x10 yield delay(10) raise StopSimulation return tbdut, tbstim run_testbench(bench, args)
def spi_controller_top(clock, reset, sck, mosi, miso, ss): """SPI top-level for conversion testing""" glbl = Global(clock, reset) spibus = SPIBus(sck, mosi, miso, ss) fifobus = FIFOBus() cso = spi_controller.cso() cso.isstatic = True cfg_inst = cso.instances() spi_controller.debug = False spi_inst = spi_controller(glbl, spibus, fifobus, cso=cso) @always_comb def fifo_loopback(): fifobus.write_data.next = fifobus.read_data fifobus.write.next = fifobus.read_valid fifobus.read.next = not fifobus.empty return myhdl.instances()
def spi_controller_top(clock, sck, mosi, miso, ss): """SPI top-level for conversion testing""" glbl = Global(clock, reset) spibus = SPIBus(sck, mosi, miso, ss) fifobus = FIFOBus() cso = spi_controller.cso() cso.isstatic = True cfg_inst = cso.get_generators() spi_controller.debug = False spi_inst = spi_controller(glbl, spibus, fifobus, cso=cso) @always_comb def fifo_loopback(): fifobus.write_data.next = fifobus.read_data fifobus.write.next = fifobus.read_valid fifobus.read.next = not fifobus.empty reset_dly_cnt = Signal(intbv(0)[5:]) # software reset need for xula2 @always(clock.posedge) def reset_tst(): ''' For the first 4 clocks the reset is forced to lo for clock 6 to 31 the reset is set hi then the reset is lo ''' if (reset_dly_cnt < 31): reset_dly_cnt.next = reset_dly_cnt + 1 if (reset_dly_cnt <= 4): reset.next = 0 if (reset_dly_cnt >= 5): reset.next = 1 else: reset.next = 0 return myhdl.instances()
def test_spi_controller_cso(args=None): args = tb_default_args(args) clock = Clock(0, frequency=50e6) reset = Reset(0, active=1, isasync=False) glbl = Global(clock, reset) spibus = SPIBus() # a FIFOBus to push-pull data from the SPI controller fifobus = FIFOBus(width=8) # control-status object for the SPI controller cso = spi_controller.cso() spiee = SPIEEPROM() asserr = Signal(bool(0)) @myhdl.block def bench_spi_cso(): spi_controller.debug = True # enable debug monitors tbdut = spi_controller(glbl, spibus, fifobus, cso=cso) tbeep = spiee.process(clock, reset, spibus) tbclk = clock.gen(hticks=5) @instance def tbstim(): yield reset.pulse(33) yield delay(100) yield clock.posedge try: # enable the SPI core cso.enable.next = True cso.bypass_fifo.next = True cso.loopback.next = True # write to the transmit FIFO values = (0x02, 0x00, 0x00, 0x00, 0x55) for data in values: cso.tx_byte.next = data cso.tx_write.next = True yield clock.posedge cso.tx_write.next = False while cso.tx_fifo_count > 0: yield delay(100) while cso.rx_fifo_count < 5: yield delay(100) ii, nticks = 0, 0 while ii < len(values): if cso.rx_empty: cso.rx_read.next = False else: cso.rx_read.next = True if cso.rx_byte_valid: assert values[ii] == cso.rx_byte, \ "{:<4d}: data mismatch, {:02X} != {:02X}".format( ii, int(values[ii]), int(cso.rx_byte)) ii += 1 nticks = 0 yield clock.posedge, cso.rx_empty.posedge cso.rx_read.next = False if nticks > 30: raise TimeoutError nticks += 1 cso.rx_read.next = False yield clock.posedge except AssertionError as err: asserr.next = True print("@E: assertion {}".format(err)) yield delay(100) traceback.print_exc() raise err raise StopSimulation # monitor signals for debugging tx_write, rx_read = Signals(bool(0), 2) @always_comb def tbmon(): rx_read.next = cso.rx_read tx_write.next = cso.tx_write return tbdut, tbeep, tbclk, tbstim, tbmon run_testbench(bench_spi_cso, args=args)
from rhea.models.spi import SPIEEPROM from rhea.system import Global, Clock, Reset, Signals from rhea.system import Wishbone from rhea.system import FIFOBus from rhea.utils.test import run_testbench, tb_convert, tb_args, tb_default_args # global signals used by many clock = Clock(0, frequency=100e6) reset = Reset(0, active=1, isasync=True) glbl = Global(clock, reset) portmap = dict(glbl=glbl, spibus=SPIBus(), fifobus=FIFOBus(), cso=spi_controller.cso()) @myhdl.block def spi_controller_top(clock, reset, sck, mosi, miso, ss): """SPI top-level for conversion testing""" glbl = Global(clock, reset) spibus = SPIBus(sck, mosi, miso, ss) fifobus = FIFOBus() cso = spi_controller.cso() cso.isstatic = True cfg_inst = cso.instances() spi_controller.debug = False spi_inst = spi_controller(glbl, spibus, fifobus, cso=cso)
def test_spi_controller_cso(args=None): args = tb_default_args(args) clock = Clock(0, frequency=50e6) reset = Reset(0, active=1, async=False) glbl = Global(clock, reset) spibus = SPIBus() # a FIFOBus to push-pull data from the SPI controller fifobus = FIFOBus(size=16) # control-status object for the SPI controller cso = spi_controller.cso() spiee = SPIEEPROM() asserr = Signal(bool(0)) def bench_spi_cso(): spi_controller.debug = True # enable debug monitors tbdut = spi_controller(glbl, spibus, fifobus, cso=cso) tbeep = spiee.gen(clock, reset, spibus) tbclk = clock.gen(hticks=5) @instance def tbstim(): yield reset.pulse(33) yield delay(100) yield clock.posedge try: # enable the SPI core cso.enable.next = True cso.bypass_fifo.next = True cso.loopback.next = True # write to the transmit FIFO values = (0x02, 0x00, 0x00, 0x00, 0x55) for data in values: cso.tx_byte.next = data cso.tx_write.next = True yield clock.posedge cso.tx_write.next = False while cso.tx_fifo_count > 0: yield delay(100) while cso.rx_fifo_count < 5: yield delay(100) ii, nticks = 0, 0 while ii < len(values): if cso.rx_empty: cso.rx_read.next = False else: cso.rx_read.next = True if cso.rx_byte_valid: assert values[ii] == cso.rx_byte, \ "{:<4d}: data mismatch, {:02X} != {:02X}".format( ii, int(values[ii]), int(cso.rx_byte)) ii += 1 nticks = 0 yield clock.posedge, cso.rx_empty.posedge cso.rx_read.next = False if nticks > 30: raise TimeoutError nticks += 1 cso.rx_read.next = False yield clock.posedge except AssertionError as err: asserr.next = True print("@E: assertion {}".format(err)) yield delay(100) traceback.print_exc() raise err raise StopSimulation # monitor signals for debugging tx_write, rx_read = Signals(bool(0), 2) @always_comb def tbmon(): rx_read.next = cso.rx_read tx_write.next = cso.tx_write return tbdut, tbeep, tbclk, tbstim, tbmon run_testbench(bench_spi_cso, args=args)
from rhea.system import Global, Clock, Reset, Signals from rhea.system import Wishbone from rhea.system import FIFOBus from rhea.utils.test import run_testbench, tb_convert, tb_args, tb_default_args # global signals used by many clock = Clock(0, frequency=100e6) reset = Reset(0, active=1, async=True) glbl = Global(clock, reset) portmap = dict( glbl=glbl, spibus=SPIBus(), fifobus=FIFOBus(), cso=spi_controller.cso() ) def spi_controller_top(clock, sck, mosi, miso, ss): """SPI top-level for conversion testing""" glbl = Global(clock, reset) spibus = SPIBus(sck, mosi, miso, ss) fifobus = FIFOBus() cso = spi_controller.cso() cso.isstatic = True cfg_inst = cso.get_generators() spi_controller.debug = False spi_inst = spi_controller(glbl, spibus, fifobus, cso=cso)