def xula_vga( # ~~~[PORTS]~~~ vselect, hsync, vsync, red, green, blue, pxlen, active, clock, reset=None, # ~~~~[PARAMETERS]~~~~ # @todo: replace these parameters with a single VGATimingParameter resolution=(640, 480,), color_depth=(8, 8, 8,), refresh_rate=60, line_rate=31250 ): """ (arguments == ports) Arguments: vselect: Parameters: resolution: the video resolution color_depth: the color depth of a pixel, the number of bits for each color component in a pixel. refresh_rate: the refresh rate of the video """ # stub out reset if needed if reset is None: reset = ResetSignal(0, active=0, async=False) @always(clock.posedge) def reset_stub(): reset.next = not reset.active else: reset_stub = None # create the system-level signals, overwrite clock, reset glbl = Global(clock=clock, reset=reset) # VGA inteface vga = VGA() # assign the top-level ports to the VGA interface vga.assign( hsync=hsync, vsync=vsync, red=red, green=green, blue=blue, pxlen=pxlen, active=active ) # video memory interface vmem = VideoMemory(color_depth=color_depth) # color bar generation bar_inst = color_bars(glbl, vmem, resolution=resolution) # VGA driver vga_inst = vga_sync(glbl, vga, vmem, resolution=resolution) return myhdl.instances()
def mm_vgasys( # ~~~[PORTS]~~~ clock, reset, vselect, hsync, vsync, red, green, blue, pxlen, active, # ~~~~[PARAMETERS]~~~~ resolution=(640, 480), color_depth=(8, 8, 8), refresh_rate=60, line_rate=31250, ): # create the system-level signals, overwrite clock, reset glbl = Global(clock=clock, reset=reset) # VGA interface vga = VGA() vga.assign(hsync=hsync, vsync=vsync, red=red, green=green, blue=blue, pxlen=pxlen, active=active) # video memory interface vmem = VideoMemory(color_depth=color_depth) # instances of modules bar_inst = color_bars(glbl, vmem, resolution=resolution, color_depth=color_depth) vga_inst = vga_sync(glbl, vga, vmem, resolution=resolution, refresh_rate=refresh_rate, line_rate=line_rate) return myhdl.instances()
def mm_vgasys( # ~~~[PORTS]~~~ clock, reset, vselect, hsync, vsync, red, green, blue, pxlen, active, # ~~~~[PARAMETERS]~~~~ resolution=( 640, 480, ), color_depth=( 8, 8, 8, ), refresh_rate=60, line_rate=31250): # create the system-level signals, overwrite clock, reset glbl = Global(clock=clock, reset=reset) # VGA interface vga = VGA() vga.assign(hsync=hsync, vsync=vsync, red=red, green=green, blue=blue, pxlen=pxlen, active=active) # video memory interface vmem = VideoMemory(color_depth=color_depth) # instances of modules bar_inst = color_bars(glbl, vmem, resolution=resolution, color_depth=color_depth) vga_inst = vga_sync(glbl, vga, vmem, resolution=resolution, refresh_rate=refresh_rate, line_rate=line_rate) return myhdl.instances()
def test_xula_vga(args=None): args = tb_default_args(args) resolution = (64, 48,) refresh_rate = 60 line_rate = 31250 color_depth = (3, 4, 3,) clock = Clock(0, frequency=12e6) reset = Reset(0, active=1, async=False) glbl = Global(clock, reset) vga = VGA(color_depth=color_depth) vga_hsync, vga_vsync = Signals(bool(0), 2) vga_red, vga_green, vga_blue = Signals(intbv(0)[6:], 3) vselect = Signal(bool(0)) pxlen, active = Signals(bool(0), 2) @myhdl.block def bench(): tbdut = xula_vga( clock, reset, vselect, vga_hsync, vga_vsync, vga_red, vga_green, vga_blue, pxlen, active, resolution=resolution, color_depth=color_depth, refresh_rate=refresh_rate, line_rate=line_rate ) tbclk = clock.gen() mdl = VGADisplay(frequency=clock.frequency, resolution=resolution, refresh_rate=refresh_rate, line_rate=line_rate, color_depth=color_depth) tbmdl = mdl.process(glbl, vga) @instance def tbstim(): yield delay(100000) raise StopSimulation return tbdut, tbclk, tbmdl, tbstim # run the above stimulus, the above is not self checking it simply # verifies the code will simulate. run_testbench(bench, args=args) portmap = dict(vselect=vselect, hsync=vga_hsync, vsync=vga_vsync, red=vga_red, green=vga_green, blue=vga_blue, clock=clock) # convert the module, check for any conversion errors tb_convert(xula_vga, **portmap)
def xula_vga( # ~~~[PORTS]~~~ clock, reset, vselect, hsync, vsync, red, green, blue, pxlen, active, # ~~~~[PARAMETERS]~~~~ resolution=(640, 480,), color_depth=(10, 10, 10,), refresh_rate=60, line_rate=31250 ): """ """ # create the system-level signals, overwrite clock, reset glbl = Global(clock=clock, reset=reset) # VGA inteface vga = VGA() vga.assign( hsync=hsync, vsync=vsync, red=red, green=green, blue=blue, pxlen=pxlen, active=active ) # video memory interface vmem = VideoMemory() # color bar generation bar_inst = color_bars(glbl, vmem, resolution=resolution) # VGA driver vga_inst = vga_sync(glbl, vga, vmem, resolution=resolution) return myhdl.instances()
def mm_vgasys( # ~~~[PORTS]~~~ clock, reset, vselect, hsync, vsync, red, green, blue, pxlen, active, # ~~~~[PARAMETERS]~~~~ resolution=( 640, 480, ), color_depth=( 10, 10, 10, ), refresh_rate=60, line_rate=31250): # create the system-level signals, overwrite clock, reset glbl = Global(clock=clock, reset=reset) # VGA inteface vga = VGA(hsync=hsync, vsync=vsync, red=red, green=green, blue=blue, pxlen=pxlen, active=active) # video memory interface vmem = VideoMemory() # instances of modules gbar = m_color_bars(glbl, vmem, resolution=resolution) gvga = m_vga_sync(glbl, vga, vmem, resolution=resolution) return gvga, gbar
def tb_vgasys(args=None): if args is None: args = Namespace() resolution = (80, 60) line_rate = 4000 refresh_rate = 60 color_depth = (10, 10, 10) else: # @todo: retrieve these from ... resolution = args.resolution refresh_rate = args.refresh_rate line_rate = args.line_rate color_depth = args.color_depth clock = Clock(0, frequency=1e6) reset = Reset(0, active=0, async=False) vselect = Signal(bool(0)) # intergace to the VGA driver and emulated display vga = VGA(color_depth=color_depth) def _bench_vgasys(): # top-level VGA system tbdut = mm_vgasys(clock, reset, vselect, vga.hsync, vga.vsync, vga.red, vga.green, vga.blue, vga.pxlen, vga.active, resolution=resolution, color_depth=color_depth, refresh_rate=refresh_rate, line_rate=line_rate) # group global signals glbl = Global(clock=clock, reset=reset) # a display for each dut mvd = VGADisplay(frequency=clock.frequency, resolution=resolution, refresh_rate=refresh_rate, line_rate=line_rate, color_depth=color_depth) # connect VideoDisplay model to the VGA signals tbvd = mvd.process(glbl, vga) # clock generator tbclk = clock.gen() @instance def tbstim(): reset.next = reset.active yield delay(18) reset.next = not reset.active # Wait till a full screen has been updated while mvd.update_cnt < 3: yield delay(1000) print("display updates complete") time.sleep(1) # @todo: verify video system memory is correct! # @todo: (self checking!). Read one of the frame # @todo: png's and verify a couple bars are expected raise StopSimulation return tbclk, tbvd, tbstim, tbdut # run the verification simulation run_testbench(_bench_vgasys)
def zybo_vga( # Ports led, btn, vga_red, vga_grn, vga_blu, vga_hsync, vga_vsync, clock, reset=None, # Parameters resolution=(1280, 1024), color_depth=(5, 6, 5), refresh_rate=60, line_rate=64512): """ This is a VGA example for the Digilent Zybo board. Arguments (ports): led: the Zybo 4 LEDs btn: the Zybo 4 buttons vga_red: red bits vga_grn: green bits vga_blu: blue bits vga_hsync: horizontal sync vga_vsync: vertical sync Parameters: resolution: the monitor desired resolution color_depth: the number of bits per color refresh_rate: the monitor refresh rate line_rate: the monitor line rate Common configurations 600x480, 60 800x600, 60, 37880 1280x1024, 60, 64512 """ glbl = Global(clock=clock, reset=reset) # VGA interface vga = VGA(color_depth=color_depth) vga.assign( hsync=vga_hsync, vsync=vga_vsync, red=vga_red, green=vga_grn, blue=vga_blu, ) # video memory interface vmem = VideoMemory(resolution=resolution, color_depth=color_depth) # rhea.core instances bar_inst = color_bars(glbl, vmem, resolution=resolution, color_depth=color_depth) vga_inst = vga_sync(glbl, vga, vmem, resolution=resolution, refresh_rate=refresh_rate, line_rate=line_rate) bcnt = Signal(intbv(0, min=0, max=clock.frequency)) blink = Signal(bool(0)) nticks = int(clock.frequency - 1) @always(clock.posedge) def beh_blink(): if bcnt == nticks: bcnt.next = 0 blink.next = not blink else: bcnt.next = bcnt + 1 @always(clock.posedge) def beh_led(): led.next = concat("000", blink) return bar_inst, vga_inst, beh_blink, beh_led
def zybo_vga( # Ports led, btn, vga_red, vga_grn, vga_blu, vga_hsync, vga_vsync, clock, reset=None, # Parameters resolution=(1280, 1024), color_depth=(5, 6, 5), refresh_rate=60, line_rate=64512): """ This is a VGA example for the Digilent Zybo board. Arguments (ports): led: the Zybo 4 LEDs btn: the Zybo 4 buttons vga_red: red bits vga_grn: green bits vga_blu: blue bits vga_hsync: horizontal sync vga_vsync: vertical sync Parameters: resolution: the monitor desired resolution color_depth: the number of bits per color refresh_rate: the monitor refresh rate line_rate: the monitor line rate Common configurations 600x480, 60 800x600, 60, 37880 1280x1024, 60, 64512 """ glbl = Global(clock=clock, reset=reset) # VGA interface vga = VGA(color_depth=color_depth) vga.assign(hsync=vga_hsync, vsync=vga_vsync, red=vga_red, green=vga_grn, blue=vga_blu,) # video memory interface vmem = VideoMemory(resolution=resolution, color_depth=color_depth) # rhea.core instances bar_inst = color_bars(glbl, vmem, resolution=resolution, color_depth=color_depth) vga_inst = vga_sync(glbl, vga, vmem, resolution=resolution, refresh_rate=refresh_rate, line_rate=line_rate) bcnt = Signal(intbv(0, min=0, max=clock.frequency)) blink = Signal(bool(0)) nticks = int(clock.frequency-1) @always(clock.posedge) def beh_blink(): if bcnt == nticks: bcnt.next = 0 blink.next = not blink else: bcnt.next = bcnt + 1 @always(clock.posedge) def beh_led(): led.next = concat("000", blink) return bar_inst, vga_inst, beh_blink, beh_led
def test_zybo_vga(args=None): args = tb_default_args(args) resolution = ( 80, 60, ) refresh_rate = 60 line_rate = 31250 color_depth = ( 6, 6, 6, ) clock = Clock(0, frequency=125e6) glbl = Global(clock) vga = VGA(color_depth=color_depth) vga_hsync, vga_vsync = Signals(bool(0), 2) vga_red, vga_green, vga_blue = Signals(intbv(0)[6:], 3) led, btn = Signals(intbv(0)[4:], 2) @myhdl.block def bench(): tbdut = zybo_vga(led, btn, vga_red, vga_green, vga_blue, vga_hsync, vga_vsync, clock, resolution=resolution, color_depth=color_depth, refresh_rate=refresh_rate, line_rate=line_rate) tbclk = clock.gen() mdl = VGADisplay(frequency=clock.frequency, resolution=resolution, refresh_rate=refresh_rate, line_rate=line_rate, color_depth=color_depth) tbmdl = mdl.process(glbl, vga) @instance def tbstim(): yield delay(100000) raise StopSimulation return tbdut, tbclk, tbmdl, tbstim # run the above testbench, the above testbench doesn't functionally # verify anything only verifies basics. run_testbench(bench, args=args) # test conversion portmap = dict(led=led, btn=btn, vga_red=vga_red, vga_grn=vga_green, vga_blu=vga_blue, vga_hsync=vga_hsync, vga_vsync=vga_vsync, clock=clock) inst = zybo_vga(**portmap) tb_convert(inst)