def fifo_cdc(glbl, emesh_i, emesh_o):
"""
map the packet interfaces to the FIOF interface
"""
fifo_intf = FIFOBus(size=16, width=len(emesh_i.bits))
@always_comb
def rtl_assign():
wr.next = emesh_i.access and not fifo_intf.full
rd.next = not fifo_intf.empty and not emesh_i.wait
emesh_o.wait.next = fifo_intf.full
@always(emesh_o.clock.posedge)
def rtl_access():
if not emesh_i.wait:
emesh_o.access.next = fifo_intf.read
# assign signals ot the FIFO interface
fifo_intf.write_data = emesh_i.bits
fifo_intf.read_data = emesh_o.bits
g_fifo = cores.fifo.fifo_async(glbl.reset, emesh_i.clock,
emesh_o.clock, fifo_intf)
return rtl_assign, rtl_access, g_fifo
def fifo_short(clock, reset, clear, datain, src_rdy_i, dst_rdy_o, dataout,
src_rdy_o, dst_rdy_i):
wr = Signal(bool(0))
rd = Signal(bool(0))
args = Namespace(width=36, size=16, name='fifo_2clock_cascade')
fbus = FIFOBus(size=args.size, width=args.width)
# need to update the fbus refernces to reference the Signals in
# the module port list (function arguments).
fbus.write = wr
fbus.write_data = datain
fbus.read = rd
fbus.read_data = dataout
@always_comb
def rtl_assign1():
wr.next = src_rdy_i & dst_rdy_o
rd.next = dst_rdy_i & src_rdy_o
@always_comb
def rtl_assign2():
dst_rdy_o.next = not fbus.full
src_rdy_o.next = not fbus.empty
gfifo = fifo_fast(reset, clock, fbus)
return rtl_assign1, rtl_assign2, gfifo
def fifo_cdc(glbl, emesh_i, emesh_o):
"""
map the packet interfaces to the FIFO interface
"""
wr, rd = Signals(bool(0), 2)
fifo_intf = FIFOBus(width=len(emesh_i.bits))
@always_comb
def beh_assign():
wr.next = emesh_i.access and not fifo_intf.full
rd.next = not fifo_intf.empty and not emesh_i.wait
emesh_o.wait.next = fifo_intf.full
@always(emesh_o.clock.posedge)
def beh_access():
if not emesh_i.wait:
emesh_o.access.next = fifo_intf.read
# assign signals ot the FIFO interface
fifo_intf.write_data = emesh_i.bits
fifo_intf.read_data = emesh_o.bits
fifo_inst = cores.fifo.fifo_async(clock_write=emesh_i.clock,
clock_read=emesh_o.clock,
fifobus=fifo_intf,
reset=glbl.reset,
size=16)
return beh_assign, beh_access, fifo_inst
def fifo_short(clock, reset, clear,
datain, src_rdy_i, dst_rdy_o,
dataout, src_rdy_o, dst_rdy_i):
wr = Signal(bool(0))
rd = Signal(bool(0))
args = Namespace(width=36, size=16, name='fifo_2clock_cascade')
fbus = FIFOBus(size=args.size, width=args.width)
# need to update the fbus refernces to reference the Signals in
# the module port list (function arguments).
fbus.write = wr
fbus.write_data = datain
fbus.read = rd
fbus.read_data = dataout
@always_comb
def rtl_assign1():
wr.next = src_rdy_i & dst_rdy_o
rd.next = dst_rdy_i & src_rdy_o
@always_comb
def rtl_assign2():
dst_rdy_o.next = not fbus.full
src_rdy_o.next = not fbus.empty
gfifo = fifo_fast(reset, clock, fbus)
return rtl_assign1, rtl_assign2, gfifo
def fifo_cdc(glbl, emesh_i, emesh_o):
"""
map the packet interfaces to the FIFO interface
"""
wr, rd = Signals(bool(0), 2)
fifo_intf = FIFOBus(width=len(emesh_i.bits))
@always_comb
def beh_assign():
wr.next = emesh_i.access and not fifo_intf.full
rd.next = not fifo_intf.empty and not emesh_i.wait
emesh_o.wait.next = fifo_intf.full
@always(emesh_o.clock.posedge)
def beh_access():
if not emesh_i.wait:
emesh_o.access.next = fifo_intf.read
# assign signals ot the FIFO interface
fifo_intf.write_data = emesh_i.bits
fifo_intf.read_data = emesh_o.bits
fifo_inst = cores.fifo.fifo_async(
clock_write=emesh_i.clock, clock_read=emesh_o.clock,
fifobus=fifo_intf, reset=glbl.reset, size=16
)
return beh_assign, beh_access, fifo_inst
def fifo_cdc(glbl, emesh_i, emesh_o):
"""
map the packet interfaces to the FIOF interface
"""
fifo_intf = FIFOBus(size=16, width=len(emesh_i.bits))
@always_comb
def rtl_assign():
wr.next = emesh_i.access and not fifo_intf.full
rd.next = not fifo_intf.empty and not emesh_i.wait
emesh_o.wait.next = fifo_intf.full
@always(emesh_o.clock.posedge)
def rtl_access():
if not emesh_i.wait:
emesh_o.access.next = fifo_intf.read
# assign signals ot the FIFO interface
fifo_intf.write_data = emesh_i.bits
fifo_intf.read_data = emesh_o.bits
g_fifo = cores.fifo.fifo_async(glbl.reset, emesh_i.clock, emesh_o.clock,
fifo_intf)
return rtl_assign, rtl_access, g_fifo
def fifo_2clock_cascade(
wclk, # in: write side clock
datain, # in: write data
src_rdy_i, # in:
dst_rdy_o, # out:
space, # out: how many can be written
rclk, # in: read side clock
dataout, # out: read data
src_rdy_o, # out:
dst_rdy_i, # in:
occupied, # out: number in the fifo
reset, # in: system reset
):
wr = Signal(bool(0))
rd = Signal(bool(0))
dataout_d = Signal(intbv(0, min=dataout.min, max=dataout.max))
args = Namespace(width=36, size=128, name='fifo_2clock_cascade')
fbus = FIFOBus(size=args.size, width=args.width)
# need to update the fbus refernces to reference the Signals in
# the moudule port list (function arguments).
fbus.write = wr
fbus.write_data = datain
fbus.read = rd
fbus.read_data = dataout_d
@always_comb
def rtl_assign1():
wr.next = src_rdy_i & dst_rdy_o
rd.next = dst_rdy_i & src_rdy_o
@always_comb
def rtl_assign2():
dst_rdy_o.next = not fbus.full
src_rdy_o.next = not fbus.empty
# the original was a chain:
# m_fifo_fast (16)
# m_fifo_async (??)
# m_fifo_fast (16)
gfifo = fifo_async(reset, wclk, rclk, fbus)
# @todo: calculate space and occupied based on fbus.count
# @todo: the output is delayed two clock from the "read" strobe
# the m_fifo_async only has a delta of one (read valid strobe
# aligns with valid data). Need to delay the data one more
# clock cycle???
@always(rclk.posedge)
def rtl_delay():
dataout.next = dataout_d
return rtl_assign1, rtl_assign2, gfifo, rtl_delay
def fifo_2clock_cascade(
wclk, # in: write side clock
datain, # in: write data
src_rdy_i, # in:
dst_rdy_o, # out:
space, # out: how many can be written
rclk, # in: read side clock
dataout, # out: read data
src_rdy_o, # out:
dst_rdy_i, # in:
occupied, # out: number in the fifo
reset, # in: system reset
):
""" """
wr = Signal(bool(0))
rd = Signal(bool(0))
dataout_d = Signal(intbv(0, min=dataout.min, max=dataout.max))
args = Namespace(width=36, size=128, name='fifo_2clock_cascade')
fbus = FIFOBus(width=args.width)
# need to update the fbus references to reference the Signals in
# the module port list (function arguments).
fbus.write = wr
fbus.write_data = datain
fbus.read = rd
fbus.read_data = dataout_d
@always_comb
def beh_assign1():
wr.next = src_rdy_i & dst_rdy_o
rd.next = dst_rdy_i & src_rdy_o
@always_comb
def beh_assign2():
dst_rdy_o.next = not fbus.full
src_rdy_o.next = not fbus.empty
# the original was a chain:
# fifo_fast (16)
# fifo_async (??)
# fifo_fast (16)
fifo_inst = fifo_async(wclk, rclk, fbus, reset=reset, size=args.size)
# @todo: calculate space and occupied based on fbus.count
# @todo: the output is delayed two clock from the "read" strobe
# the m_fifo_async only has a delta of one (read valid strobe
# aligns with valid data). Need to delay the data one more
# clock cycle???
@always(rclk.posedge)
def beh_delay():
dataout.next = dataout_d
return myhdl.instances()