def mm_lt24lcdsys(clock, reset, lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn,
lcd_rdn, lcd_data):
"""
"""
# interfaces
glbl = Global(clock, reset)
lcd = LT24Interface()
resolution = lcd.resolution
color_depth = lcd.color_depth
refresh_rate = 60
vmem = VideoMemory(resolution=resolution, color_depth=color_depth)
# assign the ports to the interface
lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn, lcd_rdn, lcd_data)
# simulation mode, reduce the dead time between real-world ticks
# modules
tck_inst = glbl_timer_ticks(glbl, user_timer=16, tick_div=100)
bar_inst = color_bars(glbl,
vmem,
resolution=resolution,
color_depth=color_depth)
lcd_inst = lt24lcd(glbl, vmem, lcd)
return myhdl.instances()
def mm_vgasys(
# ~~~[PORTS]~~~
clock,
reset,
vselect,
hsync,
vsync,
red,
green,
blue,
pxlen,
active,
# ~~~~[PARAMETERS]~~~~
resolution=(
640,
480,
),
color_depth=(
8,
8,
8,
),
refresh_rate=60,
line_rate=31250):
# create the system-level signals, overwrite clock, reset
glbl = Global(clock=clock, reset=reset)
# VGA interface
vga = VGA()
vga.assign(hsync=hsync,
vsync=vsync,
red=red,
green=green,
blue=blue,
pxlen=pxlen,
active=active)
# video memory interface
vmem = VideoMemory(color_depth=color_depth)
# instances of modules
bar_inst = color_bars(glbl,
vmem,
resolution=resolution,
color_depth=color_depth)
vga_inst = vga_sync(glbl,
vga,
vmem,
resolution=resolution,
refresh_rate=refresh_rate,
line_rate=line_rate)
return myhdl.instances()
def regfilesys(clock, reset):
"""
"""
glbl = Global(clock, reset)
csrbus = AXI4Lite(glbl, data_width=32, address_width=32)
cio = Signal(intbv(0)[8:])
mminst = memmap_component(glbl, csrbus, cio)
return mminst
def catboard_blinky_host(clock, led, uart_tx, uart_rx):
"""
The LEDs are controlled from the RPi over the UART
to the FPGA.
"""
glbl = Global(clock, None)
ledreg = Signal(intbv(0)[8:])
# create the timer tick instance
tick_inst = glbl_timer_ticks(glbl, include_seconds=True)
# create the interfaces to the UART
fifobus = FIFOBus(width=8)
# create the memmap (CSR) interface
memmap = Barebone(glbl, data_width=32, address_width=32)
# create the UART instance.
uart_inst = uartlite(glbl,
fifobus,
serial_in=uart_rx,
serial_out=uart_tx,
fifosize=4)
# create the packet command instance
cmd_inst = command_bridge(glbl, fifobus, memmap)
@always_seq(clock.posedge, reset=None)
def beh_led_control():
memmap.done.next = not (memmap.write or memmap.read)
if memmap.write and memmap.mem_addr == 0x20:
ledreg.next = memmap.write_data
@always_comb
def beh_led_read():
if memmap.read and memmap.mem_addr == 0x20:
memmap.read_data.next = ledreg
else:
memmap.read_data.next = 0
# blink one of the LEDs
tone = Signal(intbv(0)[8:])
@always_seq(clock.posedge, reset=None)
def beh_assign():
if glbl.tick_sec:
tone.next = (~tone) & 0x1
led.next = ledreg | tone[5:]
return (tick_inst, uart_inst, cmd_inst, beh_led_control, beh_led_read,
beh_assign)
def bench_vgasys():
# top-level VGA system
tbdut = mm_vgasys(clock,
reset,
vselect,
vga.hsync,
vga.vsync,
vga.red,
vga.green,
vga.blue,
vga.pxlen,
vga.active,
resolution=resolution,
color_depth=color_depth,
refresh_rate=refresh_rate,
line_rate=line_rate)
# group global signals
glbl = Global(clock=clock, reset=reset)
# a display for each dut
mvd = VGADisplay(frequency=clock.frequency,
resolution=resolution,
refresh_rate=refresh_rate,
line_rate=line_rate,
color_depth=color_depth)
# connect VideoDisplay model to the VGA signals
tbvd = mvd.process(glbl, vga)
# clock generator
tbclk = clock.gen()
@instance
def tbstim():
reset.next = reset.active
yield delay(18)
reset.next = not reset.active
# Wait till a full screen has been updated
while mvd.update_cnt < 3:
yield delay(1000)
print("display updates complete")
time.sleep(1)
# @todo: verify video system memory is correct!
# @todo: (self checking!). Read one of the frame
# @todo: png's and verify a couple bars are expected
raise StopSimulation
return tbclk, tbvd, tbstim, tbdut
def test_uart(args=None):
# @todo: get numbytes from args
numbytes = 13
clock = Clock(0, frequency=12e6)
reset = Reset(0, active=0, isasync=True)
glbl = Global(clock, reset)
mdlsi, mdlso = Signal(bool(1)), Signal(bool(1))
uartmdl = UARTModel()
fifobus = FIFOBus()
@myhdl.block
def bench_uart():
tbmdl = uartmdl.process(glbl, mdlsi, mdlso)
tbdut = uartlite(glbl, fifobus, mdlso, mdlsi)
tbclk = clock.gen()
@always_comb
def tblpbk():
fifobus.read.next = not fifobus.empty
fifobus.write.next = fifobus.read_valid
fifobus.write_data.next = fifobus.read_data
@instance
def tbstim():
yield reset.pulse(33)
yield delay(1000)
yield clock.posedge
for ii in range(numbytes):
wb = randint(0, 255)
print("send {:02X}".format(wb))
uartmdl.write(wb)
timeout = ((clock.frequency / uartmdl.baudrate) * 40)
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise TimeoutError
print("received {:02X}".format(rb))
assert rb == wb, "{:02X} != {:02X}".format(rb, wb)
yield delay(100)
raise StopSimulation
return tbdut, tbmdl, tbclk, tblpbk, tbstim
run_testbench(bench_uart, args=args)
def led_blinker_top(clock, reset, leds, buttons):
glbl = Global(clock, reset)
csrbus = Barebone()
dbtns = Signal(buttons.val)
led_inst = led_blinker(glbl, csrbus, leds)
dbn_inst = button_debounce(glbl, buttons, dbtns)
btn_inst = button_controller(glbl, csrbus, dbtns)
# above all the components have been added, now build the
# register file (figures out addresses, etc) and then get
# the memory-mapped bus interconnect
csrbus.regfile_build()
bus_inst = csrbus.interconnect()
return myhdl.instances()
def test_uart_model(args=None):
# @todo: get numbytes from args
numbytes = 7
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, isasync=True)
glbl = Global(clock, reset)
si, so = Signal(bool(1)), Signal(bool(1))
uartmdl = UARTModel()
@myhdl.block
def bench_uart_model():
tbdut = uartmdl.process(glbl, si, so)
tbclk = clock.gen()
@always_comb
def tblpbk():
si.next = so
@instance
def tbstim():
yield reset.pulse(33)
yield delay(1000)
yield clock.posedge
for ii in range(numbytes):
wb = randint(0, 255)
print("send {:02X}".format(wb))
uartmdl.write(wb)
timeout = ((clock.frequency / uartmdl.baudrate) * 20)
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise TimeoutError
print("received {:02X}".format(rb))
assert rb == wb, "{:02X} != {:02X}".format(rb, wb)
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tblpbk, tbstim
run_testbench(bench_uart_model, args=args)
def test_register_file_bits():
global regfile
# top-level signals and interfaces
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
regbus = Wishbone(glbl)
@myhdl.block
def bench_regfile_bits():
tbdut = memmap_peripheral_bits(glbl, regbus, 0xAA)
tbor = regbus.interconnect()
tbmclk = clock.gen()
tbrclk = regbus.clk_i.gen()
asserr = Signal(bool(0))
@instance
def tbstim():
regfile.ok.next = True
try:
yield reset.pulse(111)
yield clock.posedge
yield clock.posedge
truefalse = True
yield regbus.writetrans(regfile.control.addr, 0x01)
for _ in range(100):
assert regfile.enable == truefalse
assert regfile.loop == (not truefalse)
yield regbus.readtrans(regfile.control.addr)
invertbits = ~intbv(regbus.get_read_data())[8:]
yield regbus.writetrans(regfile.control.addr, invertbits)
truefalse = not truefalse
yield clock.posedge
except AssertionError as err:
asserr.next = True
for _ in range(20):
yield clock.posedge
raise err
raise StopSimulation
return tbmclk, tbstim, tbdut, tbor, tbrclk
run_testbench(bench_regfile_bits)
def xula_vga(
# ~~~[PORTS]~~~
clock, reset, vselect,
hsync, vsync,
red, green, blue,
pxlen, active,
# ~~~~[PARAMETERS]~~~~
resolution=(640, 480,),
color_depth=(10, 10, 10,),
refresh_rate=60,
line_rate=31250
):
"""
"""
# create the system-level signals, overwrite clock, reset
glbl = Global(clock=clock, reset=reset)
# VGA inteface
vga = VGA()
vga.assign(
hsync=hsync, vsync=vsync,
red=red, green=green, blue=blue,
pxlen=pxlen, active=active
)
# video memory interface
vmem = VideoMemory()
# color bar generation
bar_inst = color_bars(glbl, vmem, resolution=resolution)
# VGA driver
vga_inst = vga_sync(glbl, vga, vmem, resolution=resolution)
return myhdl.instances()
def uart_blinky(clock, led, uart_tx, uart_rx):
"""
Uses UART module to control LEDs while blinking the first LED.
LEDs used are pins 0-7 on wing A.
Expected behavior after upload is that LED[0] blinks on/off.
When sending
0xDE 0x02 0x00 0x00 0x00 0x20 0x04 0xCA 0x00 0x00 0x00 0xFF
via serial connection, all LEDs should turn on.
For details about the message format see
/rhea/cores/memmap/command_bridge.py
"""
reset = ResetSignal(0, active=0, async=True)
glbl = Global(clock, reset)
ledreg = Signal(intbv(0)[8:])
# create the timer tick instance
tick_inst = glbl_timer_ticks(glbl, include_seconds=True)
# create the interfaces to the UART
fifobus = FIFOBus(width=8)
# create the memmap (CSR) interface
memmap = Barebone(glbl, data_width=32, address_width=32)
# create the UART instance.
uart_inst = uartlite(glbl,
fifobus,
serial_in=uart_rx,
serial_out=uart_tx,
fifosize=4)
# create the packet command instance
cmd_inst = command_bridge(glbl, fifobus, memmap)
@always_seq(clock.posedge, reset=reset)
def beh_led_control():
memmap.done.next = not (memmap.write or memmap.read)
if memmap.write and memmap.mem_addr == 0x20:
ledreg.next = memmap.write_data
@always_comb
def beh_led_read():
if memmap.read and memmap.mem_addr == 0x20:
memmap.read_data.next = ledreg
else:
memmap.read_data.next = 0
# blink one of the LEDs
tone = Signal(intbv(0)[8:])
reset_dly_cnt = Signal(intbv(0)[5:])
@always_seq(clock.posedge, reset=None)
def beh_assign():
if glbl.tick_sec:
tone.next = (~tone) & 0x1
led.next = ledreg | tone[5:]
@always(clock.posedge)
def reset_tst():
'''
For the first 4 clocks the reset is forced to lo
for clock 6 to 31 the reset is set hi
then the reset is lo
'''
if (reset_dly_cnt < 31):
reset_dly_cnt.next = reset_dly_cnt + 1
if (reset_dly_cnt <= 4):
reset.next = 1
if (reset_dly_cnt >= 5):
reset.next = 0
else:
reset.next = 1
return (tick_inst, cmd_inst, uart_inst, beh_led_control, beh_led_read,
beh_assign, reset_tst)
def bench_lt24lcd_driver():
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, isasync=False)
glbl = Global(clock, reset)
lcd = LT24Interface()
display = LT24LCDDisplay()
cmd = Signal(intbv(0)[8:])
datalen = Signal(intbv(0, min=0, max=lcd.number_of_pixels + 1))
data = Signal(intbv(0)[16:])
datasent = Signal(bool(0))
datalast = Signal(bool(0))
cmd_in_progress = Signal(bool(0))
tbdut = lt24lcd_driver(glbl,
lcd,
cmd,
datalen,
data,
datasent,
datalast,
cmd_in_progress,
maxlen=lcd.number_of_pixels)
gtck = glbl_timer_ticks(glbl, tick_div=100)
tbmdl = display.process(glbl, lcd)
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(111)
yield clock.posedge
# --------------------------------------------
# send a column write command
print("column write command")
cmd.next = 0x2A
bytes = [0, 0, 0, 239]
data.next = bytes[0]
datalen.next = 4
for ii in range(4):
yield datasent.posedge
data.next = bytes[ii + 1] if ii < 3 else 0
cmd.next = 0
yield cmd_in_progress.negedge
yield clock.posedge
# --------------------------------------------
# send a page address write command
print("page address write command")
cmd.next = 0x2B
bytes = [0, 0, 1, 0x3F]
data.next = bytes[0]
datalen.next = 4
for ii in range(4):
yield datasent.posedge
data.next = bytes[ii + 1] if ii < 3 else 0
cmd.next = 0
yield cmd_in_progress.negedge
yield clock.posedge
# --------------------------------------------
# write display memory, full update
print("display update")
cmd.next = 0x2C
data.next = randint(0, data.max - 1)
datalen.next = lcd.number_of_pixels
for ii in range(lcd.number_of_pixels):
yield datasent.posedge
data.next = randint(0, data.max - 1)
if (ii % 5000) == 0:
print("{} pixels xfer'd".format(ii))
cmd.next = 0
yield cmd_in_progress.negedge
yield clock.posedge
print("display update complete")
# --------------------------------------------
# @todo: verify the display received an image
yield delay(100)
raise StopSimulation
return myhdl.instances()
def test_sdram(args=None):
""" SDRAM controller testbench
"""
args = tb_default_args(args)
# @todo: get the number of address to test from argparse
num_addr = 100 # number of address to test
# internal clock
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, isasync=False)
# sdram clock
clock_sdram = Clock(0, frequency=100e6)
# interfaces to the modules
glbl = Global(clock=clock, reset=reset)
ixbus = Wishbone(glbl=glbl, data_width=32, address_width=32)
exbus = SDRAMInterface()
exbus.clk = clock_sdram
# Models
sdram = SDRAMModel(exbus) # model driven by model :)
max_addr = 2048 # @todo: add actual SDRAM memory size limit
max_data = 2**16 # @todo: add actual databus width
@myhdl.block
def bench_sdram():
"""
This test exercises a SDRAM controller ...
"""
tbmdl_sdm = sdram.process()
tbmdl_ctl = sdram_controller_model(exbus, ixbus)
# this test currently only exercises the models,
# insert a second SDRAMInterface to test an actual
# controller
# tbdut = sdram_sdr_controller(ibus, exbus)
tbclk = clock.gen(hticks=10*1000)
tbclk_sdram = clock_sdram.gen(hticks=5*1000)
@instance
def tbstim():
reset.next = reset.active
yield delay(18000)
reset.next = not reset.active
# test a bunch of random addresses
try:
saved_addr_data = {}
for ii in range(num_addr):
# get a random address and random data, save the address and data
addr = randint(0, max_addr-1)
data = randint(0, max_data-1)
saved_addr_data[addr] = data
yield ixbus.writetrans(addr, data)
yield ixbus.readtrans(addr)
read_data = ixbus.get_read_data()
assert read_data == data, "{:08X} != {:08X}".format(read_data, data)
yield delay(20*1000)
# verify all the addresses have the last written data
for addr, data in saved_addr_data.items():
yield ixbus.readtrans(addr)
read_data = ixbus.get_read_data()
assert read_data == data
yield clock.posedge
for ii in range(10):
yield delay(1000)
except AssertionError as err:
# if test check fails about let the simulation run more cycles,
# useful for debug
yield delay(20000)
raise err
raise StopSimulation
return tbclk, tbclk_sdram, tbstim, tbmdl_sdm, tbmdl_ctl
run_testbench(bench_sdram, timescale='1ps')
def test_register_file(args=None):
global regfile
args = tb_default_args(args)
# top-level signals and interfaces
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
regbus = Wishbone(glbl)
@myhdl.block
def bench_regfile():
tbdut = memmap_peripheral(glbl, regbus, 0xAA)
tbor = regbus.interconnect()
tbmclk = clock.gen(hticks=5)
asserr = Signal(bool(0))
mon_ack = Signal(bool(0))
@always_comb
def tbmon():
mon_ack.next = regbus.ack_o
regdef = regfile.get_regdef()
@instance
def tbstim():
try:
yield delay(100)
yield reset.pulse(110)
yield clock.posedge
for k, reg in regdef.items():
if reg.access == 'ro':
yield regbus.readtrans(reg.addr)
rval = regbus.get_read_data()
assert rval == reg.default, \
"ro: {:02x} != {:02x}".format(rval, reg.default)
else:
wval = randint(0, (2**reg.width) - 1)
yield regbus.writetrans(reg.addr, wval)
for _ in range(4):
yield clock.posedge
yield regbus.readtrans(reg.addr)
rval = regbus.get_read_data()
assert rval == wval, \
"rw: {:02x} != {:02x} @ {:04X}".format(
rval, wval, reg.addr)
yield delay(100)
except AssertionError as err:
print("@E: %s".format(err))
traceback.print_exc()
asserr.next = True
for _ in range(10):
yield clock.posedge
raise err
raise StopSimulation
return tbmclk, tbstim, tbdut, tbmon, tbor
run_testbench(bench_regfile, args=args)
int(irx.full),
int(irx.empty),
))
@always(clock.posedge)
def mon_tx_fifo_write():
if itx.write:
print(" WRITE tx fifo {:02X}".format(int(itx.write_data)))
if itx.read:
print(" READ tx fifo {:02X}".format(int(itx.read_data)))
@always(clock.posedge)
def mon_rx_fifo_write():
if irx.write:
print(" WRITE rx fifo {:02X}".format(int(irx.write_data)))
if irx.read:
print(" READ rx fifo {:02X}".format(int(irx.read_data)))
# return the myhdl generators and instances
return myhdl.instances()
spi_controller.debug = False
spi_controller.cso = ControlStatus
spi_controller.portmap = dict(glbl=Global(),
spibus=SPIBus(),
fifobus=FIFOBus(),
cso=spi_controller.cso())
def peripheral_top(clock, reset, mon):
glbl = Global(clock, reset)
wb = Wishbone(glbl)
inst = memmap_peripheral(glbl, wb, mon)
return inst
def test_memmap_command_bridge(args=None):
nloops = 37
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
fifobus = FIFOBus()
memmap = Barebone(glbl, data_width=32, address_width=28)
fifobus.clock = clock
@myhdl.block
def bench_command_bridge():
tbclk = clock.gen()
tbdut = command_bridge(glbl, fifobus, memmap)
readpath, writepath = FIFOBus(), FIFOBus()
readpath.clock = writepath.clock = clock
tbmap = fifobus.assign_read_write_paths(readpath, writepath)
tbftx = fifo_fast(glbl, writepath) # user write path
tbfrx = fifo_fast(glbl, readpath) # user read path
# @todo: add other bus types
tbmem = memmap_peripheral_bb(clock, reset, memmap)
# save the data read ...
read_value = []
@instance
def tbstim():
yield reset.pulse(32)
fifobus.read.next = False
fifobus.write.next = False
assert not fifobus.full
assert fifobus.empty
assert fifobus.read_data == 0
fifobus.write_data.next = 0
try:
# test a single address
pkt = CommandPacket(True, 0x0000)
yield pkt.put(readpath)
yield pkt.get(writepath, read_value, [0])
pkt = CommandPacket(False, 0x0000, [0x5555AAAA])
yield pkt.put(readpath)
yield pkt.get(writepath, read_value, [0x5555AAAA])
# test a bunch of random addresses
for ii in range(nloops):
randaddr = randint(0, (2**20)-1)
randdata = randint(0, (2**32)-1)
pkt = CommandPacket(False, randaddr, [randdata])
yield pkt.put(readpath)
yield pkt.get(writepath, read_value, [randdata])
except Exception as err:
print("Error: {}".format(str(err)))
traceback.print_exc()
yield delay(2000)
raise StopSimulation
wp_read, wp_valid = Signals(bool(0), 2)
wp_read_data = Signal(intbv(0)[8:])
wp_empty, wp_full = Signals(bool(0), 2)
@always_comb
def tbmon():
wp_read.next = writepath.read
wp_read_data.next = writepath.read_data
wp_valid.next = writepath.read_valid
wp_full.next = writepath.full
wp_empty.next = writepath.empty
return tbclk, tbdut, tbmap, tbftx, tbfrx, tbmem, tbstim, tbmon
run_testbench(bench_command_bridge, args=args)
def doublefifo(clock, reset, dfifo_bus, buffer_sel, depth=16):
"""
I/O ports:
dfifo_bus : A FIFOBus connection interace
buffer_sel : select a buffer
Constants :
depth : depth of the fifo used
width_data : width of the data to be stored in FIFO
"""
# width of the input data
width_data = len(dfifo_bus.write_data)
# input to both the FIFO's
fifo_data_in = Signal(intbv(0)[width_data:])
# FIFOBus instantiation from rhea
glbl = Global(clock, reset)
fbus1 = FIFOBus(width=width_data)
fbus2 = FIFOBus(width=width_data)
assert isinstance(glbl, Global)
assert isinstance(fbus1, FIFOBus)
assert isinstance(fbus2, FIFOBus)
# instantiate two sync FIFO's
fifo_sync1 = fifo_sync(glbl, fbus1, depth)
fifo_sync2 = fifo_sync(glbl, fbus2, depth)
@always_comb
def assign():
"""write data into FIFO's"""
fbus1.write_data.next = fifo_data_in
fbus2.write_data.next = fifo_data_in
@always_seq(clock.posedge, reset=reset)
def mux2_logic():
"""select buffer to pump data"""
if not buffer_sel:
fbus1.write.next = dfifo_bus.write
else:
fbus2.write.next = dfifo_bus.write
fifo_data_in.next = dfifo_bus.write_data
@always_comb
def logic():
"""read or write into buffer"""
fbus1.read.next = dfifo_bus.read if (
buffer_sel) else False
fbus2.read.next = dfifo_bus.read if (
not buffer_sel) else False
dfifo_bus.read_data.next = fbus1.read_data if (
buffer_sel) else fbus2.read_data
dfifo_bus.empty.next = fbus1.empty if (
buffer_sel) else fbus2.empty
return (
fifo_sync1, fifo_sync2, assign, mux2_logic, logic)
def atlys_blinky_host(clock, reset, led, sw, pmod, uart_tx, uart_rx):
"""
This example is similar to the other examples in this directory but
the LEDs are controlled externally via command packets sent from a
host via the UART on the icestick.
"""
glbl = Global(clock, reset)
ledreg = Signal(intbv(0)[8:])
# create the timer tick instance
tick_inst = glbl_timer_ticks(glbl, include_seconds=True)
# create the interfaces to the UART
fifobus = FIFOBus(width=8)
# create the memmap (CSR) interface
memmap = Barebone(glbl, data_width=32, address_width=32)
# create the UART instance, cmd_tx is an internal loopback
# for testing (see below)
cmd_tx = Signal(bool(0))
uart_inst = uartlite(glbl, fifobus, uart_rx, cmd_tx)
# create the packet command instance
cmd_inst = command_bridge(glbl, fifobus, memmap)
@always_seq(clock.posedge, reset=reset)
def beh_led_control():
memmap.done.next = not (memmap.write or memmap.read)
if memmap.write and memmap.mem_addr == 0x20:
ledreg.next = memmap.write_data
@always_comb
def beh_led_read():
if memmap.read and memmap.mem_addr == 0x20:
memmap.read_data.next = ledreg
else:
memmap.read_data.next = 0
# blink one of the LEDs
status = [Signal(bool(0)) for _ in range(8)]
statusbv = ConcatSignal(*reversed(status))
@always_seq(clock.posedge, reset=reset)
def beh_assign():
# status / debug signals
if glbl.tick_sec:
status[0].next = not status[0]
status[1].next = memmap.mem_addr == 0x20
status[2].next = uart_rx
status[3].next = uart_tx
led.next = ledreg | statusbv | sw
pmod.next = 0
if sw[0]:
uart_tx.next = uart_rx
else:
uart_tx.next = cmd_tx
# @todo: PMOD OLED memmap control
return (tick_inst, uart_inst, cmd_inst, beh_led_control, beh_led_read,
beh_assign)
