def main():
c_pci_data_width = 128 # PCIe lane width
ptrsize = 64 # pointer size of the host system, 32 bit or 64 bit
wordsize = 32 # width of data port to design (any power of 2)
num_chnls = 4 # Virtmem takes 2 channels, add more for direct use, plus last one for loopback "are you there?" test
combined_interface_tx = riffa.Interface(data_width=c_pci_data_width, num_chnls=num_chnls)
combined_interface_rx = riffa.Interface(data_width=c_pci_data_width, num_chnls=num_chnls)
m = DesignTemplate(combined_interface_rx=combined_interface_rx, combined_interface_tx=combined_interface_tx, c_pci_data_width=c_pci_data_width, wordsize=wordsize, ptrsize=ptrsize)
# add a loopback to test responsiveness
test_rx, test_tx = m.get_channel(num_chnls - 1)
m.comb += test_rx.connect(test_tx)
m.cd_sys.clk.name_override="clk"
m.cd_sys.rst.name_override="rst"
for name in "ack", "last", "len", "off", "data", "data_valid", "data_ren":
getattr(combined_interface_rx, name).name_override="chnl_rx_{}".format(name)
getattr(combined_interface_tx, name).name_override="chnl_tx_{}".format(name)
combined_interface_rx.start.name_override="chnl_rx"
combined_interface_tx.start.name_override="chnl_tx"
m.rx_clk.name_override="chnl_rx_clk"
m.tx_clk.name_override="chnl_tx_clk"
print(verilog.convert(m, name="top", ios={getattr(combined_interface_rx, name) for name in ["start", "ack", "last", "len", "off", "data", "data_valid", "data_ren"]} | {getattr(combined_interface_tx, name) for name in ["start", "ack", "last", "len", "off", "data", "data_valid", "data_ren"]} | {m.rx_clk, m.tx_clk, m.cd_sys.clk, m.cd_sys.rst} ))
def __init__(self):
c_pci_data_width = 128
num_chnls = 3
self.wordsize = 32
self.ptrsize = 64
combined_interface_tx = riffa.Interface(data_width=c_pci_data_width,
num_chnls=num_chnls)
combined_interface_rx = riffa.Interface(data_width=c_pci_data_width,
num_chnls=num_chnls)
# instantiate test "memory" module that responds to page fetch/writeback requests
self.submodules.channelsplitter = riffa.ChannelSplitter(
combined_interface_tx, combined_interface_rx)
tx0, rx0 = self.channelsplitter.get_channel(0)
tx1, rx1 = self.channelsplitter.get_channel(1)
self.submodules.tbmem = TBMemory(tx0,
rx0,
tx1,
rx1,
c_pci_data_width=c_pci_data_width,
init_fn=generate_data)
# instantiate design under test
self.submodules.dut = count.Count(
combined_interface_rx=combined_interface_rx,
combined_interface_tx=combined_interface_tx,
c_pci_data_width=c_pci_data_width,
wordsize=self.wordsize,
ptrsize=self.ptrsize,
drive_clocks=False)
# channel to send args / receive results
# remember rx/tx from FPGA side -> write to rx, read from tx
self.tx, self.rx = self.channelsplitter.get_channel(2)
def __init__(self):
self.c_pci_data_width = c_pci_data_width = 128
self.ptrsize = 64
self.wordsize = 32
self.pagesize = 4096
num_chnls = 2
combined_interface_tx = riffa.Interface(data_width=c_pci_data_width,
num_chnls=num_chnls)
combined_interface_rx = riffa.Interface(data_width=c_pci_data_width,
num_chnls=num_chnls)
self.submodules.dut = virtmem.VirtmemWrapper(
combined_interface_rx=combined_interface_rx,
combined_interface_tx=combined_interface_tx,
c_pci_data_width=c_pci_data_width,
wordsize=self.wordsize,
ptrsize=self.ptrsize,
drive_clocks=False)
self.submodules.channelsplitter = riffa.ChannelSplitter(
combined_interface_tx, combined_interface_rx)
tx0, rx0 = self.channelsplitter.get_channel(0)
tx1, rx1 = self.channelsplitter.get_channel(1)
self.submodules.tbmem = TBMemory(tx0,
rx0,
tx1,
rx1,
c_pci_data_width=c_pci_data_width,
wordsize=self.wordsize,
ptrsize=self.ptrsize,
init_fn=generate_data_fn(
self.wordsize))
def __init__(self):
c_pci_data_width = 128
wordsize = 32
ptrsize = 64
npagesincache = 4
pagesize = 4096
memorywidth = max(c_pci_data_width, wordsize)
memorysize = npagesincache * pagesize * 8 // memorywidth
self.specials.mem = Memory(
memorywidth,
memorysize,
init=[i + 0xABBA for i in range(memorysize)])
self.specials.rd_port = rd_port = self.mem.get_port(has_re=True)
self.specials.wr_port = wr_port = self.mem.get_port(
write_capable=True, we_granularity=min(wordsize, c_pci_data_width))
num_chnls = 2
combined_interface_tx = riffa.Interface(data_width=c_pci_data_width,
num_chnls=num_chnls)
combined_interface_rx = riffa.Interface(data_width=c_pci_data_width,
num_chnls=num_chnls)
self.submodules.channelsplitter = riffa.ChannelSplitter(
combined_interface_tx, combined_interface_rx)
tx0, rx0 = self.channelsplitter.get_channel(0)
tx1, rx1 = self.channelsplitter.get_channel(1)
self.submodules.dut = PageTransferrer(
rx0,
tx0,
rx1,
tx1,
self.rd_port,
self.wr_port,
c_pci_data_width=c_pci_data_width,
wordsize=wordsize,
ptrsize=ptrsize,
npagesincache=npagesincache,
pagesize=pagesize)
self.submodules.tbmem = TBMemory(tx0,
rx0,
tx1,
rx1,
c_pci_data_width=c_pci_data_width)
def __init__(self): c_pci_data_width = 128 num_chnls = 3 combined_interface_tx = riffa.Interface(data_width=c_pci_data_width, num_chnls=num_chnls) combined_interface_rx = riffa.Interface(data_width=c_pci_data_width, num_chnls=num_chnls) self.submodules.dut = usercode.UserCode(combined_interface_rx=combined_interface_rx, combined_interface_tx=combined_interface_tx, c_pci_data_width=c_pci_data_width, drive_clocks=False) self.submodules.channelsplitter = riffa.ChannelSplitter(combined_interface_tx, combined_interface_rx) tx0, rx0 = self.channelsplitter.get_channel(0) tx1, rx1 = self.channelsplitter.get_channel(1) tx2, rx2 = self.channelsplitter.get_channel(2) data_to_send = [0x604000, 0x604004, 0x597a004, 0xfffe000, 0x8, 0x45600c, 0x604000, 0x604008] self.submodules.writer = Writer(rx2, data_to_send) self.submodules.reader = Reader(tx2, [generate_data(x) for x in data_to_send]) self.submodules.tbmem = TBMemory(tx0, rx0, tx1, rx1, c_pci_data_width=c_pci_data_width, init_fn=generate_data)
def main():
c_pci_data_width = 128
num_chnls = 4
combined_interface_tx = riffa.Interface(data_width=c_pci_data_width,
num_chnls=num_chnls)
combined_interface_rx = riffa.Interface(data_width=c_pci_data_width,
num_chnls=num_chnls)
m = Whoosh(combined_interface_rx=combined_interface_rx,
combined_interface_tx=combined_interface_tx,
c_pci_data_width=c_pci_data_width)
# add a loopback to test responsiveness
test_rx, test_tx = m.get_channel(num_chnls - 1)
m.comb += test_rx.connect(test_tx)
m.cd_sys.clk.name_override = "clk"
m.cd_sys.rst.name_override = "rst"
for name in "ack", "last", "len", "off", "data", "data_valid", "data_ren":
getattr(combined_interface_rx,
name).name_override = "chnl_rx_{}".format(name)
getattr(combined_interface_tx,
name).name_override = "chnl_tx_{}".format(name)
combined_interface_rx.start.name_override = "chnl_rx"
combined_interface_tx.start.name_override = "chnl_tx"
m.rx_clk.name_override = "chnl_rx_clk"
m.tx_clk.name_override = "chnl_tx_clk"
print(
verilog.convert(m,
name="top",
ios={
getattr(combined_interface_rx, name)
for name in [
"start", "ack", "last", "len", "off", "data",
"data_valid", "data_ren"
]
} | {
getattr(combined_interface_tx, name)
for name in [
"start", "ack", "last", "len", "off", "data",
"data_valid", "data_ren"
]
} | {m.rx_clk, m.tx_clk, m.cd_sys.clk, m.cd_sys.rst}))
def __init__(self):
c_pci_data_width = 128
num_chnls = 3
combined_interface_tx = riffa.Interface(data_width=c_pci_data_width,
num_chnls=num_chnls)
combined_interface_rx = riffa.Interface(data_width=c_pci_data_width,
num_chnls=num_chnls)
self.submodules.dut = whoosh.Whoosh(
combined_interface_rx=combined_interface_rx,
combined_interface_tx=combined_interface_tx,
c_pci_data_width=c_pci_data_width,
drive_clocks=False)
self.submodules.channelsplitter = riffa.ChannelSplitter(
combined_interface_tx, combined_interface_rx)
tx0, rx0 = self.channelsplitter.get_channel(0)
tx1, rx1 = self.channelsplitter.get_channel(1)
tx2, rx2 = self.channelsplitter.get_channel(2)
xy_range = 4096
self.data_to_send = [0x604000, xy_range]
self.results = [
functools.reduce(operator.xor, (generate_data((x + i) << 2)
for i in range(3)), 0)
for x in range(xy_range - 2)
] + [generate_data((xy_range - 2) << 2)
] + [generate_data((xy_range - 1) << 2)]
self.submodules.writer = Writer(rx2, self.data_to_send)
self.submodules.reader = Reader(tx2, [xy_range])
self.submodules.tbmem = TBMemory(tx0,
rx0,
tx1,
rx1,
c_pci_data_width=c_pci_data_width,
init_fn=generate_data)
def __init__(self): channel = riffa.Interface(data_width=128) dummy = Signal() self.comb += dummy.eq(channel.raw_bits()) self.submodules.writer = Writer(channel) self.submodules.reader = Reader(channel)
def __init__(self, c_pci_data_width=32, drive_clocks=True):
firorder = 7
wordsize = 32
self.chnl_rx_clk = Signal()
self.chnl_tx_clk = Signal()
self.chnl_rx = riffa.Interface(data_width=c_pci_data_width)
self.chnl_tx = riffa.Interface(data_width=c_pci_data_width)
###
if drive_clocks:
self.clock_domains.cd_sys = ClockDomain()
self.comb += self.chnl_rx_clk.eq(
self.cd_sys.clk), self.chnl_tx_clk.eq(self.cd_sys.clk)
rcount = Signal(32)
rcount_n = Signal(32)
rcount_en = Signal()
self.sync += If(rcount_en, rcount.eq(rcount_n))
tcount = Signal(32)
tcount_n = Signal(32)
tcount_en = Signal()
self.sync += If(tcount_en, tcount.eq(tcount_n))
rlen = Signal(32)
rlen_load = Signal()
self.sync += If(rlen_load, rlen.eq(self.chnl_rx.len))
rdata = Signal(c_pci_data_width)
self.sync += If(self.chnl_rx.data_valid, rdata.eq(self.chnl_rx.data))
fsm = FSM()
self.submodules += fsm
self.comb += self.chnl_tx.off.eq(0)
fsm.act(
"IDLE", rcount_n.eq(0), rcount_en.eq(1), tcount_n.eq(0),
tcount_en.eq(1),
If(self.chnl_rx.start, rlen_load.eq(1), NextState("RECEIVING")))
fsm.act(
"RECEIVING",
self.chnl_rx.ack.eq(1),
If(self.chnl_rx.data_valid,
rcount_n.eq(rcount + c_pci_data_width // wordsize),
rcount_en.eq(1), self.chnl_rx.data_ren.eq(1),
NextState("TRANSMITTING")),
)
fsm.act(
"TRANSMITTING",
#TODO: next test, split in 2 transactions of half length
self.chnl_tx.start.eq(1),
[
self.chnl_tx.data[i * wordsize:(i + 1) * wordsize].eq(tcount +
i + 1)
for i in range(c_pci_data_width // wordsize)
],
self.chnl_tx.len.eq(c_pci_data_width //
wordsize), #TODO: calculate if only 1 at end
self.chnl_tx.data_valid.eq(1),
self.chnl_tx.last.eq(1),
If(
self.chnl_tx.data_ren,
tcount_n.eq(tcount + c_pci_data_width // wordsize),
tcount_en.eq(1),
If(tcount >= rlen,
NextState("IDLE")).Else(NextState("RECEIVING"))))