def compile_synthesis_for_RASC(directives_map): """Compile the local VHDL files and extra RASC files to produce RASC bit file""" # ensure environment variables are set because we can call the compiled programs # without having to reference the entire path ROCCC_PY_LIB.check_env_vars([ ROCCC_PY_LIB.CONST_ENV_VAR_ROCCC_HOME, ROCCC_PY_LIB.CONST_ENV_VAR_XILINX, ROCCC_PY_LIB.CONST_ENV_VAR_RASC ]) last_dir = os.getcwd() # make ./synthesis_DIR if not os.path.isdir(SYNTHESIS_DIR): os.mkdir(SYNTHESIS_DIR) os.chdir(SYNTHESIS_DIR) ROCCC_PY_LIB.debug_print('CD to ' + SYNTHESIS_DIR) # make ./src directory if not os.path.isdir(SOURCE_DIR): os.mkdir(SOURCE_DIR) ROCCC_PY_LIB.debug_print('MKDIR: ' + SOURCE_DIR) top_entity_name = directives_map[TOP_ENTITY] ################### # Copy compilation files to local directory for easier compilation. # Create : # - ${top_entity_name}.prj (project files listing for XST) # - ${top_entity_name}.scr (script that list synthesis options for XST) # - Makefile, Makefile.local, alg.h, alg_block_top.v to local directory ################### # write the project files fout_prj = open(top_entity_name + '.prj', 'w') ################### if DO_RASC_XST: #### # the default RASC project options that were imported # change all references of $RASC to actual evironment variable pat_env_var_RASC = re.compile("\$RASC") for val in directives_map[PROJECT_OPTIONS]: val_out = pat_env_var_RASC.sub( os.environ[ROCCC_PY_LIB.CONST_ENV_VAR_RASC], val) fout_prj.write(val_out) #### # write alg_block_top.v fout_prj.write('verilog work ./src/alg_block_top.v\n') # by default alg-block.vhd and rc100.vhd for val in directives_map[VHDL_FILES_EXTRA]: fout_prj.write('vhdl work ./src/' + val + '\n') copy_files_to_dir(['../' + val], SOURCE_DIR) # the dp, buffer, and ROCCC_control.vhd and ROCCC_utility_lib for val in directives_map[VHDL_FILES_DEFAULT]: fout_prj.write('vhdl work ./src/' + val + '\n') ROCCC_PY_LIB.copy_files_to_dir(['../' + val], SOURCE_DIR) # WRITE XST script file to top_entity_name.scr fout_scr = open(top_entity_name + '.scr', 'w') for val in directives_map[SYNTHESIS_OPTIONS]: fout_scr.write(val) fout_scr.close() ################### elif DO_RASC_SYNPLIFY_PRO: fout_prj.write('set RASC [get_env RASC]\n') fout_prj.write('set THE_PWD [get_env PWD]\n') # FIXME, met it relative and see if works, otherwise absolute will have to do #fout_prj.write('set ALG_DIR ' + os.environ['PWD'] + '/SYNTHESIS_DIR/src\n') fout_prj.write('set ALG_DIR $THE_PWD/src\n') fout_prj.write( 'add_file -verilog "$RASC/design/alg_core/templates/user_space_wrapper.v"\n' ) fout_prj.write( 'add_file -verilog "$RASC/design/alg_core/templates/acs_adr.v"\n') fout_prj.write( 'add_file -verilog "$RASC/design/alg_core/templates/acs_debug_reg.v"\n' ) fout_prj.write('add_file -verilog "$ALG_DIR/alg_block_top.v"\n') for val in directives_map[VHDL_FILES_EXTRA]: fout_prj.write('add_file -vhdl "$ALG_DIR/' + val + '"\n') ROCCC_PY_LIB.copy_files_to_dir(['../' + val], SOURCE_DIR) # the dp, buffer, and ROCCC_control.vhd and ROCCC_utility_lib for val in directives_map[VHDL_FILES_DEFAULT]: fout_prj.write('add_file -vhdl "$ALG_DIR/' + val + '"\n') ROCCC_PY_LIB.copy_files_to_dir(['../' + val], SOURCE_DIR) for val in directives_map[PROJECT_OPTIONS]: val_out = val #pat_env_var_RASC.sub( os.environ[ROCCC_PY_LIB.CONST_ENV_VAR_RASC], val) fout_prj.write(val_out) ################### fout_prj.close() ##### # copy RASC default makefile, by parsing it and changing several options to good one: # make ucf -> make ucf_new (fix problem with reference to $RASC/implementations makefile_IN_filename = os.environ[ ROCCC_PY_LIB. CONST_ENV_VAR_RASC] + '/implementations/templates/Makefile' makefile_OUT_filename = './Makefile' ROCCC_PY_LIB.pattern_replace_and_copy_to_new_filepath( makefile_IN_filename, makefile_OUT_filename, [[ '\${RASC}/implementations/\${SYNTHESIS_PROJ}/\${SYNTHESIS_PROJ}.ucf', './${SYNTHESIS_PROJ}.ucf' ], ['python2.4', 'python']]) ##### # Set to EXPORT directory because I want user to be able to modify it for RASC #RASC_CUSTOM_LIB_PATH = os.environ[ROCCC_PY_LIB.CONST_ENV_VAR_ROCCC_HOME] + '/src/roccc_lib/vhdl_lib/RASC-specific' RASC_CUSTOM_LIB_PATH = '..' ##### # copy RASC makefile.local by parsing it and changing only the alg name makefile_local_IN_filename = RASC_CUSTOM_LIB_PATH + '/Makefile.local.RASC-SYNTHESIS' makefile_local_OUT_filename = './Makefile.local' if DO_RASC_XST: SYNTHESIS_RESULT_EXT = 'ngc' SYNTHESIS_TOOL = 'ise_xst' elif DO_RASC_SYNPLIFY_PRO: SYNTHESIS_RESULT_EXT = 'edf' SYNTHESIS_TOOL = 'synplify_pro' ROCCC_PY_LIB.pattern_replace_and_copy_to_new_filepath( makefile_local_IN_filename, makefile_local_OUT_filename, [['THE_DEFAULT_ALGORITHM_NAME', top_entity_name], ['THE_DEFAULT_SOURCE_DIR', SOURCE_DIR], ['THE_DEFAULT_SYNTHESIS_TOOL', SYNTHESIS_TOOL], ['THE_DEFAULT_SYNTHESIS_RESULT_EXT', SYNTHESIS_RESULT_EXT]]) ##### # copy over the extra files needed: alg.h, alg_block_top.v ROCCC_PY_LIB.copy_filepath_to_filepath( RASC_CUSTOM_LIB_PATH + '/alg_block_top.v', SOURCE_DIR + '/alg_block_top.v') ROCCC_PY_LIB.copy_filepath_to_filepath(RASC_CUSTOM_LIB_PATH + '/alg.h', SOURCE_DIR + '/alg.h') # don't do make all and copy files if not wanted if not DO_STOP_BEFORE_MAKE: ################### # EXECUTION ################### ROCCC_PY_LIB.execute_shell_cmd('make all') ################### # COPY RESULTS OUT ################### # copy out results (the RASC ./rev_1/${ENTITY_NAME}.bin, ./user_space.cfg, ./core_services.cfg) # to the ../RASC_EXPORT directory # append username for uniqueness of filenames, FIXME to add date+timestamp as well try: os.environ['USER'] THE_USERNAME = '******' + os.environ['USER'] except: THE_USERNAME = '' TOP_LEVEL_ENTITY_NAME = top_entity_name + THE_USERNAME ROCCC_PY_LIB.copy_files_to_dir( ['./user_space.cfg', './core_services.cfg'], RASC_EXPORT_DIR) ROCCC_PY_LIB.copy_filepath_to_filepath( './rev_1/' + top_entity_name + '.bin', RASC_EXPORT_DIR + '/' + TOP_LEVEL_ENTITY_NAME + '.bin') # copy Makefile for sgi-2 ROCCC_PY_LIB.pattern_replace_and_copy_to_new_filepath( RASC_CUSTOM_LIB_PATH + '/Makefile.C-COMPILE-SGI-2', RASC_EXPORT_DIR + '/Makefile', [['DEFAULT_ALGORITHM_NAME', TOP_LEVEL_ENTITY_NAME]]) # copy ../$HOST_CODE to $RASC_EXPORT_DIR/$HOST_CODE ROCCC_PY_LIB.pattern_replace_and_copy_to_new_filepath( RASC_CUSTOM_LIB_PATH + '/' + directives_map[HOST_C_SW], RASC_EXPORT_DIR + '/' + directives_map[HOST_C_SW], [['DEFAULT_ALGORITHM_NAME', TOP_LEVEL_ENTITY_NAME]])
RASC_CUSTOM_LIB_PATH + '/' + directives_map[HOST_C_SW], RASC_EXPORT_DIR + '/' + directives_map[HOST_C_SW], [['DEFAULT_ALGORITHM_NAME', TOP_LEVEL_ENTITY_NAME]]) # finished running make and copied files #### ########################################################### ### Begin program ######################################### ########################################################### if __name__ == "__main__": # set our script name ROCCC_PY_LIB.SCRIPT_NAME = 'VHDL2FGPA' directives_filename = parse_args() directives_map = read_directives(directives_filename) if DO_RASC: compile_synthesis_for_RASC(directives_map) else: compile_synthesis_manually(directives_map) ROCCC_PY_LIB.debug_print( '########################################################') ROCCC_PY_LIB.debug_print( '<<<<<< COMPILE LOCAL (VHDL TO FPGA) JOB END <<<<<<') ROCCC_PY_LIB.debug_print( '########################################################')
def compile_synthesis_manually(directives_map): """Compile manually the local VHDL files""" # ensure environment variables are set because we can call the compiled programs # without having to reference the entire path ROCCC_PY_LIB.check_env_vars([ROCCC_PY_LIB.CONST_ENV_VAR_XILINX]) last_dir = os.getcwd() if not os.path.isdir(SYNTHESIS_DIR): os.mkdir(SYNTHESIS_DIR) os.chdir(SYNTHESIS_DIR) top_entity_name = directives_map[TOP_ENTITY] # write the project files fout_prj = open(top_entity_name + '.prj', 'w') for val in directives_map[VHDL_FILES_DEFAULT]: fout_prj.write('vhdl work "../' + val + '"\n') fout_prj.close() fout_scr = open(top_entity_name + '.scr', 'w') for val in directives_map[SYNTHESIS_OPTIONS]: fout_scr.write(val) fout_scr.close() ############################## # run synthesis in this directory ############################## ##### XST COMPILATION #### # output is top_entity_name.ngc cmd_xst = 'xst -ifn' + SPACE + top_entity_name + '.scr' + SPACE + \ '-ofn' + SPACE + top_entity_name + '.syr' ROCCC_PY_LIB.execute_shell_cmd(cmd_xst) # Exit if only synthesis if DO_DEFAULT_SYNTHESIS_XST_ONLY == True: ROCCC_PY_LIB.debug_print('STOP AT XST SYNTHESIS') sys.exit(ERROR_NONE) ##### NGDBUILD COMPILATION #### # output is top_entity_name.ngd cmd_ngdbuild = 'ngdbuild ' + SPACE + top_entity_name + '.ngc' ROCCC_PY_LIB.execute_shell_cmd(cmd_ngdbuild) ##### MAP COMPILATION #### # output is top_entity_name.ncd, pcf ( pcf looks like a log file) cmd_map = 'map -p xc4vlx200-ff1513-10 -cm area -pr b -k 4 -c 100 ' + \ '-o' + SPACE + top_entity_name + '.ncd' + SPACE + \ top_entity_name + '.ngd' + SPACE + \ top_entity_name + '.pcf' ROCCC_PY_LIB.execute_shell_cmd(cmd_map) ##### PAR COMPILATION #### # -w means overwrite, should change cmd_par = 'par -w -ol std -t 1' + SPACE + \ top_entity_name + '.ncd' + SPACE + \ top_entity_name + '.ncd' + SPACE + \ top_entity_name + '.pcf' ROCCC_PY_LIB.execute_shell_cmd(cmd_par) ##### TRCE COMPILATION #### # -xml option needs top name, adds extension .twx automatically cmd_trce = 'trce -e 3 -s 10' + SPACE + \ '-xml' + SPACE + top_entity_name + SPACE + \ top_entity_name + '.ncd' + SPACE + \ '-o' + SPACE + top_entity_name + '.twr' + SPACE + \ top_entity_name + '.pcf' ROCCC_PY_LIB.execute_shell_cmd(cmd_trce) os.chdir(last_dir)
full_filename = args[0] # Take out prefix and split extension ext_temp = re.split('[.]',full_filename) hicirrf_filename_prefix = ext_temp[0] # split extension to determine ranges ext_range_temp = re.split(':', ext_temp[1]) if len(ext_range_temp) == 1: if ext_temp[1].upper() != 'C' : ROCCC_PY_LIB.error_print(ERROR_INVALID_RANGE, 'Invalid extension format, must be a *.c file if not defining a range') hicirrf_filename = full_filename ROCCC_PY_LIB.debug_print('ext = .c, hicirrf_filename = ' + hicirrf_filename) rangeL_int = START_RANGE rangeR_int = END_RANGE elif len(ext_range_temp) == 2: rangeL_str = ext_range_temp[0].upper() rangeR_str = ext_range_temp[1].upper() if pass_name_to_int_dict.has_key(rangeL_str): rangeL_int = pass_name_to_int_dict[rangeL_str] + 1 if pass_name_to_int_dict.has_key(rangeR_str): rangeR_int = pass_name_to_int_dict[rangeR_str]
# Take out prefix and split extension ext_temp = re.split('[.]', full_filename) hicirrf_filename_prefix = ext_temp[0] # split extension to determine ranges ext_range_temp = re.split(':', ext_temp[1]) if len(ext_range_temp) == 1: if ext_temp[1].upper() != 'C': ROCCC_PY_LIB.error_print( ERROR_INVALID_RANGE, 'Invalid extension format, must be a *.c file if not defining a range' ) hicirrf_filename = full_filename ROCCC_PY_LIB.debug_print('ext = .c, hicirrf_filename = ' + hicirrf_filename) rangeL_int = START_RANGE rangeR_int = END_RANGE elif len(ext_range_temp) == 2: rangeL_str = ext_range_temp[0].upper() rangeR_str = ext_range_temp[1].upper() if pass_name_to_int_dict.has_key(rangeL_str): rangeL_int = pass_name_to_int_dict[rangeL_str] + 1 if pass_name_to_int_dict.has_key(rangeR_str): rangeR_int = pass_name_to_int_dict[rangeR_str]
def compile_synthesis_for_RASC(directives_map): """Compile the local VHDL files and extra RASC files to produce RASC bit file""" # ensure environment variables are set because we can call the compiled programs # without having to reference the entire path ROCCC_PY_LIB.check_env_vars( [ROCCC_PY_LIB.CONST_ENV_VAR_ROCCC_HOME, ROCCC_PY_LIB.CONST_ENV_VAR_XILINX, ROCCC_PY_LIB.CONST_ENV_VAR_RASC] ) last_dir = os.getcwd() # make ./synthesis_DIR if not os.path.isdir(SYNTHESIS_DIR): os.mkdir(SYNTHESIS_DIR) os.chdir(SYNTHESIS_DIR) ROCCC_PY_LIB.debug_print("CD to " + SYNTHESIS_DIR) # make ./src directory if not os.path.isdir(SOURCE_DIR): os.mkdir(SOURCE_DIR) ROCCC_PY_LIB.debug_print("MKDIR: " + SOURCE_DIR) top_entity_name = directives_map[TOP_ENTITY] ################### # Copy compilation files to local directory for easier compilation. # Create : # - ${top_entity_name}.prj (project files listing for XST) # - ${top_entity_name}.scr (script that list synthesis options for XST) # - Makefile, Makefile.local, alg.h, alg_block_top.v to local directory ################### # write the project files fout_prj = open(top_entity_name + ".prj", "w") ################### if DO_RASC_XST: #### # the default RASC project options that were imported # change all references of $RASC to actual evironment variable pat_env_var_RASC = re.compile("\$RASC") for val in directives_map[PROJECT_OPTIONS]: val_out = pat_env_var_RASC.sub(os.environ[ROCCC_PY_LIB.CONST_ENV_VAR_RASC], val) fout_prj.write(val_out) #### # write alg_block_top.v fout_prj.write("verilog work ./src/alg_block_top.v\n") # by default alg-block.vhd and rc100.vhd for val in directives_map[VHDL_FILES_EXTRA]: fout_prj.write("vhdl work ./src/" + val + "\n") copy_files_to_dir(["../" + val], SOURCE_DIR) # the dp, buffer, and ROCCC_control.vhd and ROCCC_utility_lib for val in directives_map[VHDL_FILES_DEFAULT]: fout_prj.write("vhdl work ./src/" + val + "\n") ROCCC_PY_LIB.copy_files_to_dir(["../" + val], SOURCE_DIR) # WRITE XST script file to top_entity_name.scr fout_scr = open(top_entity_name + ".scr", "w") for val in directives_map[SYNTHESIS_OPTIONS]: fout_scr.write(val) fout_scr.close() ################### elif DO_RASC_SYNPLIFY_PRO: fout_prj.write("set RASC [get_env RASC]\n") fout_prj.write("set THE_PWD [get_env PWD]\n") # FIXME, met it relative and see if works, otherwise absolute will have to do # fout_prj.write('set ALG_DIR ' + os.environ['PWD'] + '/SYNTHESIS_DIR/src\n') fout_prj.write("set ALG_DIR $THE_PWD/src\n") fout_prj.write('add_file -verilog "$RASC/design/alg_core/templates/user_space_wrapper.v"\n') fout_prj.write('add_file -verilog "$RASC/design/alg_core/templates/acs_adr.v"\n') fout_prj.write('add_file -verilog "$RASC/design/alg_core/templates/acs_debug_reg.v"\n') fout_prj.write('add_file -verilog "$ALG_DIR/alg_block_top.v"\n') for val in directives_map[VHDL_FILES_EXTRA]: fout_prj.write('add_file -vhdl "$ALG_DIR/' + val + '"\n') ROCCC_PY_LIB.copy_files_to_dir(["../" + val], SOURCE_DIR) # the dp, buffer, and ROCCC_control.vhd and ROCCC_utility_lib for val in directives_map[VHDL_FILES_DEFAULT]: fout_prj.write('add_file -vhdl "$ALG_DIR/' + val + '"\n') ROCCC_PY_LIB.copy_files_to_dir(["../" + val], SOURCE_DIR) for val in directives_map[PROJECT_OPTIONS]: val_out = val # pat_env_var_RASC.sub( os.environ[ROCCC_PY_LIB.CONST_ENV_VAR_RASC], val) fout_prj.write(val_out) ################### fout_prj.close() ##### # copy RASC default makefile, by parsing it and changing several options to good one: # make ucf -> make ucf_new (fix problem with reference to $RASC/implementations makefile_IN_filename = os.environ[ROCCC_PY_LIB.CONST_ENV_VAR_RASC] + "/implementations/templates/Makefile" makefile_OUT_filename = "./Makefile" ROCCC_PY_LIB.pattern_replace_and_copy_to_new_filepath( makefile_IN_filename, makefile_OUT_filename, [ ["\${RASC}/implementations/\${SYNTHESIS_PROJ}/\${SYNTHESIS_PROJ}.ucf", "./${SYNTHESIS_PROJ}.ucf"], ["python2.4", "python"], ], ) ##### # Set to EXPORT directory because I want user to be able to modify it for RASC # RASC_CUSTOM_LIB_PATH = os.environ[ROCCC_PY_LIB.CONST_ENV_VAR_ROCCC_HOME] + '/src/roccc_lib/vhdl_lib/RASC-specific' RASC_CUSTOM_LIB_PATH = ".." ##### # copy RASC makefile.local by parsing it and changing only the alg name makefile_local_IN_filename = RASC_CUSTOM_LIB_PATH + "/Makefile.local.RASC-SYNTHESIS" makefile_local_OUT_filename = "./Makefile.local" if DO_RASC_XST: SYNTHESIS_RESULT_EXT = "ngc" SYNTHESIS_TOOL = "ise_xst" elif DO_RASC_SYNPLIFY_PRO: SYNTHESIS_RESULT_EXT = "edf" SYNTHESIS_TOOL = "synplify_pro" ROCCC_PY_LIB.pattern_replace_and_copy_to_new_filepath( makefile_local_IN_filename, makefile_local_OUT_filename, [ ["THE_DEFAULT_ALGORITHM_NAME", top_entity_name], ["THE_DEFAULT_SOURCE_DIR", SOURCE_DIR], ["THE_DEFAULT_SYNTHESIS_TOOL", SYNTHESIS_TOOL], ["THE_DEFAULT_SYNTHESIS_RESULT_EXT", SYNTHESIS_RESULT_EXT], ], ) ##### # copy over the extra files needed: alg.h, alg_block_top.v ROCCC_PY_LIB.copy_filepath_to_filepath(RASC_CUSTOM_LIB_PATH + "/alg_block_top.v", SOURCE_DIR + "/alg_block_top.v") ROCCC_PY_LIB.copy_filepath_to_filepath(RASC_CUSTOM_LIB_PATH + "/alg.h", SOURCE_DIR + "/alg.h") # don't do make all and copy files if not wanted if not DO_STOP_BEFORE_MAKE: ################### # EXECUTION ################### ROCCC_PY_LIB.execute_shell_cmd("make all") ################### # COPY RESULTS OUT ################### # copy out results (the RASC ./rev_1/${ENTITY_NAME}.bin, ./user_space.cfg, ./core_services.cfg) # to the ../RASC_EXPORT directory # append username for uniqueness of filenames, FIXME to add date+timestamp as well try: os.environ["USER"] THE_USERNAME = "******" + os.environ["USER"] except: THE_USERNAME = "" TOP_LEVEL_ENTITY_NAME = top_entity_name + THE_USERNAME ROCCC_PY_LIB.copy_files_to_dir(["./user_space.cfg", "./core_services.cfg"], RASC_EXPORT_DIR) ROCCC_PY_LIB.copy_filepath_to_filepath( "./rev_1/" + top_entity_name + ".bin", RASC_EXPORT_DIR + "/" + TOP_LEVEL_ENTITY_NAME + ".bin" ) # copy Makefile for sgi-2 ROCCC_PY_LIB.pattern_replace_and_copy_to_new_filepath( RASC_CUSTOM_LIB_PATH + "/Makefile.C-COMPILE-SGI-2", RASC_EXPORT_DIR + "/Makefile", [["DEFAULT_ALGORITHM_NAME", TOP_LEVEL_ENTITY_NAME]], ) # copy ../$HOST_CODE to $RASC_EXPORT_DIR/$HOST_CODE ROCCC_PY_LIB.pattern_replace_and_copy_to_new_filepath( RASC_CUSTOM_LIB_PATH + "/" + directives_map[HOST_C_SW], RASC_EXPORT_DIR + "/" + directives_map[HOST_C_SW], [["DEFAULT_ALGORITHM_NAME", TOP_LEVEL_ENTITY_NAME]], )
def compile_synthesis_manually(directives_map): """Compile manually the local VHDL files""" # ensure environment variables are set because we can call the compiled programs # without having to reference the entire path ROCCC_PY_LIB.check_env_vars([ROCCC_PY_LIB.CONST_ENV_VAR_XILINX]) last_dir = os.getcwd() if not os.path.isdir(SYNTHESIS_DIR): os.mkdir(SYNTHESIS_DIR) os.chdir(SYNTHESIS_DIR) top_entity_name = directives_map[TOP_ENTITY] # write the project files fout_prj = open(top_entity_name + ".prj", "w") for val in directives_map[VHDL_FILES_DEFAULT]: fout_prj.write('vhdl work "../' + val + '"\n') fout_prj.close() fout_scr = open(top_entity_name + ".scr", "w") for val in directives_map[SYNTHESIS_OPTIONS]: fout_scr.write(val) fout_scr.close() ############################## # run synthesis in this directory ############################## ##### XST COMPILATION #### # output is top_entity_name.ngc cmd_xst = "xst -ifn" + SPACE + top_entity_name + ".scr" + SPACE + "-ofn" + SPACE + top_entity_name + ".syr" ROCCC_PY_LIB.execute_shell_cmd(cmd_xst) # Exit if only synthesis if DO_DEFAULT_SYNTHESIS_XST_ONLY == True: ROCCC_PY_LIB.debug_print("STOP AT XST SYNTHESIS") sys.exit(ERROR_NONE) ##### NGDBUILD COMPILATION #### # output is top_entity_name.ngd cmd_ngdbuild = "ngdbuild " + SPACE + top_entity_name + ".ngc" ROCCC_PY_LIB.execute_shell_cmd(cmd_ngdbuild) ##### MAP COMPILATION #### # output is top_entity_name.ncd, pcf ( pcf looks like a log file) cmd_map = ( "map -p xc4vlx200-ff1513-10 -cm area -pr b -k 4 -c 100 " + "-o" + SPACE + top_entity_name + ".ncd" + SPACE + top_entity_name + ".ngd" + SPACE + top_entity_name + ".pcf" ) ROCCC_PY_LIB.execute_shell_cmd(cmd_map) ##### PAR COMPILATION #### # -w means overwrite, should change cmd_par = ( "par -w -ol std -t 1" + SPACE + top_entity_name + ".ncd" + SPACE + top_entity_name + ".ncd" + SPACE + top_entity_name + ".pcf" ) ROCCC_PY_LIB.execute_shell_cmd(cmd_par) ##### TRCE COMPILATION #### # -xml option needs top name, adds extension .twx automatically cmd_trce = ( "trce -e 3 -s 10" + SPACE + "-xml" + SPACE + top_entity_name + SPACE + top_entity_name + ".ncd" + SPACE + "-o" + SPACE + top_entity_name + ".twr" + SPACE + top_entity_name + ".pcf" ) ROCCC_PY_LIB.execute_shell_cmd(cmd_trce) os.chdir(last_dir)
# copy ../$HOST_CODE to $RASC_EXPORT_DIR/$HOST_CODE ROCCC_PY_LIB.pattern_replace_and_copy_to_new_filepath( RASC_CUSTOM_LIB_PATH + "/" + directives_map[HOST_C_SW], RASC_EXPORT_DIR + "/" + directives_map[HOST_C_SW], [["DEFAULT_ALGORITHM_NAME", TOP_LEVEL_ENTITY_NAME]], ) # finished running make and copied files #### ########################################################### ### Begin program ######################################### ########################################################### if __name__ == "__main__": # set our script name ROCCC_PY_LIB.SCRIPT_NAME = "VHDL2FGPA" directives_filename = parse_args() directives_map = read_directives(directives_filename) if DO_RASC: compile_synthesis_for_RASC(directives_map) else: compile_synthesis_manually(directives_map) ROCCC_PY_LIB.debug_print("########################################################") ROCCC_PY_LIB.debug_print("<<<<<< COMPILE LOCAL (VHDL TO FPGA) JOB END <<<<<<") ROCCC_PY_LIB.debug_print("########################################################")