def test_generate_arbitrators_simple(self):
"""the project file is supposed to generate one file"""
#read in the configuration file
config_file_name = os.getenv("SAPLIB_BASE") + "/example_project/arb_example.json"
try:
self.project.read_config_file(config_file_name, debug=self.dbg)
except TypeError as err:
print "Error reading JSON Config File: %s" % str(err)
self.assertEqual(True, False)
#read in the template
#if there is an error an assertion will be raised
self.project.read_template(self.project.project_tags["TEMPLATE"])
self.project.filegen.set_tags(self.project.project_tags)
#get the clock rate from the constraint file
board_dict = saputils.get_board_config("sycamore1")
cfiles = board_dict["default_constraint_files"]
self.project.project_tags["CLOCK_RATE"] = saputils.read_clock_rate(cfiles[0])
#generate the project directories and files
self.project.project_tags["BASE_DIR"] = "~/sandbox/test_syc"
saputils.create_dir(self.project.project_tags["BASE_DIR"])
#print "Parent dir: " + self.project.project_tags["BASE_DIR"]
for key in self.project.template_tags["PROJECT_TEMPLATE"]["files"]:
self.project.recursive_structure_generator(
self.project.template_tags["PROJECT_TEMPLATE"]["files"],
key,
self.project.project_tags["BASE_DIR"])
arb_tags = saparbitrator.generate_arbitrator_tags(self.project.project_tags)
self.project.project_tags["ARBITRATORS"] = arb_tags
result = self.project.generate_arbitrators(debug = self.dbg)
self.assertEqual(result, 1)
def test_generate_arbitrator_tags(self):
"""test if saparbitrator correctly determins if an arbitrator is requried"""
result = {}
tags = {}
#get the example project data
try:
filename = os.getenv("SAPLIB_BASE") + "/example_project/arb_example.json"
filein = open(filename)
filestr = filein.read()
tags = json.loads(filestr)
except IOError as err:
print "File Error: " + str(err)
self.assertEqual(False, True)
result = saparbitrator.generate_arbitrator_tags(tags, debug = self.dbg)
if (self.dbg):
for aslave in result.keys():
print "arbitrated slave: " + aslave
for master in result[aslave]:
print "\tmaster: " + master + " bus: " + result[aslave][master]
self.assertEqual((len(result.keys()) > 0), True)
def test_generate_arbitrator_tags(self):
"""test if saparbitrator correctly determins if an arbitrator is requried"""
result = {}
tags = {}
#get the example project data
try:
filename = os.getenv(
"SAPLIB_BASE") + "/example_project/arb_example.json"
filein = open(filename)
filestr = filein.read()
tags = json.loads(filestr)
except IOError as err:
print "File Error: " + str(err)
self.assertEqual(False, True)
result = saparbitrator.generate_arbitrator_tags(tags, debug=self.dbg)
if (self.dbg):
for aslave in result.keys():
print "arbitrated slave: " + aslave
for master in result[aslave]:
print "\tmaster: " + master + " bus: " + result[aslave][
master]
self.assertEqual((len(result.keys()) > 0), True)
def test_generate_arbitrators_simple(self):
"""the project file is supposed to generate one file"""
config_file_name = os.getenv("SAPLIB_BASE") + "/example_project/arb_example.json"
result = self.project.read_config_file(config_file_name)
self.assertEqual(result, True)
result = self.project.read_template(self.project.project_tags["TEMPLATE"])
self.assertEqual(result, True)
self.project.filegen.set_tags(self.project.project_tags)
#get the clock rate from the constraint file
self.project.project_tags["CLOCK_RATE"] = saputils.read_clock_rate(self.project.project_tags["CONSTRAINTS"]["constraint_files"][0])
#generate the project directories and files
self.project.project_tags["BASE_DIR"] = "~/sandbox/test_syc"
saputils.create_dir(self.project.project_tags["BASE_DIR"])
#print "Parent dir: " + self.project.project_tags["BASE_DIR"]
for key in self.project.template_tags["PROJECT_TEMPLATE"]["files"]:
self.project.recursive_structure_generator(
self.project.template_tags["PROJECT_TEMPLATE"]["files"],
key,
self.project.project_tags["BASE_DIR"])
arb_tags = saparbitrator.generate_arbitrator_tags(self.project.project_tags)
self.project.project_tags["ARBITRATORS"] = arb_tags
result = self.project.generate_arbitrators(debug = self.dbg)
self.assertEqual(result, 1)
def test_generate_arbitrators_difficult(self):
"""the project calls for three arbitrators, but two are identical"""
#read in the configuration file
config_file_name = os.getenv(
"SAPLIB_BASE") + "/example_project/arb_difficult_example.json"
result = False
try:
self.project.read_config_file(config_file_name, debug=self.dbg)
except TypeError as err:
print "Error reading JSON Config File: %s" % str(err)
self.assertEqual(True, False)
#this will throw an exception if something failed
self.project.read_template(self.project.project_tags["TEMPLATE"])
board_dict = saputils.get_board_config(
self.project.project_tags["board"])
cfiles = board_dict["default_constraint_files"]
self.project.filegen.set_tags(self.project.project_tags)
#get the clock rate from the constraint file
self.project.project_tags["CLOCK_RATE"] = saputils.read_clock_rate(
cfiles[0])
#generate the project directories and files
self.project.project_tags["BASE_DIR"] = "~/sandbox/test_syc"
saputils.create_dir(self.project.project_tags["BASE_DIR"])
#print "Parent dir: " + self.project.project_tags["BASE_DIR"]
for key in self.project.template_tags["PROJECT_TEMPLATE"]["files"]:
self.project.recursive_structure_generator(
self.project.template_tags["PROJECT_TEMPLATE"]["files"], key,
self.project.project_tags["BASE_DIR"])
arb_tags = saparbitrator.generate_arbitrator_tags(
self.project.project_tags)
self.project.project_tags["ARBITRATORS"] = arb_tags
result = self.project.generate_arbitrators(debug=self.dbg)
self.assertEqual(result, 2)
def test_generate_arbitrators_simple(self):
"""the project file is supposed to generate one file"""
#read in the configuration file
config_file_name = os.getenv(
"SAPLIB_BASE") + "/example_project/arb_example.json"
try:
self.project.read_config_file(config_file_name, debug=self.dbg)
except TypeError as err:
print "Error reading JSON Config File: %s" % str(err)
self.assertEqual(True, False)
#read in the template
#if there is an error an assertion will be raised
self.project.read_template(self.project.project_tags["TEMPLATE"])
self.project.filegen.set_tags(self.project.project_tags)
#get the clock rate from the constraint file
board_dict = saputils.get_board_config("sycamore1")
cfiles = board_dict["default_constraint_files"]
self.project.project_tags["CLOCK_RATE"] = saputils.read_clock_rate(
cfiles[0])
#generate the project directories and files
self.project.project_tags["BASE_DIR"] = "~/sandbox/test_syc"
saputils.create_dir(self.project.project_tags["BASE_DIR"])
#print "Parent dir: " + self.project.project_tags["BASE_DIR"]
for key in self.project.template_tags["PROJECT_TEMPLATE"]["files"]:
self.project.recursive_structure_generator(
self.project.template_tags["PROJECT_TEMPLATE"]["files"], key,
self.project.project_tags["BASE_DIR"])
arb_tags = saparbitrator.generate_arbitrator_tags(
self.project.project_tags)
self.project.project_tags["ARBITRATORS"] = arb_tags
result = self.project.generate_arbitrators(debug=self.dbg)
self.assertEqual(result, 1)
def test_generate_arbitrators_difficult(self):
"""the project calls for three arbitrators, but two are identical"""
#read in the configuration file
config_file_name = os.getenv("SAPLIB_BASE") + "/example_project/arb_difficult_example.json"
result = False
try:
self.project.read_config_file(config_file_name, debug=self.dbg)
except TypeError as err:
print "Error reading JSON Config File: %s" % str(err)
self.assertEqual(True, False)
#this will throw an exception if something failed
self.project.read_template(self.project.project_tags["TEMPLATE"])
board_dict = saputils.get_board_config(self.project.project_tags["board"])
cfiles = board_dict["default_constraint_files"]
self.project.filegen.set_tags(self.project.project_tags)
#get the clock rate from the constraint file
self.project.project_tags["CLOCK_RATE"] = saputils.read_clock_rate(cfiles[0])
#generate the project directories and files
self.project.project_tags["BASE_DIR"] = "~/sandbox/test_syc"
saputils.create_dir(self.project.project_tags["BASE_DIR"])
#print "Parent dir: " + self.project.project_tags["BASE_DIR"]
for key in self.project.template_tags["PROJECT_TEMPLATE"]["files"]:
self.project.recursive_structure_generator(
self.project.template_tags["PROJECT_TEMPLATE"]["files"],
key,
self.project.project_tags["BASE_DIR"])
arb_tags = saparbitrator.generate_arbitrator_tags(self.project.project_tags)
self.project.project_tags["ARBITRATORS"] = arb_tags
result = self.project.generate_arbitrators(debug = self.dbg)
self.assertEqual(result, 2)
def generate_arbitrator_buffer(self, debug=False):
result = ""
board_dict = saputils.get_board_config(self.tags["board"])
invert_reset = board_dict["invert_reset"]
#self.wires
arbitrator_count = 0
if (not saparbitrator.is_arbitrator_required(self.tags)):
return ""
if debug:
print "arbitration is required"
result += "//Project Arbitrators\n\n"
arb_tags = saparbitrator.generate_arbitrator_tags(self.tags)
for i in range(0, len(arb_tags.keys())):
arb_slave = arb_tags.keys()[i]
master_count = 1
arb_name = ""
if debug:
print "found arbitrated slave: " + arb_slave
result += "//" + arb_slave + " arbitrator\n\n"
master_count += len(arb_tags[arb_slave].keys())
arb_name = "arb" + str(i)
arb_module = "arbitrator_" + str(master_count) + "_masters"
if debug:
print "number of masters for this arbitrator: " + str(
master_count)
print "using: " + arb_module
print "arbitrator name: " + arb_name
#generate the wires
for mi in range(0, master_count):
wbm_name = ""
if (mi == 0):
#these wires are taken care of by the interconnect
continue
else:
master_name = arb_tags[arb_slave].keys()[mi - 1]
bus_name = arb_tags[arb_slave][master_name]
wbm_name = master_name + "_" + bus_name
#strobe
wire = wbm_name + "_stb_o"
if (not (wire in self.wires)):
result += "\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#cycle
wire = wbm_name + "_cyc_o"
if (not (wire in self.wires)):
result += "\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#write enable
wire = wbm_name + "_we_o"
if (not (wire in self.wires)):
result += "\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#select
wire = wbm_name + "_sel_o"
if (not (wire in self.wires)):
result += "\twire\t[3:0]\t" + wire + ";\n"
self.wires.append(wire)
#in data
wire = wbm_name + "_dat_o"
if (not (wire in self.wires)):
result += "\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#out data
wire = wbm_name + "_dat_i"
if (not (wire in self.wires)):
result += "\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#address
wire = wbm_name + "_adr_o"
if (not (wire in self.wires)):
result += "\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#acknowledge
wire = wbm_name + "_ack_i"
if (not (wire in self.wires)):
result += "\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#interrupt
wire = wbm_name + "_int_i"
if (not (wire in self.wires)):
result += "\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#generate arbitrator signals
#strobe
wire = arb_name + "_wbs_stb_i"
if (not (wire in self.wires)):
result += "\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#cycle
wire = arb_name + "_wbs_cyc_i"
if (not (wire in self.wires)):
result += "\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#write enable
wire = arb_name + "_wbs_we_i"
if (not (wire in self.wires)):
result += "\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#select
wire = arb_name + "_wbs_sel_i"
if (not (wire in self.wires)):
result += "\twire\t[3:0]\t" + wire + ";\n"
self.wires.append(wire)
#in data
wire = arb_name + "_wbs_dat_i"
if (not (wire in self.wires)):
result += "\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#out data
wire = arb_name + "_wbs_dat_o"
if (not (wire in self.wires)):
result += "\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#address
wire = arb_name + "_wbs_adr_i"
if (not (wire in self.wires)):
result += "\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#acknowledge
wire = arb_name + "_wbs_ack_o"
if (not (wire in self.wires)):
result += "\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#interrupt
wire = arb_name + "_wbs_int_o"
if (not (wire in self.wires)):
result += "\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
result += "\n\n"
#finished generating the wires
result += "\t" + arb_module + " " + arb_name + "(\n"
result += "\t\t.clk(clk),\n"
if invert_reset:
result += "\t\t.rst(rst_n),\n"
else:
result += "\t\t.rst(rst),\n"
result += "\n"
result += "\t\t//masters\n"
for mi in range(0, master_count):
wbm_name = ""
#last master is always from the interconnect
#XXX: This should really be a parameter, but this will alow slaves to take over a peripheral
if (mi == master_count - 1):
if debug:
print "mi: " + str(mi)
on_periph_bus = False
#in this case I need to use the wishbone interconnect
#search for the index of the slave
for i in range(0, len(self.tags["SLAVES"].keys())):
name = self.tags["SLAVES"].keys()[i]
if name == arb_slave:
interconnect_index = i + 1 # +1 to account for DRT
on_periph_bus = True
wbm_name = "s" + str(interconnect_index)
if debug:
print "arb slave on peripheral bus"
print "slave index: " + str(
interconnect_index - 1)
print "accounting for drt, actual bus index == " + str(
interconnect_index)
break
#check mem bus
if (not on_periph_bus):
if ("MEMORY" in self.tags.keys()):
#There is a memory bus, look in here
for i in range(0, len(self.tags["MEMORY"].keys())):
name = self.tags["MEMORY"].keys()[i]
if name == arb_slave:
mem_inc_index = i
wbm_name = "sm" + str(i)
if debug:
print "arb slave on mem bus"
print "slave index: " + str(
mem_inc_index)
break
result += "\t\t.m" + str(
mi) + "_stb_i(" + wbm_name + "_wbs_stb_i),\n"
result += "\t\t.m" + str(
mi) + "_cyc_i(" + wbm_name + "_wbs_cyc_i),\n"
result += "\t\t.m" + str(
mi) + "_we_i(" + wbm_name + "_wbs_we_i),\n"
result += "\t\t.m" + str(
mi) + "_sel_i(" + wbm_name + "_wbs_sel_i),\n"
result += "\t\t.m" + str(
mi) + "_dat_i(" + wbm_name + "_wbs_dat_i),\n"
result += "\t\t.m" + str(
mi) + "_adr_i(" + wbm_name + "_wbs_adr_i),\n"
result += "\t\t.m" + str(
mi) + "_dat_o(" + wbm_name + "_wbs_dat_o),\n"
result += "\t\t.m" + str(
mi) + "_ack_o(" + wbm_name + "_wbs_ack_o),\n"
result += "\t\t.m" + str(
mi) + "_int_o(" + wbm_name + "_wbs_int_o),\n"
result += "\n\n"
#not the last index
else:
if debug:
print "mi: " + str(mi)
master_name = arb_tags[arb_slave].keys()[mi]
bus_name = arb_tags[arb_slave][master_name]
wbm_name = master_name + "_" + bus_name
result += "\t\t.m" + str(
mi) + "_stb_i(" + wbm_name + "_stb_o),\n"
result += "\t\t.m" + str(
mi) + "_cyc_i(" + wbm_name + "_cyc_o),\n"
result += "\t\t.m" + str(
mi) + "_we_i(" + wbm_name + "_we_o),\n"
result += "\t\t.m" + str(
mi) + "_sel_i(" + wbm_name + "_sel_o),\n"
result += "\t\t.m" + str(
mi) + "_dat_i(" + wbm_name + "_dat_o),\n"
result += "\t\t.m" + str(
mi) + "_adr_i(" + wbm_name + "_adr_o),\n"
result += "\t\t.m" + str(
mi) + "_dat_o(" + wbm_name + "_dat_i),\n"
result += "\t\t.m" + str(
mi) + "_ack_o(" + wbm_name + "_ack_i),\n"
result += "\t\t.m" + str(
mi) + "_int_o(" + wbm_name + "_int_i),\n"
result += "\n\n"
result += "\t\t//slave\n"
result += "\t\t.s_stb_o(" + arb_name + "_wbs_stb_i),\n"
result += "\t\t.s_cyc_o(" + arb_name + "_wbs_cyc_i),\n"
result += "\t\t.s_we_o(" + arb_name + "_wbs_we_i),\n"
result += "\t\t.s_sel_o(" + arb_name + "_wbs_sel_i),\n"
result += "\t\t.s_dat_o(" + arb_name + "_wbs_dat_i),\n"
result += "\t\t.s_adr_o(" + arb_name + "_wbs_adr_i),\n"
result += "\t\t.s_dat_i(" + arb_name + "_wbs_dat_o),\n"
result += "\t\t.s_ack_i(" + arb_name + "_wbs_ack_o),\n"
result += "\t\t.s_int_i(" + arb_name + "_wbs_int_o)\n"
result += ");\n"
return result
def generate_arbitrator_buffer(self, debug = False):
result = ""
board_dict = saputils.get_board_config(self.tags["board"])
invert_reset = board_dict["invert_reset"]
#self.wires
arbitrator_count = 0
if (not saparbitrator.is_arbitrator_required(self.tags)):
return ""
if debug:
print "arbitration is required"
result += "//Project Arbitrators\n\n"
arb_tags = saparbitrator.generate_arbitrator_tags(self.tags)
for i in range (0, len(arb_tags.keys())):
arb_slave = arb_tags.keys()[i]
master_count = 1
arb_name = ""
if debug:
print "found arbitrated slave: " + arb_slave
result += "//" + arb_slave + " arbitrator\n\n"
master_count += len(arb_tags[arb_slave].keys())
arb_name = "arb" + str(i)
arb_module = "arbitrator_" + str(master_count) + "_masters"
if debug:
print "number of masters for this arbitrator: " + str(master_count)
print "using: " + arb_module
print "arbitrator name: " + arb_name
#generate the wires
for mi in range (0, master_count):
wbm_name = ""
if (mi == 0):
#these wires are taken care of by the interconnect
continue
else:
master_name = arb_tags[arb_slave].keys()[mi - 1]
bus_name = arb_tags[arb_slave][master_name]
wbm_name = master_name + "_" + bus_name
#strobe
wire = wbm_name + "_stb_o"
if (not (wire in self.wires)):
result +="\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#cycle
wire = wbm_name + "_cyc_o"
if (not (wire in self.wires)):
result +="\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#write enable
wire = wbm_name + "_we_o"
if (not (wire in self.wires)):
result +="\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#select
wire = wbm_name + "_sel_o"
if (not (wire in self.wires)):
result +="\twire\t[3:0]\t" + wire + ";\n"
self.wires.append(wire)
#in data
wire = wbm_name + "_dat_o"
if (not (wire in self.wires)):
result +="\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#out data
wire = wbm_name + "_dat_i"
if (not (wire in self.wires)):
result +="\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#address
wire = wbm_name + "_adr_o"
if (not (wire in self.wires)):
result +="\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#acknowledge
wire = wbm_name + "_ack_i"
if (not (wire in self.wires)):
result +="\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#interrupt
wire = wbm_name + "_int_i"
if (not (wire in self.wires)):
result +="\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#generate arbitrator signals
#strobe
wire = arb_name + "_wbs_stb_i"
if (not (wire in self.wires)):
result +="\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#cycle
wire = arb_name + "_wbs_cyc_i"
if (not (wire in self.wires)):
result +="\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#write enable
wire = arb_name + "_wbs_we_i"
if (not (wire in self.wires)):
result +="\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#select
wire = arb_name + "_wbs_sel_i"
if (not (wire in self.wires)):
result +="\twire\t[3:0]\t" + wire + ";\n"
self.wires.append(wire)
#in data
wire = arb_name + "_wbs_dat_i"
if (not (wire in self.wires)):
result +="\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#out data
wire = arb_name + "_wbs_dat_o"
if (not (wire in self.wires)):
result +="\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#address
wire = arb_name + "_wbs_adr_i"
if (not (wire in self.wires)):
result +="\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#acknowledge
wire = arb_name + "_wbs_ack_o"
if (not (wire in self.wires)):
result +="\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#interrupt
wire = arb_name + "_wbs_int_o"
if (not (wire in self.wires)):
result +="\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
result +="\n\n"
#finished generating the wires
result += "\t" + arb_module + " " + arb_name + "(\n"
result += "\t\t.clk(clk),\n"
if invert_reset:
result += "\t\t.rst(rst_n),\n"
else:
result += "\t\t.rst(rst),\n"
result += "\n"
result += "\t\t//masters\n"
for mi in range (0, master_count):
wbm_name = ""
#last master is always from the interconnect
#XXX: This should really be a parameter, but this will alow slaves to take over a peripheral
if (mi == master_count - 1):
if debug:
print "mi: " + str(mi)
on_periph_bus = False
#in this case I need to use the wishbone interconnect
#search for the index of the slave
for i in range (0, len(self.tags["SLAVES"].keys())):
name = self.tags["SLAVES"].keys()[i]
if name == arb_slave:
interconnect_index = i + 1 # +1 to account for DRT
on_periph_bus = True
wbm_name = "s" + str(interconnect_index)
if debug:
print "arb slave on peripheral bus"
print "slave index: " + str(interconnect_index - 1)
print "accounting for drt, actual bus index == " + str(interconnect_index)
break
#check mem bus
if (not on_periph_bus):
if ("MEMORY" in self.tags.keys()):
#There is a memory bus, look in here
for i in range (0, len(self.tags["MEMORY"].keys())):
name = self.tags["MEMORY"].keys()[i]
if name == arb_slave:
mem_inc_index = i
wbm_name = "sm" + str(i)
if debug:
print "arb slave on mem bus"
print "slave index: " + str(mem_inc_index)
break
result +="\t\t.m" + str(mi) + "_stb_i(" + wbm_name + "_wbs_stb_i),\n"
result +="\t\t.m" + str(mi) + "_cyc_i(" + wbm_name + "_wbs_cyc_i),\n"
result +="\t\t.m" + str(mi) + "_we_i(" + wbm_name + "_wbs_we_i),\n"
result +="\t\t.m" + str(mi) + "_sel_i(" + wbm_name + "_wbs_sel_i),\n"
result +="\t\t.m" + str(mi) + "_dat_i(" + wbm_name + "_wbs_dat_i),\n"
result +="\t\t.m" + str(mi) + "_adr_i(" + wbm_name + "_wbs_adr_i),\n"
result +="\t\t.m" + str(mi) + "_dat_o(" + wbm_name + "_wbs_dat_o),\n"
result +="\t\t.m" + str(mi) + "_ack_o(" + wbm_name + "_wbs_ack_o),\n"
result +="\t\t.m" + str(mi) + "_int_o(" + wbm_name + "_wbs_int_o),\n"
result +="\n\n"
#not the last index
else:
if debug:
print "mi: " + str(mi)
master_name = arb_tags[arb_slave].keys()[mi]
bus_name = arb_tags[arb_slave][master_name]
wbm_name = master_name + "_" + bus_name
result +="\t\t.m" + str(mi) + "_stb_i(" + wbm_name + "_stb_o),\n"
result +="\t\t.m" + str(mi) + "_cyc_i(" + wbm_name + "_cyc_o),\n"
result +="\t\t.m" + str(mi) + "_we_i(" + wbm_name + "_we_o),\n"
result +="\t\t.m" + str(mi) + "_sel_i(" + wbm_name + "_sel_o),\n"
result +="\t\t.m" + str(mi) + "_dat_i(" + wbm_name + "_dat_o),\n"
result +="\t\t.m" + str(mi) + "_adr_i(" + wbm_name + "_adr_o),\n"
result +="\t\t.m" + str(mi) + "_dat_o(" + wbm_name + "_dat_i),\n"
result +="\t\t.m" + str(mi) + "_ack_o(" + wbm_name + "_ack_i),\n"
result +="\t\t.m" + str(mi) + "_int_o(" + wbm_name + "_int_i),\n"
result +="\n\n"
result += "\t\t//slave\n"
result += "\t\t.s_stb_o(" + arb_name + "_wbs_stb_i),\n"
result += "\t\t.s_cyc_o(" + arb_name + "_wbs_cyc_i),\n"
result += "\t\t.s_we_o(" + arb_name + "_wbs_we_i),\n"
result += "\t\t.s_sel_o(" + arb_name + "_wbs_sel_i),\n"
result += "\t\t.s_dat_o(" + arb_name + "_wbs_dat_i),\n"
result += "\t\t.s_adr_o(" + arb_name + "_wbs_adr_i),\n"
result += "\t\t.s_dat_i(" + arb_name + "_wbs_dat_o),\n"
result += "\t\t.s_ack_i(" + arb_name + "_wbs_ack_o),\n"
result += "\t\t.s_int_i(" + arb_name + "_wbs_int_o)\n"
result += ");\n"
return result
def generate_project(self, config_file_name, debug=False):
"""Generate the folders and files for the project
Using the project tags and template tags this function generates all
the directories and files of the project. It will go through the template
structure and determine what files need to be added and call either
a generation script (in the case of \"top.v\") or simply copy the file
over (in the case of a peripheral or memory module.
Args:
config_file_name: name of the JSON configuration file
Return:
True: Success
False: Failure
Raises:
TypeError
IOError
SapError
"""
#reading the project config data into the the project tags
#XXX: This should be changed to an exception begin raised and not a True False statement
self.read_config_file(config_file_name)
board_dict = saputils.get_board_config(self.project_tags["board"])
cfiles = []
pt = self.project_tags
if "constraint_files" in pt.keys():
cfiles = pt["constraint_files"]
#if the user didn't specify any constraint files
#load the default
if len(cfiles) == 0:
cfiles = board_dict["default_constraint_files"]
#extrapolate the bus template
#XXX: Need to check all the constraint files
self.project_tags["CLOCK_RATE"] = saputils.read_clock_rate(cfiles[0])
self.read_template(self.project_tags["TEMPLATE"])
#set all the tags within the filegen structure
if debug:
print "set all tags wihin filegen structure"
self.filegen.set_tags(self.project_tags)
#generate the project directories and files
saputils.create_dir(self.project_tags["BASE_DIR"])
if debug:
print "generated the first dir"
#generate the arbitrator tags, this is important because the top
#needs the arbitrator tags
arb_tags = saparbitrator.generate_arbitrator_tags(
self.project_tags, False)
self.project_tags["ARBITRATORS"] = arb_tags
#print "Parent dir: " + self.project_tags["BASE_DIR"]
for key in self.template_tags["PROJECT_TEMPLATE"]["files"]:
self.recursive_structure_generator(
self.template_tags["PROJECT_TEMPLATE"]["files"], key,
self.project_tags["BASE_DIR"])
if debug:
print "generating project directories finished"
if debug:
print "generate the arbitrators"
self.generate_arbitrators()
#Generate all the slaves
for slave in self.project_tags["SLAVES"]:
fdict = {"location": ""}
file_dest = self.project_tags["BASE_DIR"] + "/rtl/bus/slave"
fn = self.project_tags["SLAVES"][slave]["filename"]
try:
self.filegen.process_file(filename=fn,
file_dict=fdict,
directory=file_dest,
debug=debug)
except ModuleFactoryError as err:
print "ModuleFactoryError while generating a slave: %s" % str(
err)
#each slave
if ("MEMORY" in self.project_tags):
for mem in self.project_tags["MEMORY"]:
fdict = {"location": ""}
file_dest = self.project_tags["BASE_DIR"] + "/rtl/bus/slave"
fn = self.project_tags["MEMORY"][mem]["filename"]
try:
self.filegen.process_file(filename=fn,
file_dict=fdict,
directory=file_dest)
except ModuleFactoryError as err:
print "ModuleFactoryError while generating a memory slave: %s" % str(
err)
#Copy the user specified constraint files to the constraints directory
for constraint_fname in cfiles:
sap_abs_base = os.getenv("SAPLIB_BASE")
abs_proj_base = saputils.resolve_linux_path(
self.project_tags["BASE_DIR"])
constraint_path = self.get_constraint_path(constraint_fname)
if (len(constraint_path) == 0):
print "Couldn't find constraint: " + constraint_fname + ", searched in current directory and " + sap_abs_base + " /hdl/" + self.project_tags[
"board"]
continue
shutil.copy(constraint_path,
abs_proj_base + "/constraints/" + constraint_fname)
#Generate the IO handler
interface_filename = self.project_tags["INTERFACE"]["filename"]
fdict = {"location": ""}
file_dest = self.project_tags["BASE_DIR"] + "/rtl/bus/interface"
result = self.filegen.process_file(filename=interface_filename,
file_dict=fdict,
directory=file_dest)
if debug:
print "copy over the dependencies..."
print "verilog files: "
for f in self.filegen.verilog_file_list:
print f
print "dependent files: "
for d in self.filegen.verilog_dependency_list:
fdict = {"location": ""}
file_dest = self.project_tags["BASE_DIR"] + "/dependencies"
result = self.filegen.process_file(filename=d,
file_dict=fdict,
directory=file_dest)
if debug:
print d
return True
def generate_project(self, config_file_name, debug=False):
"""Generate the folders and files for the project
Using the project tags and template tags this function generates all
the directories and files of the project. It will go through the template
structure and determine what files need to be added and call either
a generation script (in the case of \"top.v\") or simply copy the file
over (in the case of a peripheral or memory module.
Args:
config_file_name: name of the JSON configuration file
Return:
True: Success
False: Failure
Raises:
TypeError
IOError
SapError
"""
#reading the project config data into the the project tags
#XXX: This should be changed to an exception begin raised and not a True False statement
self.read_config_file(config_file_name)
board_dict = saputils.get_board_config(self.project_tags["board"])
cfiles = []
pt = self.project_tags
if "constraint_files" in pt.keys():
cfiles = pt["constraint_files"]
#if the user didn't specify any constraint files
#load the default
if len(cfiles) == 0:
cfiles = board_dict["default_constraint_files"]
#extrapolate the bus template
#XXX: Need to check all the constraint files
self.project_tags["CLOCK_RATE"] = saputils.read_clock_rate(cfiles[0])
self.read_template(self.project_tags["TEMPLATE"])
#set all the tags within the filegen structure
if debug:
print "set all tags wihin filegen structure"
self.filegen.set_tags(self.project_tags)
#generate the project directories and files
saputils.create_dir(self.project_tags["BASE_DIR"])
if debug:
print "generated the first dir"
#generate the arbitrator tags, this is important because the top
#needs the arbitrator tags
arb_tags = saparbitrator.generate_arbitrator_tags(self.project_tags, False)
self.project_tags["ARBITRATORS"] = arb_tags
#print "Parent dir: " + self.project_tags["BASE_DIR"]
for key in self.template_tags["PROJECT_TEMPLATE"]["files"]:
self.recursive_structure_generator(
self.template_tags["PROJECT_TEMPLATE"]["files"],
key,
self.project_tags["BASE_DIR"])
if debug:
print "generating project directories finished"
if debug:
print "generate the arbitrators"
self.generate_arbitrators()
#Generate all the slaves
for slave in self.project_tags["SLAVES"]:
fdict = {"location":""}
file_dest = self.project_tags["BASE_DIR"] + "/rtl/bus/slave"
fn = self.project_tags["SLAVES"][slave]["filename"]
try:
self.filegen.process_file(filename = fn, file_dict = fdict, directory=file_dest, debug=debug)
except ModuleFactoryError as err:
print "ModuleFactoryError while generating a slave: %s" % str(err)
#each slave
if ("MEMORY" in self.project_tags):
for mem in self.project_tags["MEMORY"]:
fdict = {"location":""}
file_dest = self.project_tags["BASE_DIR"] + "/rtl/bus/slave"
fn = self.project_tags["MEMORY"][mem]["filename"]
try:
self.filegen.process_file(filename = fn, file_dict = fdict, directory = file_dest)
except ModuleFactoryError as err:
print "ModuleFactoryError while generating a memory slave: %s" % str(err)
#Copy the user specified constraint files to the constraints directory
for constraint_fname in cfiles:
sap_abs_base = os.getenv("SAPLIB_BASE")
abs_proj_base = saputils.resolve_linux_path(self.project_tags["BASE_DIR"])
constraint_path = self.get_constraint_path(constraint_fname)
if (len(constraint_path) == 0):
print "Couldn't find constraint: " + constraint_fname + ", searched in current directory and " + sap_abs_base + " /hdl/" + self.project_tags["board"]
continue
shutil.copy (constraint_path, abs_proj_base + "/constraints/" + constraint_fname)
#Generate the IO handler
interface_filename = self.project_tags["INTERFACE"]["filename"]
fdict = {"location":""}
file_dest = self.project_tags["BASE_DIR"] + "/rtl/bus/interface"
result = self.filegen.process_file(filename = interface_filename, file_dict=fdict , directory=file_dest)
if debug:
print "copy over the dependencies..."
print "verilog files: "
for f in self.filegen.verilog_file_list:
print f
print "dependent files: "
for d in self.filegen.verilog_dependency_list:
fdict = {"location":""}
file_dest = self.project_tags["BASE_DIR"] + "/dependencies"
result = self.filegen.process_file(filename = d, file_dict = fdict, directory = file_dest)
if debug:
print d
return True
def generate_project(self, config_file_name, debug=False):
"""Recursively go through template structure and generate the folders and files"""
#reading the project config data into the the project tags
result = self.read_config_file(config_file_name)
if (not result):
if (debug):
print "failed to read in project config file"
return False
#extrapolate the bus template
self.project_tags["CLOCK_RATE"] = saputils.read_clock_rate(self.project_tags["CONSTRAINTS"]["constraint_files"][0])
result = self.read_template(self.project_tags["TEMPLATE"])
if (not result):
if (debug):
print "failed to read in template file"
return False
#set all the tags within the filegen structure
if debug:
print "set all tags wihin filegen structure"
self.filegen.set_tags(self.project_tags)
#generate the project directories and files
saputils.create_dir(self.project_tags["BASE_DIR"])
if debug:
print "generated the first dir"
#generate the arbitrator tags, this is important because the top
#needs the arbitrator tags
arb_tags = saparbitrator.generate_arbitrator_tags(self.project_tags, False)
self.project_tags["ARBITRATORS"] = arb_tags
#print "Parent dir: " + self.project_tags["BASE_DIR"]
for key in self.template_tags["PROJECT_TEMPLATE"]["files"]:
self.recursive_structure_generator(
self.template_tags["PROJECT_TEMPLATE"]["files"],
key,
self.project_tags["BASE_DIR"])
if debug:
print "generating project directories finished"
if debug:
print "generate the arbitrators"
self.generate_arbitrators()
#Generate all the slaves
for slave in self.project_tags["SLAVES"]:
fdict = {"location":""}
file_dest = self.project_tags["BASE_DIR"] + "/rtl/bus/slave"
fn = self.project_tags["SLAVES"][slave]["filename"]
result = self.filegen.process_file(filename = fn, file_dict = fdict, directory=file_dest)
if (not result):
print "Error: Failed to process the slave file: " + fn
#each slave
if ("MEMORY" in self.project_tags):
for mem in self.project_tags["MEMORY"]:
fdict = {"location":""}
file_dest = self.project_tags["BASE_DIR"] + "/rtl/bus/slave"
fn = self.project_tags["MEMORY"][mem]["filename"]
result = self.filegen.process_file(filename = fn, file_dict = fdict, directory = file_dest, debug = True)
if (not result):
print "Error: Failed to proecess memory file!: " + mem
#Copy the user specified constraint files to the constraints directory
for constraint_fname in self.project_tags["CONSTRAINTS"]["constraint_files"]:
sap_abs_base = os.getenv("SAPLIB_BASE")
abs_proj_base = saputils.resolve_linux_path(self.project_tags["BASE_DIR"])
constraint_path = self.get_constraint_path(constraint_fname)
if (len(constraint_path) == 0):
print "Couldn't find constraint: " + constraint_fname + ", searched in current directory and " + sap_abs_base + " /hdl/" + self.project_tags["CONSTRAINTS"]["board"]
continue
shutil.copy (constraint_path, abs_proj_base + "/constraints/" + constraint_fname)
#Generate the IO handler
interface_filename = self.project_tags["INTERFACE"]
fdict = {"location":""}
file_dest = self.project_tags["BASE_DIR"] + "/rtl/bus/interface"
result = self.filegen.process_file(filename = interface_filename, file_dict=fdict , directory=file_dest)
if debug:
print "copy over the dependencies..."
print "verilog files: "
for f in self.filegen.verilog_file_list:
print f
print "dependent files: "
for d in self.filegen.verilog_dependency_list:
fdict = {"location":""}
file_dest = self.project_tags["BASE_DIR"] + "/dependencies"
result = self.filegen.process_file(filename = d, file_dict = fdict, directory = file_dest)
print d
return True
