def new_74374():
"8-bit DFF"
chip = skidl.Part('74xx', '74LS374', footprint="Package_DIP:DIP-20_W7.62mm")
chip.VCC += VCC
chip.GND += GND
chip.OE += GND # enable
return chip
def new_74151():
"single 8-1 MUX"
chip = skidl.Part('74xx', '74LS151', footprint="Package_DIP:DIP-16_W7.62mm")
chip.VCC += VCC
chip.GND += GND
chip['~E'] += GND # enable
return chip
def new_74257():
"quad 2-1 MUX"
chip = skidl.Part('74xx', '74LS257', footprint="Package_DIP:DIP-16_W7.62mm")
chip.VCC += VCC
chip.GND += GND
chip.OE += GND # enable
return chip
def get_keyswitch(self, value, is_mx, is_hotswap):
if is_mx:
switch_type = "MX"
else:
switch_type = "PG1350"
if is_hotswap:
socket_type = "Kailh_socket"
else:
socket_type = "SW"
footprint = "keycad:%s_%s" % (socket_type, switch_type)
if is_mx:
self.record_part(_Part.MxSw)
if is_hotswap:
self.record_part(_Part.MxKailh)
else:
self.record_part(_Part.Pg1350Sw)
if is_hotswap:
self.record_part(_Part.Pg1350Kailh)
part = skidl.Part('keycad',
'KEYSW',
skidl.NETLIST,
footprint=footprint)
part.ref = self.assign_ref(_RefType.Keyswitch)
part.value = value
return part
def new_74158():
"quad 2-1 MUX, inverted"
chip = skidl.Part('74xx', '74LS158', footprint="Package_DIP:DIP-16_W7.62mm")
chip.VCC += VCC
chip.GND += GND
chip.OE += GND # enable
return chip
def new_74161():
"4-bit counter"
chip = skidl.Part('74xx', '74LS161', footprint="Package_DIP:DIP-16_W7.62mm")
chip.VCC += VCC
chip.GND += GND
chip['~MR'] += VCC
chip.CEP += VCC
return chip
def new_74244():
"8-bit buffer"
chip = skidl.Part('74xx', '74LS244', footprint="Package_DIP:DIP-20_W7.62mm")
chip.VCC += VCC
chip.GND += GND
chip.OE0 += GND # enable
chip.OE1 += GND # enable
return chip
def new_74153():
"dual 4-1 MUX"
chip = skidl.Part('74xx', '74LS153', footprint="Package_DIP:DIP-16_W7.62mm")
chip.VCC += VCC
chip.GND += GND
chip['0E'] += GND # enable
chip['1E'] += GND # enable
return chip
def get_diode(self):
self.record_part(_Part.D1N4148)
part = skidl.Part('keycad',
'D',
skidl.NETLIST,
footprint='keycad:D_0805')
part.ref = self.assign_ref(_RefType.Diode)
part.value = "1N4148"
return part
def get_reset_switch(self):
self.record_part(_Part.SWSKQG)
part = skidl.Part('keycad',
'SW_Push',
skidl.NETLIST,
footprint='keycad:SW_SPST_SKQG_WithoutStem')
part.ref = self.assign_ref(_RefType.Switch)
part.value = 'SKQGAKE010'
return part
def get_per_key_rgb_led(self):
self.record_part(_Part.Sk6812MiniE)
part = skidl.Part('keycad',
'SK6812MINI-E',
skidl.NETLIST,
footprint='keycad:SK6812-MINI-E-BOTTOM')
part.ref = self.assign_ref(_RefType.LED)
part.value = "SK6812MINI-E"
return part
def get_usb_c_connector(self):
self.record_part(_Part.USB_HRO_C31M14)
part = skidl.Part(
'keycad',
'USB_C_Receptacle_USB2.0',
skidl.NETLIST,
footprint='keycad:USB_C_Receptacle_HRO_TYPE-C-31-M-14')
part.ref = self.assign_ref(_RefType.Connector)
part.value = 'TYPE-C-31-M-14'
return part
def get_resistor(self, value):
part = skidl.Part('keycad',
'R',
skidl.NETLIST,
footprint='keycad:R_0805_2012Metric')
if value == "5K1":
self.record_part(_Part.R5K1)
part.value = value
else:
raise ValueError("Unknown resistor value")
part.ref = self.assign_ref(_RefType.Resistor)
return part
def get_capacitor(self, value):
part = skidl.Part('keycad',
'C',
skidl.NETLIST,
footprint='keycad:C_0805_2012Metric')
if value == "0.1uF":
self.record_part(_Part.C0UF1)
part.value = value
else:
raise ValueError("Unknown capacitor value")
part.ref = self.assign_ref(_RefType.Capacitor)
return part
def circuit(self, port):
circuit_nets = {}
gnd = skidl.Net('GND')
decoupling_caps = []
fpga = skidl.Part(lib=altera_sklib.altera,
name='10M02SCE',
footprint='EQFP144')
#Power related pins
for pin in fpga.pins:
if "GND" in pin.name:
pin += gnd
elif "VCC" in pin.name:
if pin.name not in circuit_nets.keys():
circuit_nets[pin.name] = skidl.Net(pin.name)
decoupling_caps.append(
skidl.Part('device',
'C',
value='100n',
footprint='Capacitors_SMD:C_0805'))
pin += circuit_nets[pin.name]
decoupling_caps[-1][1] += circuit_nets[pin.name]
decoupling_caps[-1][2] += gnd
def get_mcu(self, mcu_type):
if not isinstance(mcu_type, McuType):
raise ValueError("%s is not a Mcu enum" % (mcu_type))
if mcu_type == McuType.ProMicro:
self.record_part(_Part.ProMicro)
part = skidl.Part('keycad',
'ProMicro',
skidl.NETLIST,
footprint='keycad:ArduinoProMicro')
part.ref = self.assign_ref(_RefType.IC)
part.value = 'Pro Micro'
return part
if mcu_type == McuType.BluePill:
self.record_part(_Part.BluePill)
part = skidl.Part('keycad',
'BluePill_STM32F103C',
skidl.NETLIST,
footprint='keycad:BluePill_STM32F103C')
part.ref = self.assign_ref(_RefType.IC)
part.value = 'Blue Pill'
return part
raise ValueError("MCU type %s not implemented" % mcu_type)
def part(self,
device,
value,
footprint,
cls=component.Component,
ref=None):
if device:
part = skidl.Part(device,
value,
footprint=footprint,
circuit=self.circuit)
else:
part = None
module = self.pcb.parseFootprintModule(footprint)
if not part and not ref:
ref = 'X%d' % self._next_ref
self._next_ref += 1
component = cls(part, footprint, module, self, ref=ref)
component.reserve_nets()
self._parts.append(component)
return component
def new_cap():
"a decoupling capacitor"
chip = skidl.Part('Device', 'C', footprint="Capacitor_THT:C_Disc_D4.7mm_W2.5mm_P5.00mm")
chip[1] += VCC
chip[2] += GND
def new_7410():
"triple NAND3"
chip = skidl.Part('74xx', '74LS10', footprint="Package_DIP:DIP-14_W7.62mm")
chip.VCC += VCC
chip.GND += GND
return chip
def new_74377():
"8-bit DFFE"
chip = skidl.Part('74xx', '74LS377', footprint="Package_DIP:DIP-20_W7.62mm")
chip.VCC += VCC
chip.GND += GND
return chip
def new_74273():
"8-bit DFF with clear"
chip = skidl.Part('74xx', '74LS273', footprint="Package_DIP:DIP-20_W7.62mm")
chip.VCC += VCC
chip.GND += GND
return chip
def new_74688():
"8-bit magnitude comparator"
chip = skidl.Part('74xx', '74LS688', footprint="Package_DIP:DIP-20_W7.62mm")
chip.VCC += VCC
chip.GND += GND
return chip
def new_7402():
"quad NOR"
chip = skidl.Part('74xx', '74LS02', footprint="Package_DIP:DIP-14_W7.62mm")
chip.VCC += VCC
chip.GND += GND
return chip
def new_7474():
"dual DFFSR"
chip = skidl.Part('74xx', '74LS74', footprint="Package_DIP:DIP-14_W7.62mm")
chip.VCC += VCC
chip.GND += GND
return chip
def new_7420():
"dual NAND4"
chip = skidl.Part('74xx', '74LS20', footprint="Package_DIP:DIP-14_W7.62mm")
chip.VCC += VCC
chip.GND += GND
return chip
def new_7404():
"hex NOT"
chip = skidl.Part('74xx', '74LS04', footprint="Package_DIP:DIP-14_W7.62mm")
chip.VCC += VCC
chip.GND += GND
return chip
def new_74283():
"4-bit adder"
chip = skidl.Part('74xx', '74LS283', footprint="Package_DIP:DIP-16_W7.62mm")
chip.VCC += VCC
chip.GND += GND
return chip
import skidl
skidl.lib_search_paths[skidl.KICAD].append('gsg-kicad-lib')
gnd = skidl.Net('GND')
vcc = skidl.Net('VCC')
num_leds = 242
leds = []
sdi = []
cki = []
for i in range(num_leds):
leds.append(
skidl.Part('gsg-symbols.lib',
'APA102',
footprint='gsg-modules:APA102-2020'))
sdi.append(skidl.Net('SDI' + str(i)))
cki.append(skidl.Net('SDO' + str(i)))
leds[i]['SDI'] += sdi[i]
leds[i]['CKI'] += cki[i]
leds[i]['GND'] += gnd
leds[i]['VCC'] += vcc
# connect input to previous output
if 0 < i:
leds[i - 1]['SDO'] += sdi[i]
leds[i - 1]['CKO'] += cki[i]
# don't connect the output of the last LED
leds[-1]['SDO'] += NC
leds[-1]['CKO'] += NC
def new_7485():
"4-bit magnitude comparator"
chip = skidl.Part('74xx', '74LS85', footprint="Package_DIP:DIP-16_W7.62mm")
chip.VCC += VCC
chip.GND += GND
return chip
