def _makeSimModel(self): self.tb = Testbench.default('top_sim') self.dut = Module.default("DUT") self.tb.add_module(self.dut) self.dut.add_clock_port("clk", "6.25ns") self.dut.add_clock_port("mem_sys_clk_p", "3ns") self.dut.add_reset_port("sys_resetn") self.axis_in = AXIS("stream_in", "slave", "clk") self.axis_in.port.init_channels('default', 64) self.axis_out = AXIS("stream_out", "master", "clk") self.axis_out.port.init_channels('default', 64) self.dut.add_interface(self.axis_in) self.dut.add_interface(self.axis_out) self.dut.add_port("mem_ready", size=1, direction="output") self.reset_thread = Thread() self.reset_thread.wait_negedge('clk') self.reset_thread.init_signals() self.reset_thread.add_delay('25ns') #T*4 #reset the system self.reset_thread.set_signal('sys_resetn', 1) #wait for memory calibration self.reset_thread.wait_level('mem_ready == $value', value=1) self.tv = TestVector() self.tv.add_thread(self.reset_thread)
def test_testbench_ethernet(test_dir, monkeypatch): """ Define the testbench for the ethernet project from the examples. Note, these arguments are only used by pytest. Args: test_dir (TestPaths): Used to hold test directories monkeypatch (MonkeyPatch): Defined in pytest for monkeypatching code """ # pylint: disable=too-many-statements,too-many-locals # create top-level entity for the testbench using the default constructor # and set the Module_Name metadata tag to 'ethernet' as specified by the # default constructor. ethernet_tb = Testbench.default("ethernet") ethernet_tb.set_metadata("Timeout_Value", "1us") # the DUT ----------------------------------------------------------------- # create a DUT module named 'DUT' and specify its signal ports dut = Module.default("DUT") data_width = 64 dut.add_parameter("DATA_WIDTH", data_width) dut.add_clock_port("clk", "20ns") dut.add_reset_port("rst") dut.add_port("m_eth_hdr_valid", "output") dut.add_port("m_eth_hdr_ready", "input") dut.add_port("m_eth_dest_mac", "output", size=48) dut.add_port("m_eth_src_mac", "output", size=48) dut.add_port("m_eth_type", "output", size=16) dut.add_port("busy", "output") dut.add_port("error_header_early_termination", "output") ethernet_tb.add_dut(dut) # create an AXI4Stream-M interface with the default side channels + tkeep axis_out = AXI4Stream("m_eth_payload_axis", "master", "clk", "rst") axis_out.init_signals("tkeep", 64, False) axis_out.add_endpoint("manual") dut.add_interface(axis_out) # create an AXI4Stream-S interface with the default side channels + tkeep axis_in = AXI4Stream("s_axis", "slave", "clk", "rst") axis_in.init_signals("tkeep", 64, False) axis_in.add_endpoint("manual") dut.add_interface(axis_in) # test vectors ------------------------------------------------------------ test_vector_0 = TestVector() # this thread just initializes signals. It could be reused in many test # vectors so it's created differently from the other threads. init_thread = Thread() init_thread.wait_negedge("clk") # wait for negedge of clk init_thread.init_signals() # initialize all signals to zero init_thread.set_signal("rst", 1) init_thread.add_delay("40ns") init_thread.set_signal("rst", 0) init_thread.set_signal("m_eth_hdr_ready", 1) init_thread.set_signal("m_eth_payload_axis_tready", 1) ethernet_tb.set_prologue_thread(init_thread) # this thread is responsible for sending the stimulus (i.e. the driver) input_thr = test_vector_0.add_thread() input_thr.init_timer() # zeros a timer that can be evaluated for runtime mac_src = "01:02:03:04:05:06" mac_dst = "07:08:09:0a:0b:0c" ether_type = "ba:ba" padstr = bytes(range(64)) my_eth = Ethernet(mac_src, mac_dst, ether_type) my_eth.add_payload(padstr) my_eth.stream(input_thr, axis_in) # this thread will validate the behavior of the DUT (i.e. the monitor) header_thr = test_vector_0.add_thread() header_thr.wait_level("m_eth_hdr_valid == 1") header_thr.assert_value("m_eth_src_mac == 48'h010203040506") header_thr.assert_value("m_eth_dest_mac == 48'h0708090a0b0c") header_thr.assert_value("m_eth_type == 16'hbaba") payload_thr = test_vector_0.add_thread() my_eth.stream(payload_thr, axis_out, "payload") payload_thr.print_elapsed_time("End") payload_thr.end_vector() # terminates the test vector # epilogue ----------------------------------------------------------------- # if there are many vectors, they can be selectively enabled by adding them ethernet_tb.add_test_vector(test_vector_0) # generate the output testbenches and data files for the specified languages # at the designated path if monkeypatch: monkeypatch.setenv("SONAR_CAD_VERSION", str(2018.1)) if test_dir: ethernet_tb.generate_tb( str(test_dir.testbench.ethernet.joinpath("ethernet.py")), "sv", True, ) print(ethernet_tb) # used to test printing out the configuration else: ethernet_tb.generate_tb(__file__, "sv", True)
import os from sonar.testbench import Testbench, Module, TestVector, Thread from sonar.interfaces import AXIS, SAXILite # create top-level entity for the testbench using the default constructor # and set the Module_Name metadata tag to 'sample' as specified by the # default constructor. sample_TB = Testbench.default("dbg_guv_width_adapter") filepath = os.path.join(os.path.dirname(__file__), "./") # the DUT ------------------------------------------------------------------ # create a DUT module named 'DUT' and specify its signal ports dut = Module.default("DUT") dut.add_clock_port("clk", "10ns") dut.add_reset_port("rst") dut.add_port("header", size=32, direction="input") sample_TB.add_module(dut) # create an AXI-M interface with the default side channels and a data width # of 64 and add it to the DUT. adapted = AXIS("adapted", "master", "clk") adapted.port.init_channels("default", 32) dut.add_interface(adapted) # create an AXI-S interface with the default side channels and a data width # of 64 and add it to the DUT. payload = AXIS("payload", "slave", "clk") payload.port.init_channels("empty")
def test_testbench_hello_world(test_dir, monkeypatch): """ Define the testbench for the hello_world project from the examples. Note, these arguments are only used by pytest. Args: test_dir (TestPaths): Used to hold test directories monkeypatch (MonkeyPatch): Defined in pytest for monkeypatching code """ # pylint: disable=too-many-statements # create top-level entity for the testbench using the default constructor # and set the Module_Name metadata tag to 'hello_world' as specified by the # default constructor. hello_world_tb = Testbench.default("hello_world") hello_world_tb.set_metadata("Timeout_Value", "5us") hello_world_tb.set_metadata("Headers", ["hello_world.hpp"]) # the DUT ----------------------------------------------------------------- # create a DUT module named 'DUT' and specify its signal ports dut = Module.cpp_vivado("DUT", "20.5ns") dut.add_port("state_out", size=3, direction="output") dut.add_port("ack", "output") clock = dut.ports.get_clocks("input")[0] # we know only one clock exists reset = dut.ports.get_resets("input")[0] # we know only one reset exists hello_world_tb.add_dut(dut) # create an AXI-M interface with the default side channels and a data width # of 64 and add it to the DUT. axis_out = AXI4Stream("axis_output", "master", clock, reset) axis_out.init_signals("default", 64) axis_out.iClass = "axis_t" # this field is needed for C++ TBs axis_out.flit = "axis_word_t" # this field is needed for C++ TBs axis_out.add_endpoint("manual") axis_out.add_endpoint("variable", cycle=2, limit=10) dut.add_interface(axis_out) # create an AXI-S interface with the default side channels and a data width # of 64 and add it to the DUT. axis_in = AXI4Stream("axis_input", "slave", clock, reset) axis_in.init_signals("default", 64) axis_in.iClass = "axis_t" axis_in.flit = "axis_word_t" axis_in.add_endpoint("manual") dut.add_interface(axis_in) # create a S-AXILite interface, set up its register space and add it to the # DUT. ctrl_bus = AXI4LiteSlave("s_axi_ctrl_bus", clock, reset) ctrl_bus.add_register("enable", 0x10) # register 'enable' is at addr 0x10 ctrl_bus.set_address("4K", 0) # address range is 4K at an offset of 0 ctrl_bus.init_signals(mode="default", data_width=32, addr_width=5) ctrl_bus.add_endpoint("manual") dut.add_interface(ctrl_bus) # test vectors ------------------------------------------------------------ test_vector_0 = TestVector() # this thread just initializes signals. It is reused in all test # vectors to initialize the test. The other threads wait until this thread # finishes before starting. init_thread = Thread() init_thread.wait_negedge(clock.name) # wait for negedge of the clock init_thread.init_signals() # initialize all signals to zero init_thread.add_delay("40ns") init_thread.set_signal(reset.name, 1) init_thread.set_signal("axis_output_tready", 1) hello_world_tb.set_prologue_thread(init_thread) # this thread is responsible for sending the stimulus (i.e. the driver) input_thr = test_vector_0.add_thread() input_thr.init_timer() # zeros a timer that can be evaluated for runtime ctrl_bus.write(input_thr, "enable", 1) axis_in.write(input_thr, 0xABCD) input_thr.call_dut(2) input_thr.wait_level("ack == $0", 1) axis_in.write(input_thr, 0) input_thr.call_dut(3) input_thr.wait_level("ack == $0", 1) input_thr.add_delay("110ns") input_thr.set_flag(0) # sets flag 0 that another thread may be waiting on # this thread will validate the behavior of the DUT (i.e. the monitor) output_thr = test_vector_0.add_thread() axis_out.read(output_thr, 1) # AXIS implicitly waits for valid data output_thr.wait_flag(0) # waits for flag 0 to be set by another thread ctrl_bus.read(output_thr, "enable", 1) output_thr.print_elapsed_time( "End") # prints string + time since last init output_thr.display("The_simulation_is_finished") # prints string output_thr.end_vector() # terminates the test vector # epilogue ----------------------------------------------------------------- # if there are many vectors, they can be selectively enabled by adding them hello_world_tb.add_test_vector(test_vector_0) # generate the output testbenches and data files for the specified languages # at the designated path if monkeypatch: monkeypatch.setenv("SONAR_CAD_VERSION", str(2018.1)) if test_dir: hello_world_tb.generate_tb( str(test_dir.testbench.hello_world.joinpath("hello_world.py")), "all", ) print(hello_world_tb) # used to test printing out the configuration else: hello_world_tb.generate_tb(__file__, "all", True)