def write_stimulus(self, mode, target_time, correct_value): """Creates a stimulus file for SRAM setup/hold time calculation""" # creates and opens the stimulus file for writing temp_stim = OPTS.openram_temp + "stim.sp" self.sf = open(temp_stim, "w") self.write_header(correct_value) # instantiate the master-slave d-flip-flop self.sf.write("\n* Instantiation of the Master-Slave D-flip-flop\n") stimuli.inst_model(stim_file=self.sf, pins=self.pins, model_name=self.model_name) self.write_data(mode=mode, target_time=target_time, correct_value=correct_value) self.write_clock() self.write_measures(mode=mode, correct_value=correct_value) stimuli.write_control(self.sf,4*self.period) self.sf.close()
def write_stimulus(self, period, load, slew): """Creates a stimulus file for simulations to probe a certain bitcell, given an address and data-position of the data-word (probe-address form: '111010000' LSB=0, MSB=1) (probe_data form: number corresponding to the bit position of data-bus, begins with position 0) """ self.check_arguments() # obtains list of time-points for each rising clk edge self.obtain_cycle_times(period) # creates and opens stimulus file for writing temp_stim = "{0}/stim.sp".format(OPTS.openram_temp) self.sf = open(temp_stim, "w") self.sf.write( "* Stimulus for period of {0}n load={1} slew={2}\n\n".format( period, load, slew)) # include files in stimulus file model_list = tech.spice["fet_models"] + [self.sram_sp_file] stimuli.write_include(stim_file=self.sf, models=model_list) # add vdd/gnd statements self.sf.write("* Global Power Supplies\n") stimuli.write_supply(self.sf) # instantiate the sram self.sf.write("* Instantiation of the SRAM\n") stimuli.inst_sram(stim_file=self.sf, abits=self.addr_size, dbits=self.word_size, sram_name=self.name) self.sf.write("* SRAM output loads\n") for i in range(self.word_size): self.sf.write("CD{0} D[{0}] 0 {1}f\n".format(i, load)) # add access transistors for data-bus self.sf.write( "* Transmission Gates for data-bus and control signals\n") stimuli.inst_accesstx(stim_file=self.sf, dbits=self.word_size) # generate data and addr signals self.sf.write("* Generation of data and address signals\n") for i in range(self.word_size): if i == self.probe_data: stimuli.gen_data(stim_file=self.sf, clk_times=self.cycle_times, sig_name="DATA[{0}]".format(i), period=period, slew=slew) else: stimuli.gen_constant(stim_file=self.sf, sig_name="D[{0}]".format(i), v_val=self.gnd) stimuli.gen_addr(self.sf, clk_times=self.cycle_times, addr=self.probe_address, period=period, slew=slew) # generate control signals self.sf.write("* Generation of control signals\n") stimuli.gen_csb(self.sf, self.cycle_times, period, slew) stimuli.gen_web(self.sf, self.cycle_times, period, slew) stimuli.gen_oeb(self.sf, self.cycle_times, period, slew) self.sf.write("* Generation of global clock signal\n") stimuli.gen_pulse(stim_file=self.sf, sig_name="CLK", v1=self.gnd, v2=self.vdd, offset=period, period=period, t_rise=slew, t_fall=slew) self.write_measures(period) # run until the last cycle time stimuli.write_control(self.sf, self.cycle_times[-1]) self.sf.close()
def write_stimulus(self, period, load, slew): """ Creates a stimulus file for simulations to probe a bitcell at a given clock period. Address and bit were previously set with set_probe(). Input slew (in ns) and output capacitive load (in fF) are required for charaterization. """ self.check_arguments() # obtains list of time-points for each rising clk edge self.obtain_cycle_times(period) # creates and opens stimulus file for writing temp_stim = "{0}/stim.sp".format(OPTS.openram_temp) self.sf = open(temp_stim, "w") self.sf.write("* Stimulus for period of {0}n load={1}fF slew={2}ns\n\n".format(period,load,slew)) # include files in stimulus file model_list = tech.spice["fet_models"] + [self.sram_sp_file] stimuli.write_include(stim_file=self.sf, models=model_list) # add vdd/gnd statements self.sf.write("\n* Global Power Supplies\n") stimuli.write_supply(self.sf) # instantiate the sram self.sf.write("\n* Instantiation of the SRAM\n") stimuli.inst_sram(stim_file=self.sf, abits=self.addr_size, dbits=self.word_size, sram_name=self.name) self.sf.write("\n* SRAM output loads\n") for i in range(self.word_size): self.sf.write("CD{0} d[{0}] 0 {1}f\n".format(i,load)) # add access transistors for data-bus self.sf.write("\n* Transmission Gates for data-bus and control signals\n") stimuli.inst_accesstx(stim_file=self.sf, dbits=self.word_size) # generate data and addr signals self.sf.write("\n* Generation of data and address signals\n") for i in range(self.word_size): if i == self.probe_data: self.gen_data(clk_times=self.cycle_times, sig_name="data[{0}]".format(i), period=period, slew=slew) else: stimuli.gen_constant(stim_file=self.sf, sig_name="d[{0}]".format(i), v_val=self.gnd) self.gen_addr(clk_times=self.cycle_times, addr=self.probe_address, period=period, slew=slew) # generate control signals self.sf.write("\n* Generation of control signals\n") self.gen_csb(self.cycle_times, period, slew) self.gen_web(self.cycle_times, period, slew) self.gen_oeb(self.cycle_times, period, slew) self.sf.write("\n* Generation of global clock signal\n") stimuli.gen_pulse(stim_file=self.sf, sig_name="CLK", v1=self.gnd, v2=self.vdd, offset=period, period=period, t_rise=slew, t_fall=slew) self.write_measures(period) # run until the end of the cycle time stimuli.write_control(self.sf,self.cycle_times[-1] + period) self.sf.close()