def __init__(self, expand=False, offset=0x0, **kwargs):
super().__init__(
expand=expand,
offset=0x0, # This module assume offset 0x0
**kwargs)
self.add(axi.AxiVersion(
offset=AXIL_OFFSETS[7],
expand=False,
))
self.add(xilinx.Xadc(
offset=AXIL_OFFSETS[8],
expand=False,
))
self.add(
micron.AxiMicronN25Q(
offset=AXIL_OFFSETS[9],
addrMode=False, # Assume 24-bit address support only
hidden=True,
))
self.add(
pr.RemoteVariable(
name='LSST_PWR_CORE_VERSION_C',
description='See LsstPwrCtrlPkg.vhd for definitions',
offset=AXIL_OFFSETS[7] + 0x400, # 0x1C0400
base=pr.UInt,
mode='RO',
))
self.add(
pr.RemoteVariable(
name='BOARD_ID',
description='eFuse[7:0] value',
offset=AXIL_OFFSETS[7] + 0x404, # 0x1C0404
base=pr.UInt,
bitSize=8,
mode='RO',
))
self.add(
pr.RemoteVariable(
name='NUM_LANE_G',
description='Number of Ethernet lanes',
offset=AXIL_OFFSETS[7] + 0x408, # 0x1C0408
base=pr.UInt,
mode='RO',
))
def __init__(self, **kwargs):
if 'description' not in kwargs:
kwargs['description'] = "HR Gen1 FPGA"
super(self.__class__, self).__init__(**kwargs)
######################################
# SACI base address and address stride
######################################
saciAddr = 0x01000000
saciChip = 0x400000
#############
# Add devices
#############
self.add(axi.AxiVersion(offset=0x00000000, expand=False))
self.add(xilinx.Xadc(offset=0x00010000, expand=False))
self.add(
AtlasChess2Feb.sysReg(name="sysReg",
offset=0x00030000,
expand=False))
self.add(
AtlasChess2Feb.memReg(name="memReg",
offset=0x00040000,
expand=True))
#self.add(AtlasChess2Feb.iobuff( name="iobuff", offset=0x00500000,expand=False))
self.add(
AtlasChess2Feb.dac(name="dac", offset=0x00100000, expand=False))
self.add(
AtlasChess2Feb.chargeInj(name="chargeInj",
offset=0x00330000,
expand=False))
for i in range(3):
self.add(
AtlasChess2Feb.Chess2Array(name='Chess2Ctrl%01i' % (i),
offset=(saciAddr + i * saciChip),
enabled=False,
expand=False))
self.add(
AtlasChess2Feb.Chess2Test(name="Chess2Test",
offset=saciAddr + (3 * saciChip),
enabled=False,
expand=False))
def __init__(self,
name='Fpga',
fpgaType='',
commType='',
description='Fpga Container',
**kwargs):
super().__init__(name=name, description=description, **kwargs)
#############
# Add devices
#############
self.add(axi.AxiVersion(
offset=0x00000000,
expand=False,
))
if (fpgaType == '7series'):
self.add(xil.Xadc(
offset=0x00010000,
expand=False,
))
if (fpgaType == 'ultrascale'):
self.add(xil.AxiSysMonUltraScale(
offset=0x00020000,
expand=False,
))
self.add(
MbSharedMem(
name='MbSharedMem',
offset=0x00030000,
size=0x10000,
expand=False,
))
self.add(ssi.SsiPrbsTx(
offset=0x00040000,
expand=False,
))
self.add(ssi.SsiPrbsRx(
offset=0x00050000,
expand=False,
))
if (commType == 'eth'):
self.add(rssi.RssiCore(
offset=0x00070000,
expand=False,
))
self.add(
axi.AxiStreamMonitoring(
name='AxisMon',
offset=0x00080000,
numberLanes=2,
expand=False,
))
self.add(
MbSharedMem(
name='TestEmptyMem',
offset=0x80000000,
size=0x80000000,
expand=False,
))
def __init__(self,
name="Top",
description="Container for FEB FPGA",
dev='/dev/datadev_0',
hwType='pcie',
ip='10.0.0.1',
**kwargs):
super().__init__(name=name, description=description, **kwargs)
# File writer
dataWriter = pr.utilities.fileio.StreamWriter()
self.add(dataWriter)
######################################################################
if (hwType == 'hsio-dtm') or (hwType == 'rce-dpm'):
# Create the mmap interface
rceMap = rogue.hardware.axi.AxiMemMap('/dev/rce_memmap')
# Add RCE version device
self.add(rceg3.RceVersion(
memBase=rceMap,
expand=False,
))
# Add PGPv3 to the FEB
self.add(
pgp.Pgp3AxiL(
name='Pgp3Mon',
memBase=rceMap,
offset=0xA0000000,
numVc=1,
writeEn=True,
expand=False,
))
if (hwType == 'hsio-dtm'):
# Add PGPv2b to the HSIO FPGA
self.add(
pgp.Pgp2bAxi(
name='Pgp2bMon',
memBase=rceMap,
offset=0xA1000000,
expand=False,
))
# Connect the SRPv0 to PGPv2b.VC[1]
pgp2bVc1 = rogue.hardware.axi.AxiStreamDma(
'/dev/axi_stream_dma_0', 1, True)
srpV0 = rogue.protocols.srp.SrpV0()
pr.streamConnectBiDir(srpV0, pgp2bVc1)
if (hwType == 'pcie'):
axiMemMap = rogue.hardware.axi.AxiMemMap(dev)
self.add(
pcie.AxiPcieCore(
memBase=axiMemMap,
offset=0x00000000,
expand=False,
))
# for i in range(8):
# self.add(pgp.Pgp3AxiL(
# memBase = axiMemMap,
# name = ('Pgp3Mon[%d]' % i),
# offset = (0x00800000 + i*0x10000),
# numVc = 16,
# writeEn = True,
# expand = False,
# ))
######################################################################
# Create an empty stream arrays
configStream = [None] * 4
dataStream = [None] * 4
########################################################################################################################
# https://github.com/slaclab/rogue/blob/master/include/rogue/hardware/axi/AxiStreamDma.h
# static boost::shared_ptr<rogue::hardware::axi::AxiStreamDma> create (std::string path, uint32_t dest, bool ssiEnable);
########################################################################################################################
######################################################################
# PGPv3.[VC=0] = FEB SRPv3 Register Access
# PGPv3.[VC=1] = RD53[DPORT=0] Streaming ASIC Configuration Interface
# PGPv3.[VC=2] = RD53[DPORT=1] Streaming ASIC Configuration Interface
# PGPv3.[VC=3] = RD53[DPORT=2] Streaming ASIC Configuration Interface
# PGPv3.[VC=4] = RD53[DPORT=3] Streaming ASIC Configuration Interface
# PGPv3.[VC=5] = RD53[DPORT=0] Streaming Data Interface
# PGPv3.[VC=6] = RD53[DPORT=1] Streaming Data Interface
# PGPv3.[VC=7] = RD53[DPORT=2] Streaming Data Interface
# PGPv3.[VC=8] = RD53[DPORT=3] Streaming Data Interface
######################################################################
if (hwType == 'simulation'):
srpStream = pr.interfaces.simulation.StreamSim(host='localhost',
dest=0,
uid=12,
ssi=True)
for i in range(4):
configStream[i] = pr.interfaces.simulation.StreamSim(
host='localhost', dest=1 + i, uid=12, ssi=True)
dataStream[i] = pr.interfaces.simulation.StreamSim(
host='localhost', dest=5 + i, uid=12, ssi=True)
elif (hwType == 'eth'):
rudp = pr.protocols.UdpRssiPack(host=ip, port=8192, packVer=2)
srpStream = rudp.application(0)
for i in range(4):
configStream[i] = rudp.application(1 + i)
dataStream[i] = rudp.application(5 + i)
else:
srpStream = rogue.hardware.axi.AxiStreamDma(dev, 0, True)
for i in range(4):
configStream[i] = rogue.hardware.axi.AxiStreamDma(
dev, 1 + i, True)
dataStream[i] = rogue.hardware.axi.AxiStreamDma(
dev, 5 + i, True)
######################################################################
# Connect the SRPv3 to PGPv3.VC[0]
memMap = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir(memMap, srpStream)
for i in range(4):
# Add data stream to file as channel [i] to dataStream[i]
pr.streamConnect(dataStream[i], dataWriter.getChannel(i))
######################################################################
# Add devices
self.add(
axiVer.AxiVersion(
name='AxiVersion',
memBase=memMap,
offset=0x00000000,
expand=False,
))
self.add(
xil.Xadc(
name='Xadc',
memBase=memMap,
offset=0x00010000,
expand=False,
))
self.add(
prom.AxiMicronP30(
name='AxiMicronP30',
memBase=memMap,
offset=0x00020000,
hidden=True, # Hidden in GUI because indented for scripting
))
self.add(
common.SysReg(
name='SysReg',
description=
'This device contains system level configuration and status registers',
memBase=memMap,
offset=0x00030000,
expand=False,
))
self.add(
common.Ntc(
name='Rd53Ntc',
description=
'This device contains the four NTC MAX6682 readout modules',
memBase=memMap,
offset=0x00040000,
expand=False,
))
self.add(
nxp.Sa56004x(
name='BoardTemp',
description=
'This device monitors the board temperature and FPGA junction temperature',
memBase=memMap,
offset=0x00050000,
expand=False,
))
self.add(
linear.Ltc4151(
name='BoardPwr',
description=
'This device monitors the board power, input voltage and input current',
memBase=memMap,
offset=0x00050400,
senseRes=20.E-3, # Units of Ohms
expand=False,
))
for i in range(4):
self.add(
common.RxPhyMon(
name=('RxPhyMon[%d]' % i),
memBase=memMap,
offset=(0x01000000 * (i + 1) + 0x00100000),
expand=False,
))
self.add(
common.Timing(
name='Timing',
description=
'This device monitors the TLU and timing/trigger emulator',
memBase=memMap,
offset=0x05000000,
expand=False,
))
def __init__(
self,
name="ClinkFeb",
description="ClinkFeb Container",
serial=None,
camType=None,
enI2C=False, # disabled by default to prevent artificial timeouts due to long I2C access latency
promLoad=False,
**kwargs):
super().__init__(name=name, description=description, **kwargs)
# Init Variables for only 1 serial/camType per PGP lane
self._serial = [serial, None]
self._camType = [camType, None]
# Add devices
self.add(
axi.AxiVersion(
name='AxiVersion',
offset=0x00000000,
expand=False,
))
if promLoad:
self.add(
prom.CypressS25Fl(
name='CypressS25Fl',
offset=0x00001000,
hidden=True, # Hidden in GUI because indented for scripting
))
else:
self.add(
nxp.Sa56004x(
name='BoardTemp',
description=
'This device monitors the board temperature and FPGA junction temperature',
offset=0x00002000,
expand=False,
enabled=
False, # enabled=False because I2C are slow transactions and might "log jam" register transaction pipeline
))
self.add(
linear.Ltc4151(
name='BoardPwr',
description=
'This device monitors the board power, input voltage and input current',
offset=0x00002400,
senseRes=20.E-3, # Units of Ohms
expand=False,
enabled=
False, # enabled=False because I2C are slow transactions and might "log jam" register transaction pipeline
))
self.add(xil.Xadc(
name='Xadc',
offset=0x00003000,
expand=False,
))
for i in range(4):
self.add(
xceiver.Sfp(
name=f'Sfp[{i}]',
offset=0x00004000 + i * 0x00001000,
expand=False,
enabled=
False, # enabled=False because I2C are slow transactions and might "log jam" register transaction pipeline
))
self.add(feb.Sem(
name='Sem',
offset=0x00008000,
expand=False,
))
self.add(
cl.ClinkTop(
offset=0x00100000,
serial=self._serial,
camType=self._camType,
expand=True,
))
self.add(
feb.ClinkTrigCtrl(
name='TrigCtrl[0]',
description='Channel A trigger control',
offset=0x00200000,
expand=True,
))
self.add(
pgp.Pgp2bAxi(
name='PgpMon[0]',
offset=0x00400000,
statusCountBits=8,
errorCountBits=8,
writeEn=False,
expand=False,
))
self.add(
pgp.Pgp4AxiL(
name='PgpMon[1]',
offset=0x00410000,
numVc=4,
statusCountBits=16,
errorCountBits=8,
writeEn=False,
expand=True,
))
def __init__(
self,
name="ClinkFeb",
description="ClinkFeb Container",
serial=[None, None],
camType=[None, None],
version3=False, # true = PGPv3, false = PGP2b
**kwargs):
super().__init__(name=name, description=description, **kwargs)
# Add devices
self.add(
axi.AxiVersion(
name='AxiVersion',
offset=0x00000000,
expand=False,
))
self.add(
prom.CypressS25Fl(
name='CypressS25Fl',
offset=0x00001000,
hidden=True, # Hidden in GUI because indented for scripting
))
self.add(
nxp.Sa56004x(
name='BoardTemp',
description=
'This device monitors the board temperature and FPGA junction temperature',
offset=0x00002000,
expand=False,
))
self.add(
linear.Ltc4151(
name='BoardPwr',
description=
'This device monitors the board power, input voltage and input current',
offset=0x00002400,
senseRes=20.E-3, # Units of Ohms
expand=False,
))
self.add(xil.Xadc(
name='Xadc',
offset=0x00003000,
expand=False,
))
self.add(
cl.ClinkTop(
offset=0x00100000,
serial=serial,
camType=camType,
expand=False,
))
self.add(
feb.ClinkTrigCtrl(
name='TrigCtrl[0]',
description='Channel A trigger control',
offset=0x00200000,
expand=False,
))
self.add(
feb.ClinkTrigCtrl(
name='TrigCtrl[1]',
description='Channel B trigger control',
offset=0x00200100,
expand=False,
))
for i in range(2):
if (version3):
self.add(
pgp.Pgp3AxiL(
name=(f'PgpMon[{i}]'),
offset=(0x00400000 + i * 0x2000),
numVc=4,
writeEn=False,
expand=False,
))
# self.add(axi.AxiStreamMonitoring(
# name = (f'PgpTxAxisMon[{i}]'),
# offset = (0x00400000 + i*0x4000 + 0x4000),
# numberLanes = 4,
# expand = False,
# ))
# self.add(axi.AxiStreamMonitoring(
# name = (f'PgpRxAxisMon[{i}]'),
# offset = (0x00400000 + i*0x4000 + 0x6000),
# numberLanes = 4,
# expand = False,
# ))
else:
self.add(
pgp.Pgp2bAxi(
name=(f'PgpMon[{i}]'),
offset=(0x00400000 + i * 0x6000 + 0 * 0x2000),
writeEn=False,
expand=False,
))
def __init__( self,
name = 'Fpga',
fpgaType = '',
commType = '',
description = 'Fpga Container',
**kwargs):
super().__init__(name=name,description=description, **kwargs)
self.add(axi.AxiVersion(
offset = 0x00000000,
expand = True,
))
if(fpgaType=='7series'):
self.add(xil.Xadc(
offset = 0x00010000,
expand = False,
))
if(fpgaType=='ultrascale'):
self.add(xil.AxiSysMonUltraScale(
offset = 0x00020000,
expand = False,
))
# self.add(MbSharedMem(
# name = 'MbSharedMem',
# offset = 0x00030000,
# size = 0x10000,
# expand = False,
# ))
self.add(ssi.SsiPrbsTx(
offset = 0x00040000,
expand = False,
))
self.add(ssi.SsiPrbsRx(
offset = 0x00050000,
expand = False,
))
if ( commType == 'eth' ):
self.add(rssi.RssiCore(
offset = 0x00070000,
expand = False,
))
# self.add(udp.UdpEngine(
# offset = 0x00078000,
# numSrv = 1,
# expand = False,
# ))
self.add(axi.AxiStreamMonAxiL(
name = 'AxisMon',
offset = 0x00080000,
numberLanes = 2,
expand = False,
))
def __init__(self,
name='Fpga',
description='Container for FPGA registers',
configProm=False,
advanceUser=False,
**kwargs):
super().__init__(name=name, description=description, **kwargs)
self.add(
MyAxiVersion(
name='AxiVersion',
offset=0x00000000,
expand=False,
))
if (configProm):
self.add(
prom.AxiMicronN25Q(
name='AxiMicronN25Q',
offset=0x00020000,
hidden=True, # Hidden in GUI because indented for scripting
))
if (advanceUser):
self.add(
xil.Xadc(
name='Xadc',
offset=0x00010000,
expand=False,
hidden=True, # Hidden in GUI because indented for scripting
))
self.add(
nxp.Sa56004x(
name='BoardTemp',
description=
'This device monitors the board temperature and FPGA junction temperature',
offset=0x00040000,
expand=False,
hidden=True, # Hidden in GUI because indented for scripting
))
self.add(
linear.Ltc4151(
name='BoardPwr',
description=
'This device monitors the board power, input voltage and input current',
offset=0x00040400,
senseRes=20.E-3, # Units of Ohms
expand=False,
hidden=True, # Hidden in GUI because indented for scripting
))
self.add(
nxp.Sa56004x(
name='DelayIcTemp',
description=
'This device monitors the board temperature and Delay IC\'s temperature',
offset=0x00050000,
expand=False,
hidden=True, # Hidden in GUI because indented for scripting
))
self.add(
silabs.Si5345(
name='Pll',
description='This device contains Jitter cleaner PLL',
offset=0x00070000,
expand=False,
))
else:
self.add(
silabs.Si5345Lite(
name='Pll',
description='This device contains Jitter cleaner PLL',
offset=0x00070000,
expand=False,
))
self.add(
common.Dac(
name='Dac',
description='This device contains DAC that sets the VTH',
offset=0x00060000,
expand=False,
))
self.add(
common.Sem(
name='Sem',
description=
'This device contains FEB Soft Error Mitigation Module',
offset=0x00080000,
expand=False,
))
self.add(
common.Altiroc(
name='Asic',
description=
'This device contains all the ASIC control/monitoring',
offset=0x01000000,
asyncDev=[self.Pll.Locked
], # Only allow access after the PLL is locked
expand=True,
))