Python s_to_ns示例

示例#1

import synth_common
from synth_common import s_to_ns

trace = synth_common.create_trace()

trace.add_chrome_metadata(os_name="Android")

track1 = 1234
gpu_track = 7890

trace.add_process_track_descriptor(track1, pid=0)
trace.add_process_track_descriptor(gpu_track, pid=4)

trace.add_rail_mode_slice(
    ts=0,
    dur=s_to_ns(1),
    track=track1,
    mode=trace.prototypes.ChromeRAILMode.RAIL_MODE_RESPONSE)
trace.add_rail_mode_slice(
    ts=s_to_ns(1),
    dur=-1,
    track=track1,
    mode=trace.prototypes.ChromeRAILMode.RAIL_MODE_IDLE)

# Generate an extra trace event long after events on the renderer process have
# ceased to ensure that the RAIL mode is extended to the end of the process
# rather than the end of the trace itself.
trace.add_track_event_slice("VSync", ts=s_to_ns(25), dur=10, track=gpu_track)

sys.stdout.buffer.write(trace.trace.SerializeToString())

示例#2

文件： modified_rail_modes_with_input.py 项目： wenfei6316/perfetto

import synth_common
from synth_common import s_to_ns

trace = synth_common.create_trace()

trace.add_chrome_metadata(os_name="Android")

track1 = 1234
track2 = 4567
gpu_track = 7890

trace.add_process_track_descriptor(track1, pid=0)
trace.add_process_track_descriptor(track2, pid=2)
trace.add_process_track_descriptor(gpu_track, pid=4)

frame_period = s_to_ns(1.0 / 60)

trace.add_track_event_slice("VSync", ts=s_to_ns(3), dur=10, track=gpu_track)
trace.add_track_event_slice(
    "VSync", ts=s_to_ns(3) + frame_period, dur=10, track=gpu_track)
# Frame skipped, but modified rail mode won't go back to foreground_idle
trace.add_track_event_slice(
    "VSync", ts=s_to_ns(3) + frame_period * 3, dur=10, track=gpu_track)
# Larger gap now when mode will go to foreground_idle
trace.add_track_event_slice(
    "VSync", ts=s_to_ns(3) + frame_period * 12, dur=10, track=gpu_track)
trace.add_track_event_slice(
    "VSync", ts=s_to_ns(3) + frame_period * 13, dur=10, track=gpu_track)
trace.add_track_event_slice(
    "VSync", ts=s_to_ns(3) + frame_period * 14, dur=10, track=gpu_track)

示例#3

import synth_common
from synth_common import s_to_ns

trace = synth_common.create_trace()

trace.add_chrome_metadata(os_name="Android")

track1 = 1234
track2 = 4567

trace.add_process_track_descriptor(track1, pid=0)
trace.add_process_track_descriptor(track2, pid=2)

trace.add_rail_mode_slice(
    ts=0,
    dur=s_to_ns(1),
    track=track1,
    mode=trace.prototypes.ChromeRAILMode.RAIL_MODE_RESPONSE)
trace.add_rail_mode_slice(
    ts=s_to_ns(1),
    dur=s_to_ns(2),
    track=track1,
    mode=trace.prototypes.ChromeRAILMode.RAIL_MODE_LOAD)
trace.add_rail_mode_slice(
    ts=s_to_ns(3),
    dur=-1,
    track=track1,
    mode=trace.prototypes.ChromeRAILMode.RAIL_MODE_IDLE)

trace.add_rail_mode_slice(
    ts=0,

示例#4

文件： modified_rail_modes.py 项目： zhu0321/perfetto

import synth_common
from synth_common import s_to_ns

trace = synth_common.create_trace()

trace.add_chrome_metadata(os_name="Android")

track1 = 1234
track2 = 4567
gpu_track = 7890

trace.add_process_track_descriptor(track1, pid=0)
trace.add_process_track_descriptor(track2, pid=2)
trace.add_process_track_descriptor(gpu_track, pid=4)

frame_period = s_to_ns(1.0 / 60)

trace.add_track_event_slice("VSync", ts=s_to_ns(3), dur=10, track=gpu_track)
trace.add_track_event_slice("VSync",
                            ts=s_to_ns(3) + frame_period,
                            dur=10,
                            track=gpu_track)
# Frame skipped, but modified rail mode won't go back to foreground_idle
trace.add_track_event_slice("VSync",
                            ts=s_to_ns(3) + frame_period * 3,
                            dur=10,
                            track=gpu_track)
# Larger gap now when mode will go to foreground_idle
trace.add_track_event_slice("VSync",
                            ts=s_to_ns(3) + frame_period * 12,
                            dur=10,

示例#5

import synth_common
from synth_common import s_to_ns

trace = synth_common.create_trace()

trace.add_chrome_metadata(os_name="Android")

track1 = 1234
track2 = 4567

trace.add_process_track_descriptor(track1, pid=0)
trace.add_process_track_descriptor(track2, pid=2)

trace.add_rail_mode_slice(
    ts=0,
    dur=s_to_ns(1),
    track=track1,
    mode=trace.prototypes.ChromeRAILMode.RAIL_MODE_RESPONSE)
trace.add_rail_mode_slice(ts=s_to_ns(1),
                          dur=s_to_ns(2),
                          track=track1,
                          mode=trace.prototypes.ChromeRAILMode.RAIL_MODE_LOAD)
trace.add_rail_mode_slice(ts=s_to_ns(3),
                          dur=-1,
                          track=track1,
                          mode=trace.prototypes.ChromeRAILMode.RAIL_MODE_IDLE)

trace.add_rail_mode_slice(
    ts=0,
    dur=s_to_ns(1),
    track=track2,

示例#6

文件： modified_rail_modes_extra_long.py 项目： santakd/perfetto

import synth_common
from synth_common import s_to_ns

trace = synth_common.create_trace()

trace.add_chrome_metadata(os_name="Android")

track1 = 1234
gpu_track = 7890

trace.add_process_track_descriptor(track1, pid=0)
trace.add_process_track_descriptor(gpu_track, pid=4)

trace.add_rail_mode_slice(
    ts=0,
    dur=s_to_ns(1),
    track=track1,
    mode=trace.prototypes.ChromeRAILMode.RAIL_MODE_RESPONSE)
trace.add_rail_mode_slice(ts=s_to_ns(1),
                          dur=-1,
                          track=track1,
                          mode=trace.prototypes.ChromeRAILMode.RAIL_MODE_IDLE)

# Generate an extra trace event long after events on the renderer process have
# ceased to ensure that the RAIL mode is extended to the end of the process
# rather than the end of the trace itself.
trace.add_track_event_slice("VSync", ts=s_to_ns(1000), dur=10, track=gpu_track)

sys.stdout.buffer.write(trace.trace.SerializeToString())

示例#7

import synth_common
from synth_common import s_to_ns

trace = synth_common.create_trace()

trace.add_chrome_metadata(os_name="Android")

track1 = 1234
track2 = 4567

trace.add_process_track_descriptor(track1, pid=0)
trace.add_process_track_descriptor(track2, pid=2)

trace.add_rail_mode_slice(
    ts=0, dur=s_to_ns(1), track=track1, mode=synth_common.RAIL_MODE_RESPONSE)
trace.add_rail_mode_slice(
    ts=s_to_ns(1),
    dur=s_to_ns(2),
    track=track1,
    mode=synth_common.RAIL_MODE_LOAD)
trace.add_rail_mode_slice(
    ts=s_to_ns(3), dur=-1, track=track1, mode=synth_common.RAIL_MODE_IDLE)

trace.add_rail_mode_slice(
    ts=0, dur=s_to_ns(1), track=track2, mode=synth_common.RAIL_MODE_ANIMATION)
trace.add_rail_mode_slice(
    ts=s_to_ns(1),
    dur=s_to_ns(2.5),
    track=track2,
    mode=synth_common.RAIL_MODE_IDLE)