def config_wr(end: int) -> None:
""" send write configuration """
# CFG_KER_WR
dut.prep("cfg_data", [end])
dut.prep("cfg_addr", [1])
dut.prep("cfg_valid", [1])
dut.tick()
dut.prep("cfg_data", [0])
dut.prep("cfg_addr", [0])
dut.prep("cfg_valid", [0])
for _ in range(2):
dut.tick()
def config_rd(end: int, start: int) -> None:
""" send read configuration """
# CFG_KER_RD
dut.prep("cfg_data", [concat_cfg2(end, start)])
dut.prep("cfg_addr", [2])
dut.prep("cfg_valid", [1])
dut.tick()
dut.prep("cfg_data", [0])
dut.prep("cfg_addr", [0])
dut.prep("cfg_valid", [0])
for _ in range(2):
dut.tick()
dut.prep("cfg_data", [0])
dut.prep("cfg_addr", [0])
dut.prep("cfg_valid", [0])
for _ in range(2):
dut.tick()
dut.init()
setup()
config_wr(0)
str_data = list(range(1, 9))
for _ in range(16 * (1 + 6)):
dut.prep("str_ker_val", [1])
dut.prep("str_ker_bus", str_data)
io = dut.tick()
if io['str_ker_rdy'] == 1:
# sample the rdy to see if the data has been moved into the pipeline,
# if both rdy & val are high we increment to the 'next' data
str_data = [n + 1 for n in str_data]
dut.prep("str_ker_val", [0])
dut.prep("str_ker_bus", [0, 0, 0, 0, 0, 0, 0, 0])
dut.tick()
config_rd(5, 0)
def setup() -> None:
""" Set starting DUT values and reset module """
dut.prep("cfg_data", [0])
dut.prep("cfg_addr", [0])
dut.prep("cfg_valid", [0])
dut.prep("str_ker_val", [0])
dut.prep("str_ker_bus", [0, 0, 0, 0, 0, 0, 0, 0])
dut.prep("kernel_rdy", [0])
# reset module
dut.prep("rst", [1])
dut.tick()
dut.prep("rst", [0])
for _ in range(2):
dut.tick()
def config_write(start_addr: int, step_pixel: int, step_row: int,
img: Dict[str, int], mem_select: int) -> None:
""" send write configuration """
# CFG_IW_IMG_W
dut.prep("cfg_data", [(img['width'] - 1)])
dut.prep("cfg_addr", [9])
dut.prep("cfg_valid", [1])
dut.tick()
# CFG_IW_START
dut.prep("cfg_data", [concat_cfg2(start_addr, (img['height'] - 1))])
dut.prep("cfg_addr", [10])
dut.prep("cfg_valid", [1])
dut.tick()
# CFG_IW_STEP
dut.prep("cfg_data", [concat_cfg2((step_pixel - 1), (step_row - 1))])
dut.prep("cfg_addr", [11])
dut.prep("cfg_valid", [1])
dut.tick()
# CFG_IMG_WR
dut.prep("cfg_data", [mem_select])
dut.prep("cfg_addr", [3])
dut.prep("cfg_valid", [1])
dut.tick()
dut.prep("cfg_data", [0])
dut.prep("cfg_addr", [0])
dut.prep("cfg_valid", [0])
for _ in range(3):
dut.tick()
def config_read(img: Dict[str, int], pad: Dict[str, int], maxp_side: int,
conv: Dict[str, int], mem_select: int) -> None:
""" send read configuration """
# CFG_IR_IMG_W
dut.prep("cfg_data", [concat_cfg1(img['width'] - 1)])
dut.prep("cfg_addr", [5])
dut.prep("cfg_valid", [1])
dut.tick()
# CFG_IR_IMG_DH
dut.prep("cfg_data",
[concat_cfg2((img['depth'] - 1), (img['height'] - 1))])
dut.prep("cfg_addr", [6])
dut.prep("cfg_valid", [1])
dut.tick()
# CFG_IR_PAD
dut.prep(
"cfg_data",
[concat_cfg4(pad['left'], pad['right'], pad['top'], pad['bottom'])])
dut.prep("cfg_addr", [7])
dut.prep("cfg_valid", [1])
dut.tick()
# CFG_IR_CONV
dut.prep("cfg_data", [
concat_cfg4((maxp_side - 1), (conv['side'] - 1), 0, (conv['step'] - 1))
])
dut.prep("cfg_addr", [8])
dut.prep("cfg_valid", [1])
dut.tick()
# CFG_IMG_RD
dut.prep("cfg_data", [0])
dut.prep("cfg_addr", [4])
dut.prep("cfg_valid", [1])
dut.tick()
dut.prep("cfg_data", [0])
dut.prep("cfg_addr", [0])
dut.prep("cfg_valid", [0])
for _ in range(3):
dut.tick()
def setup():
""" Set starting DUT values and reset module """
dut.prep("cfg_data", [0])
dut.prep("cfg_addr", [0])
dut.prep("cfg_valid", [0])
dut.prep("str_img_bus", [0])
dut.prep("str_img_val", [0])
dut.prep("image_rdy", [0])
# reset module
dut.prep("rst", [1])
dut.tick()
dut.prep("rst", [0])
for _ in range(2):
dut.tick()
img_width * img_height * step_pixel *
(param['IMG_WIDTH'] * param['DEPTH_NB'] / param['STR_IMG_WIDTH']))
dut.init()
setup()
config_write(start_addr, step_pixel, step_row, {
'width': img_width,
'height': img_height,
'depth': img_depth
}, wr_mem_select)
cnt = 1
for _ in range(stream_nb):
dut.prep("str_img_val", [1])
dut.prep("str_img_bus", [cnt])
io = dut.tick()
if io['str_img_rdy'] == 1:
# sample the rdy to see if the data has been moved into the pipeline,
# if both rdy & val are high we increment to the 'next' data
cnt = cnt + 1
dut.prep("str_img_val", [0])
dut.prep("str_img_bus", [0])
config_read({
'width': img_width,
'height': img_height,
def config(img: Dict[str, int],
pad: Dict[str, int],
maxp_side: int, conv: Dict[str, int]
) -> None:
""" send configuration """
# CFG_IR_IMG_W
dut.prep("cfg_data", [concat_cfg1(img['width']-1)])
dut.prep("cfg_addr", [5])
dut.prep("cfg_valid", [1])
io = dut.tick()
# CFG_IR_IMG_DH
dut.prep("cfg_data", [concat_cfg2((img['depth']-1), (img['height']-1))])
dut.prep("cfg_addr", [6])
dut.prep("cfg_valid", [1])
io = dut.tick()
# CFG_IR_PAD
dut.prep("cfg_data", [concat_cfg4(pad['left'], pad['right'],
pad['top'], pad['bottom'])])
dut.prep("cfg_addr", [7])
dut.prep("cfg_valid", [1])
io = dut.tick()
# CFG_IR_CONV
dut.prep("cfg_data", [concat_cfg4((maxp_side-1), (conv['side']-1),
0, (conv['step']-1))])
dut.prep("cfg_addr", [8])
dut.prep("cfg_valid", [1])
io = dut.tick()
dut.prep("cfg_data", [0])
dut.prep("cfg_addr", [0])
dut.prep("cfg_valid", [0])
for _ in range(3):
io = dut.tick()
# register next configuration
dut.prep("next", [1])
io = dut.tick()
while not io["next_rdy"]:
# wait on next handshake if next_rdy is not high
io = dut.tick()
dut.prep("next", [0])
io = dut.tick()
setup()
config(
{'width': img_width, 'height': img_height, 'depth': img_depth},
{'left': pad_left, 'right': pad_right, 'top': pad_top, 'bottom': pad_bottom},
maxp_side,
{'side': conv_side, 'step': conv_step})
rd_data_2p = 0
rd_data_1p = 0
rd_data = 0
dut.prep("image_rdy", [1])
for _ in range(6):
io = dut.tick()
# start generating software model addresses
for model_addr in model:
io = dut.tick()
if io['rd_val'] == 0:
assert model_addr == None
dut.prep("rd_data", [0])
else:
assert model_addr == io['rd_addr']
rd_data = rd_data_1p
rd_data_1p = rd_data_2p
def prep(port: str, value: List[int]):
dut.prep(port, value)