################################################################################
import trap
#---------------------------------------------------------
# Instruction Encoding
#---------------------------------------------------------
# Lets now start with defining the instructions, i.e. their bitstring and
# mnemonic and their behavior. Note the zero* field: it is a special identifier and it
# means that all those bits have value 0; the same applies for one*
# In MICROBLAZE there are two types of instructions: typeA and typeB.
# Obviously, there are many variants for each type.
#OPER with REG
oper_reg = trap.MachineCode([('opcode0', 6), ('rd', 5), ('ra', 5), ('rb', 5),
('opcode1', 11)])
oper_reg.setVarField('rd', ('GPR', 0), 'out')
oper_reg.setVarField('ra', ('GPR', 0), 'in')
oper_reg.setVarField('rb', ('GPR', 0), 'in')
#OPER with IMM
oper_imm = trap.MachineCode([('opcode', 6), ('rd', 5), ('ra', 5), ('imm', 16)])
oper_imm.setVarField('rd', ('GPR', 0), 'out')
oper_imm.setVarField('ra', ('GPR', 0), 'in')
#BRANCH COND with REG
branch_cond_reg = trap.MachineCode([('opcode0', 6), ('opcode1', 5), ('ra', 5),
('rb', 5), ('opcode2', 11)])
branch_cond_reg.setVarField('ra', ('GPR', 0), 'in')
branch_cond_reg.setVarField('rb', ('GPR', 0), 'in')
# # (c) Luca Fossati, [email protected], [email protected] # ################################################################################ import trap #--------------------------------------------------------- # Instruction Encoding #--------------------------------------------------------- # Lets now start with defining the instructions, i.e. their bitstring and # mnemonic and their behavior (look at page 68 of the ARM Architecture # Reference Manual). Note the zero* field: it is a special identifier and it # means that all those bits have value 0; the same applies for one* dataProc_imm_shift = trap.MachineCode([('cond', 4), ('zero', 3), ('opcode', 4), ('s', 1), ('rn', 4), ('rd', 4), ('shift_amm', 5), ('shift_op', 2), ('zero', 1), ('rm', 4)]) # All of the register specifiers are indexes in the registry bank REGS, # with no offset (so we access them directly, REGS[rn]) dataProc_imm_shift.setVarField('rn', ('REGS', 0), 'in') dataProc_imm_shift.setVarField('rd', ('REGS', 0), 'out') dataProc_imm_shift.setVarField('rm', ('REGS', 0), 'in') dataProc_reg_shift = trap.MachineCode([('cond', 4), ('zero', 3), ('opcode', 4), ('s', 1), ('rn', 4), ('rd', 4), ('rs', 4), ('zero', 1), ('shift_op', 2), ('one', 1), ('rm', 4)]) dataProc_reg_shift.setVarField('rn', ('REGS', 0), 'in') dataProc_reg_shift.setVarField('rd', ('REGS', 0), 'out') dataProc_reg_shift.setVarField('rm', ('REGS', 0), 'in') dataProc_reg_shift.setVarField('rs', ('REGS', 0), 'in') dataProc_imm = trap.MachineCode([('cond', 4), ('id', 3), ('opcode', 4),
#
################################################################################
import trap
#---------------------------------------------------------
# Instruction Encoding
#---------------------------------------------------------
# Lets now start with defining the instructions, i.e. their bitstring and
# mnemonic and their behavior. Note the zero* field: it is a special identifier and it
# means that all those bits have value 0; the same applies for one*
# As stated in page 44 of "The SPARC Architecture Manual V8" there are
# mainly 6 different format types
# Call instruction format
call_format = trap.MachineCode([('op', 2), ('disp30', 30)])
call_format.setBitfield('op', [0, 1])
# Branch and sethi instructions format
b_sethi_format1 = trap.MachineCode([('op', 2), ('rd', 5), ('op2', 3),
('imm22', 22)])
b_sethi_format1.setBitfield('op', [0, 0])
b_sethi_format1.setVarField('rd', ('REGS', 0), 'out')
b_sethi_format2 = trap.MachineCode([('op', 2), ('a', 1), ('cond', 4),
('op2', 3), ('disp22', 22)])
b_sethi_format2.setBitfield('op', [0, 0])
# Memory instruction format
mem_format1 = trap.MachineCode([('op', 2), ('rd', 5), ('op3', 6), ('rs1', 5),
('zero', 1), ('asi', 8), ('rs2', 5)])
mem_format1.setBitfield('op', [1, 1])