def run():
site = sorted(gen_lut_sites())[0]
print('''
module top();
wire o;
(* KEEP, DONT_TOUCH, LOC = "{loc}" *)
LUT6 #(.INIT(0) ) lut (
.I0(1),
.I1(1),
.I2(1),
.I3(1),
.I4(1),
.I5(1),
.O(o)
);
endmodule
'''.format(loc=site))
sites = list(gen_sites())
with open('gen_params.csv', 'w') as f:
for site, isone in zip(sorted(sites),
util.gen_fuzz_states(len(sites))):
f.write('{},{}\n'.format(site, isone))
def run():
print('''
module top();
''')
params = {}
sites = list(gen_sites())
for (tile_name, site_name), isone in zip(sites,
util.gen_fuzz_states(len(sites))):
params[tile_name] = (site_name, isone)
print('''
(* KEEP, DONT_TOUCH, LOC = "{loc}", LOCK_PINS="I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6" *)
wire loop_{loc};
LUT6 #(.INIT(64'b{isone}) ) lut_{loc} (
.I0(loop_{loc}),
.I1(1),
.I2(1),
.I3(1),
.I4(1),
.I5(1),
.O(loop_{loc})
);
'''.format(
loc=site_name,
isone=isone,
))
print("endmodule")
write_params(params)
def run():
site = sorted(gen_lut_sites())[0]
print('''
module top();
wire o;
(* KEEP, DONT_TOUCH, LOC = "{loc}" *)
LUT6 #(.INIT(0) ) lut (
.I0(1),
.I1(1),
.I2(1),
.I3(1),
.I4(1),
.I5(1),
.O(o)
);
endmodule
'''.format(loc=site))
bufce_leaf_sites = gen_sites()
params = {}
num_tiles = len(bufce_leaf_sites)
itr = iter(util.gen_fuzz_states(num_tiles))
for tile in sorted(bufce_leaf_sites.keys()):
for site in sorted(bufce_leaf_sites[tile],
key=lambda site: get_site_xy(site))[:1]:
params[tile] = (site, next(itr))
write_params(params)
def run():
site = sorted(gen_lut_sites())[0]
print('''
module top();
wire o;
(* KEEP, DONT_TOUCH, LOC = "{loc}" *)
LUT6 #(.INIT(0) ) lut (
.I0(1),
.I1(1),
.I2(1),
.I3(1),
.I4(1),
.I5(1),
.O(o)
);
endmodule
'''.format(loc=site))
site_pairs = gen_sites()
# The placer will not accept BUFCE_LEAF or BUFCE_ROW instances, so create
# and connect those cells after placement.
with open('params.csv', 'w') as f:
print('tile,val,left_bufce_out,right_bufce_out,left_site,right_site',
file=f)
for (tile, left_bufce_out, right_bufce_out, left_site,
right_site), isone in zip(site_pairs,
util.gen_fuzz_states(len(site_pairs))):
print(','.join((tile, str(isone), left_bufce_out, right_bufce_out,
left_site, right_site)),
file=f)
def run():
params = {}
sites = list(gen_sites())
assert len(sites) == 1
itr = iter(util.gen_fuzz_states(len(sites)))
for (tile_name, site_name) in sites:
isone = next(itr)
params[tile_name] = (site_name, isone)
print(
util.render_template(os.path.join(os.getenv("FUZDIR"), "top.tpl"),
{"isone": isone}))
write_params(params)
def run():
sites_by_tile = gen_sites()
print('''
module top(output [{number_outputs}-1:0] out);
wire o;
(* KEEP, DONT_TOUCH *)
LUT6 #(.INIT(0) ) lut (
.I0(1),
.I1(1),
.I2(1),
.I3(1),
.I4(1),
.I5(1),
.O(o)
);
'''.format(number_outputs=len(sites_by_tile)))
itr = iter(util.gen_fuzz_states(len(sites_by_tile)))
if os.environ['URAY_ARCH'] == "UltraScalePlus":
device = "ULTRASCALE_PLUS"
elif os.environ['URAY_ARCH'] == "UltraScale":
device = "ULTRASCALE"
else:
assert False, device
params = []
for idx, (tile, isone) in enumerate(zip(sorted(sites_by_tile.keys()),
itr)):
params.append((tile, isone))
print("""
(* KEEP, DONT_TOUCH, LOC="{loc}" *)
TX_BITSLICE #(
.INIT({isone}),
.SIM_DEVICE("{device}")
) tx_{idx} (
.O(out[{idx}])
);
""".format(loc=sites_by_tile[tile][0],
isone=isone,
device=device,
idx=idx))
print('endmodule')
write_params(params)
def run(tile_type):
sites_by_tile = gen_sites(tile_type)
print('''
`define N_DI {}
module top(input wire [`N_DI-1:0] di);
wire [`N_DI-1:0] di_buf;
'''.format(len(sites_by_tile)))
params = []
print('''
(* KEEP, DONT_TOUCH *)
LUT6 dummy_lut();''')
for idx, (tile_name, isone) in enumerate(
zip(
sorted(sites_by_tile.keys()),
util.gen_fuzz_states(len(sites_by_tile)))):
site_name = sites_by_tile[tile_name][0]
params.append((tile_name, site_name, isone, "di[%u]" % idx))
print('''
(* KEEP, DONT_TOUCH, LOC="{site_name}" *)
IBUF #(
) ibuf_{site_name} (
.I(di[{idx}]),
.O(di_buf[{idx}])
);'''.format(site_name=site_name, idx=idx))
if isone:
print('''
(* KEEP, DONT_TOUCH *)
PULLUP #(
) pullup_{site_name} (
.O(di[{idx}])
);'''.format(site_name=site_name, idx=idx))
print("endmodule")
write_params(params)
def run():
print('''
module top();
''')
params = {}
sites = sorted(list(gen_sites()))
for (tile_name, site_name), isone in zip(sites,
util.gen_fuzz_states(len(sites))):
params[tile_name] = (site_name, isone)
print('''
(* KEEP, DONT_TOUCH, LOC = "{loc}", LOCK_PINS="I0:A1, I1:A2, I2:A3, I3:A4, I4:A5, I5:A6" *)
wire loop_{loc};
LUT6 #(.INIT(64'hFFFFFFFFFFFFFFFF) ) lutc_{loc} (
.I0(1),
.I1(1),
.I2(1),
.I3({loop}),
.I4(loop_{loc}),
.I5(1),
.O(loop_{loc})
);
(* KEEP, DONT_TOUCH, LOC = "{loc}", LOCK_PINS="I0:A1, I1:A2, I2:A3, I3:A4, I4:A5, I5:A6" *)
LUT6 #(.INIT(64'hFFFFFFFFFFFFFFFF) ) lutd_{loc} (
.I0(1),
.I1(1),
.I2(1),
.I3(loop_{loc}),
.I4(loop_{loc}),
.I5(1)
);
'''.format(loc=site_name, loop=1 if isone else ('loop_' + site_name)))
print("endmodule")
write_params(params)
def run():
print('''
module top();
''')
params = {}
sites = list(gen_sites())
for (tile_name, site_name), isone in zip(sites,
util.gen_fuzz_states(len(sites))):
params[tile_name] = (site_name, isone)
print('''
(* KEEP, DONT_TOUCH, LOC = "{site_name}" *)
RAMB18E2 #(
.INIT_00(256'b{isone})
) bram_{site_name} ();'''.format(
site_name=site_name,
isone=isone,
))
print("endmodule")
write_params(params)
def run():
site = sorted(gen_lut_sites())[0]
print('''
module top();
'''.format(loc=site))
luts = LutMaker()
ps8_pin_map = get_ps8_pin_map()
bus_widths = {}
for pin in ps8_pin_map.values():
parts = pin.split('/')[-1].split('[')
if len(parts) == 1:
bus_widths[parts[0]] = 1
elif len(parts) == 2:
if parts[0] not in bus_widths:
bus_widths[parts[0]] = 0
width = int(parts[1][:-1]) + 1
if width > bus_widths[parts[0]]:
bus_widths[parts[0]] = width
else:
assert False, pin
tile_and_bel_pins = pick_ps8_wire(ps8_pin_map)
sinks = []
with open('params.csv', 'w') as f:
print('tile,val', file=f)
pins = []
for (tile,
pin), isone in zip(tile_and_bel_pins,
util.gen_fuzz_states(len(tile_and_bel_pins))):
print('{tile},{isone}'.format(tile=tile, isone=isone), file=f)
if isone:
sinks.append(luts.get_next_input_net())
pins.append(pin)
print('\n'.join(luts.create_wires_and_luts()))
sinks.sort()
random.shuffle(sinks)
busses = set()
for pin in pins:
busses.add(pin.split('[')[0])
for bus in busses:
print('wire [{width}-1:0] {bus};'.format(bus=bus,
width=bus_widths[bus]))
print('PS8 ps8 (')
connections = []
for bus in busses:
connections.append(' .{bus}({bus})'.format(bus=bus))
print(',\n'.join(connections))
print('\n);')
for pin in pins:
print('assign {} = {};'.format(pin, sinks.pop()))
print('endmodule')
def run():
print('''
module top(input clk, stb, di, output do);
localparam integer DIN_N = 8;
localparam integer DOUT_N = 8;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
''')
params = {}
sites = list(gen_sites())
for (tile_name, site_name), isone in zip(sites,
util.gen_fuzz_states(len(sites))):
params[tile_name] = (site_name, isone)
print('''
(* KEEP, DONT_TOUCH, LOC = "%s" *)
RAMB18E2 #(
.DOA_REG(%u)
) bram_%s (
.CLKARDCLK(),
.CLKBWRCLK(),
.ENARDEN(),
.ENBWREN(),
.REGCEAREGCE(),
.REGCEB(),
.RSTRAMARSTRAM(),
.RSTRAMB(),
.RSTREGARSTREG(),
.RSTREGB(),
.ADDRARDADDR(),
.ADDRBWRADDR(),
.DINADIN(),
.DINBDIN(),
.DINPADINP(),
.WEA(),
.WEBWE(),
.DOUTADOUT(),
.DOUTBDOUT(),
.DOUTPADOUTP(),
.DOUTPBDOUTP());
''' % (site_name, isone, site_name))
print("endmodule")
write_params(params)
