async def body(self):
uvm_info(self.get_type_name(),
sv.sformatf("%s starting...", self.get_sequence_path()),
UVM_MEDIUM)
# READ A RANDOM LOCATION
self.read_byte_seq0 = read_byte_seq("read_byte_seq")
await uvm_do_with(self, self.read_byte_seq0, {})
self.addr_check = self.read_byte_seq0.rsp.addr
self.m_data0_check = self.read_byte_seq0.rsp.data[0] + 1
# WRITE MODIFIED READ DATA
self.write_byte_seq0 = write_byte_seq("write_byte_seq")
self.write_byte_seq0.start_addr = self.addr_check
self.write_byte_seq0.data0 = self.m_data0_check
await uvm_do_with(self, self.write_byte_seq0, {})
# { write_byte_seq0.start_addr == addr_check;
# write_byte_seq0.data0 == m_data0_check; } )
self.m_data0_check = write_byte_seq.last_data
# // READ MODIFIED WRITE DATA
self.read_byte_seq0.start_addr = self.addr_check
await uvm_do_with(self, self.read_byte_seq0,
lambda start_addr: start_addr == self.addr_check)
data0_got = int(self.read_byte_seq0.rsp.data[0])
if self.m_data0_check != data0_got:
uvm_error(
self.get_type_name(),
sv.sformatf(
"%s Read Modify Write Read error!\n\tADDR: %h, EXP: %h, ACT: %h",
self.get_sequence_path(), self.addr_check,
self.m_data0_check, data0_got))
else:
self.test_pass = True
def build(self):
# create
self.ID = dut_ID.type_id.create("ID")
self.DATA = dut_DATA.type_id.create("DATA")
for i in range(self.nsockets):
socket = dut_SOCKET.type_id.create(sv.sformatf("SOCKET[%0d]", i))
self.SOCKET.append(socket)
self.RAM = dut_RAM.type_id.create("DMA_RAM")
# configure/build registers
self.ID.configure(self, None, "ID")
self.ID.build()
self.DATA.configure(self, None, "DATA")
self.DATA.build()
for i in range(len(self.SOCKET)):
self.SOCKET[i].configure(self, None, sv.sformatf("SOCKET[%0d]", i))
self.SOCKET[i].build()
self.RAM.configure(self, "DMA")
# define default map/add register to map
self.default_map = self.create_map("default_map", 0x0, 4,
UVM_LITTLE_ENDIAN, 1)
self.default_map.add_reg(self.ID, 0x0, "RW")
self.default_map.add_reg(self.DATA, 0x24, "RW")
for i in range(len(self.SOCKET)):
self.default_map.add_reg(self.SOCKET[i], 0x1000 + 16 * i, "RW")
self.default_map.add_mem(self.RAM, 0x2000, "RW")
def body(self):
uvm_info(self.get_type_name(),
sv.sformatf("%s starting...", self.get_sequence_path()),
UVM_MEDIUM)
# READ A RANDOM LOCATION
self.read_byte_seq0 = read_byte_seq("read_byte_seq")
yield uvm_do_with(self, self.read_byte_seq0, {})
self.addr_check = self.read_byte_seq0.rsp.addr
self.m_data0_check = self.read_byte_seq0.rsp.data[0] + 1
# WRITE MODIFIED READ DATA
self.write_byte_seq0 = write_byte_seq("write_byte_seq")
self.write_byte_seq0.start_addr = self.addr_check
self.write_byte_seq0.data0 = self.m_data0_check
yield uvm_do_with(self, self.write_byte_seq0, {})
# { write_byte_seq0.start_addr == addr_check;
# write_byte_seq0.data0 == m_data0_check; } )
# // READ MODIFIED WRITE DATA
self.read_byte_seq0.start_addr = self.addr_check
yield uvm_do_with(self, self.read_byte_seq0, {})
# { read_byte_seq0.start_addr == addr_check; } )
if self.m_data0_check != int(self.read_byte_seq0.rsp.data[0]):
uvm_error(
self.get_type_name(),
sv.sformatf(
"%s Read Modify Write Read error!\n\tADDR: %h, EXP: %h, ACT: %h",
self.get_sequence_path(), self.addr_check,
self.m_data0_check, int(self.read_byte_seq0.rsp.data[0])))
def memory_verify(self, trans):
data = 0
exp = 0
for i in range(trans.size):
# Check to see if entry in associative array for this address when read
# If so, check that transfer data matches associative array data.
if (trans.addr + i) in self.m_mem_expected:
if trans.read_write == READ:
data = trans.data[i]
uvm_info(
self.get_type_name(),
sv.sformatf(
"%s to existing address...Checking address : %0h with data : %0h",
str(trans.read_write), int(trans.addr), int(data)),
UVM_LOW)
if not (self.m_mem_expected[trans.addr + i]
== trans.data[i]):
exp = self.m_mem_expected[trans.addr + i]
uvm_error(
self.get_type_name(),
sv.sformatf(
"Read data mismatch. Expected : %0h. Actual : %0h",
exp, data))
self.sbd_error = True
self.num_init_reads += 1
if trans.read_write == WRITE:
data = trans.data[i]
uvm_info(
self.get_type_name(),
sv.sformatf(
"Op %s to existing address...Updating address : %0h with data : %0h",
str(trans.read_write), int(trans.addr + i),
int(data)), UVM_LOW)
self.m_mem_expected[trans.addr + i] = trans.data[i]
self.num_writes += 1
# Check to see if entry in associative array for this address
# If not, update the location regardless if read or write.
else:
data = trans.data[i]
uvm_info(
self.get_type_name(),
sv.sformatf(
"%s to empty address...Updating address : %0h with data : %0h",
str(trans.read_write), int(trans.addr + i), int(data)),
UVM_LOW)
self.m_mem_expected[trans.addr + i] = trans.data[i]
if trans.read_write == READ:
self.num_uninit_reads += 1
elif (trans.read_write == WRITE):
self.num_writes += 1
def body(self):
#p = None # uvm_phase
uvm_info(self.get_type_name(),
sv.sformatf("%s starting...", self.get_sequence_path()),
UVM_MEDIUM)
#$cast(req, create_item(ubus_transfer::get_type(), p_sequencer, "req"))
#p = self.get_starting_phase()
self.req = self.create_item(ubus_transfer.get_type(), self.p_sequencer,
"req")
while True:
util_transfer = []
yield self.p_sequencer.addr_ph_port.peek(util_transfer)
self.util_transfer = util_transfer[0]
_print("slave_mem_seq after peek. Got util_xfer: " +
self.util_transfer.convert2string())
# Need to raise/drop objection before each item because we don't want
# to be stopped in the middle of a transfer.
#p.raise_objection(self)
_print("BEFORE start_item. req is " + self.req.convert2string())
yield self.start_item(self.req)
_print("after start_item")
yield self.finish_item(self.req)
_print("after finish_item")
def body(self):
#reg_block_slave model
#sv.cast(model, self.model)
model = self.model
for i in range(1):
default_map = model.INDEX.get_default_map()
status = []
idx = sv.urandom_range(0, 255)
yield model.INDEX.write(status, idx, _map=default_map, parent=self)
status = []
yield model.INDEX.mirror(status, UVM_CHECK, UVM_FRONTDOOR,
default_map, self)
got = model.INDEX.get()
if idx != got:
uvm_error("IDX_ERR", "exp: " + str(idx) + ' got: ' + str(got))
for i in range(5):
status = []
idx = sv.urandom_range(0, (1 << 64) - 1)
yield model.SESSION[i].SRC.write(status,
idx,
_map=default_map,
parent=self)
status = []
yield model.SESSION[i].SRC.mirror(status, UVM_CHECK,
UVM_FRONTDOOR, default_map,
self)
# Randomize the content of 10 random indexed registers
#for i in range(10):
for i in range(1):
idx = sv.urandom_range(0, 255)
data = sv.urandom()
status = []
default_map = model.TABLES[idx].get_default_map()
print("Writing to TABLES idx " + str(idx))
yield model.TABLES[idx].write(status,
data,
_map=default_map,
parent=self)
print("AFTER Writing to TABLES idx " + str(idx))
# Find which indexed registers are non-zero
#for i in range(len(model.TABLES)):
for i in range(1):
data = []
status = []
print("Reading from TABLES idx " + str(i))
yield model.TABLES[i].read(status, data)
if data[0] != 0:
print(sv.sformatf("TABLES[%0d] is 0x%h...", i, data[0]))
def convert2string(self):
convert2string = sv.sformatf("dev=%h.%h kind=%s hndsk=%s data=h",
self.addr, self.endp, int(self.kind),
self.status.name)
ndata = len(self.data)
if ndata == 0:
return convert2string + "[]"
if ndata == 1:
return sv.sformatf("%s0x%h", convert2string, self.data[0])
if ndata == 2:
return sv.sformatf("%s0x%h 0x%h", convert2string, self.data[0],
self.data[1])
if ndata == 3:
return sv.sformatf("%s0x%h 0x%h 0x%h", convert2string,
self.data[0], self.data[1], self.data[2])
return sv.sformatf("%s0x%h 0x%h .. 0x%h (%0d bytes)", convert2string,
self.data[0], self.data[1], self.data[-1],
len(self.data))
def collect_transactions(self):
while True:
yield self.collect_arbitration_phase()
yield self.collect_address_phase()
yield self.collect_data_phase()
uvm_info("UBUS_MON", sv.sformatf("Transfer collected :\n%s",
self.trans_collected.sprint()), UVM_HIGH)
if (self.checks_enable):
self.perform_transfer_checks()
if (self.coverage_enable):
self.perform_transfer_coverage()
self.item_collected_port.write(self.trans_collected)
def check_which_slave(self):
slave_name = ""
slave_found = False
for slave_name in self.slave_addr_map:
if (self.slave_addr_map[slave_name].get_min_addr() <= self.trans_collected.addr
and self.trans_collected.addr <=
self.slave_addr_map[slave_name].get_max_addr()):
self.trans_collected.slave = slave_name
self.slave_found = True
if self.slave_found is True:
break
if slave_found is False:
uvm_error(self.get_type_name(),
sv.sformatf("Master attempted a transfer at illegal address 16'h%0h",
self.trans_collected.addr))
async def run_phase(self, phase):
phase.raise_objection(self)
env = self.get_child("env")
if env is None:
uvm_fatal("test", "Cannot find tb_env")
await self.reset_dut()
#env.regmodel.reset()
clk_fork = cocotb.fork(MyClock(self.dut).start(2000))
#uvm_reg_sequence seq;
seq = UVMRegHWResetSeq.type_id.create("reg_hw_rst_seq")
seq.model = env.regmodel
print("Before seq.start. Wait for seq state")
await seq.start(None)
print("seq.start was called. Wait for seq state")
await seq.wait_for_sequence_state(UVM_FINISHED)
print("AFTER yield seq.wait_for_sequence_state(UVM_FINISHED)")
nwrites = 8
uvm_info("Test", "Performing " + str(nwrites) + " writes...", UVM_LOW)
for i in range(nwrites):
status = []
uvm_info("WRITE", sv.sformatf("Write[%0d] now", i), UVM_LOW)
await env.regmodel.user_acp.write(status, sv.random())
if status[0] == UVM_NOT_OK:
raise Exception("Reg_write " + i + " failed with UVM_NOT_OK")
else:
uvm_info("WRITE_DONE", "UVM_OK status returned for write " +
str(i), UVM_LOW)
status = []
print("Now mirroring the reg status..")
await env.regmodel.user_acp.mirror(status, UVM_CHECK)
await self.reset_dut()
status = []
print("Now mirroring the reg status after reset")
await env.regmodel.user_acp.mirror(status, UVM_CHECK)
await Timer(100, "NS")
clk_fork.kill()
phase.drop_objection(self)
def collect_arbitration_phase(self):
tmpStr = ""
# @(posedge vif.sig_clock iff (vif.sig_grant != 0))
while True:
yield RisingEdge(self.vif.sig_clock)
if self.vif.sig_grant != 0:
break
self.status.bus_state = ARBI
self.state_port.write(self.status)
self.begin_tr(self.trans_collected)
# Check which grant is asserted to determine which master is performing
# the transfer on the bus.
#for (int j = 0; j <= 15; j++):
for j in range(16):
if (self.vif.sig_grant.value[j] == 1):
tmpStr = sv.sformatf("masters[%0d]", j)
self.trans_collected.master = tmpStr
break
async def body(self):
self.req.data = [1234]
self.req.addr = self.start_addr
self.req.read_write = READ
self.req.size = 1
self.req.error_pos = 1000
self.req.transmit_delay = self.transmit_delay
await uvm_do_with(self, self.req, lambda addr: addr == self.start_addr)
# { req.addr == start_addr
# req.read_write == READ
# req.size == 1
# req.error_pos == 1000
# req.transmit_delay == transmit_del; } )
rsp = []
await self.get_response(rsp)
self.rsp = rsp[0]
uvm_info(self.get_type_name(),
sv.sformatf("%s read : addr = `x{}, data[0] = `x{}",
self.get_sequence_path(), self.rsp.addr, self.rsp.data[0]),
UVM_HIGH)
def body(self):
req = ubus_transfer()
req.data.append(self.data0)
req.addr = self.start_addr
req.size = 1
req.error_pos = 1000
req.read_write = WRITE
req.transmit_delay = self.transmit_delay
yield uvm_do_with(self, req, {})
# { req.addr == start_addr
# req.read_write == WRITE
# req.size == 1
# req.data[0] == data0
# req.error_pos == 1000
# req.transmit_delay == transmit_del; } )
uvm_info(
self.get_type_name(),
sv.sformatf("%s wrote : addr = `x%0h, data[0] = `x%0h",
self.get_sequence_path(), req.addr, req.data[0]),
UVM_HIGH)
