async def initial_begin(dut): cs_ = UVMCoreService.get() env = tb_env("env") print(str(dir(simulator))) print(str(dir(dut))) vif = apb_if(dut) uvm_hdl.set_dut(dut) #root = simulator.get_root_handle() #print(str(dir(root))) cocotb.fork(Clock(vif.clk, 10, "NS").start()) svr = cs_.get_report_server() svr.set_max_quit_count(10) seq_name = [] if sv.value_plusargs("UVM_SEQUENCE=%s", seq_name): seq = UVMUtils.create_type_by_name(seq_name[0], "tb") if seq is None: uvm_fatal( "NO_SEQUENCE", "This env requires you to specify the sequence to run using UVM_SEQUENCE=<name>" ) env.seq = seq UVMConfigDb.set(env, "apb", "vif", vif) UVMConfigDb.set(None, "DUT_REF", "dut", dut) await run_test()
async def run_phase(self, phase): phase.raise_objection(self) await Timer(10, "NS") print("{}: {} HI".format(get_sim_time(), self.get_full_name())) await Timer(10, "NS") if self.comp_id == 2: uvm_fatal("COMP_ID_2", "run_phase() should be killed before fatal") phase.drop_objection(self)
async def initial_begin(dut): t = top("top", None) # Randomize all of the delays t.randomize() # cast to 'void' removed await run_test() if sv.realtime("NS") != test_duration: uvm_fatal("TIME_ERR", "Exp: {}, Got: {}".format(test_duration, sv.realtime("NS"))) svr = UVMCoreService.get().get_report_server() num_errors = svr.get_severity_count(UVM_ERROR) if num_errors > 0: uvm_fatal("SERVER_HAD_ERRORS", "Num UVM_ERRORS: {}".format(num_errors))
def initial(dut): print("dut parameter NUM_BLKS: " + str(dut.NUM_BLKS)) env = sys_env("env") vif = apb_if(dut) UVMConfigDb.set(env, "apb", "vif", vif) c = Clock(dut.apb_pclk, 10, 'ns') cocotb.fork(c.start()) yield run_test() if env.all_ok is False: uvm_fatal("ALL_NOT_OK", "env.all_ok == False, something went wrong!") else: uvm_info("ALL_OK", "*** TEST PASSED ***", UVM_NONE)
async def run_phase(self, phase): status = 0x0 data = 0x0 expected = [] max_val = 0 FIFO = None # fifo_reg regmodel = self.regmodel dut = [] UVMConfigDb.get(None, "DUT_REF", "dut", dut) dut = dut[0] #regmodel.default_map.set_auto_predict(on=True) regmodel.default_map.set_check_on_read(on=False) phase.raise_objection(self) uvm_info("Test", "Resetting DUT and Register Model...", UVM_LOW) rst_seq = dut_reset_seq.type_id.create("rst_seq", self) rst_seq.dut_top = dut await rst_seq.start(None) regmodel.reset() FIFO = regmodel.FIFO max_val = FIFO.capacity() FIFO.set_compare(UVM_CHECK) uvm_info( "FIFO Example", sv.sformatf( "Initializing FIFO reg of max_val size %0d with set()...", max_val), UVM_LOW) expected = [0] * max_val # SET - preload regmodel; remodel now has full FIFO; DUT still empty for i in range(len(expected)): data = sv.urandom() expected[i] = data FIFO.set(data) uvm_info( "FIFO Example", sv.sformatf("Updating DUT FIFO reg with mirror using update()..."), UVM_LOW) # UPDATE - write regmodel contents to DUT; DUT now has full FIFO status = [] await FIFO.update(status) if status[0] == UVM_NOT_OK: uvm_fatal("FIFO Update Error", "Received status UVM_NOT_OK updating DUT") uvm_info( "FIFO Example", sv.sformatf(" Read back DUT FIFO reg into mirror using read()..."), UVM_LOW) print("Before starting to read, FIFO contents: " + str([hex(no) for no in FIFO.fifo])) # READ - read contents of DUT back to regmodel; DUT is empty now, regmodel FULL for i in range(len(expected)): status = [] data = [] await FIFO.read(status, data) if status[0] == UVM_NOT_OK: uvm_fatal( "FIFO Read Error", "Read status UVM_NOT_OK, read {}, data: {}".format( i, data)) else: uvm_info("FIFO Read OK", "Read {}, got data: {}".format(i, data), UVM_LOW) phase.drop_objection(self)