def test_const(const_value):
a = pe.const(const_value)
tests = complete(a, 4, 16)
compile(f'test_const_complete', 'test_pe_comp_unq1', a.opcode, tests)
run_verilator_test('test_pe_comp_unq1', f'sim_test_const_complete', 'test_pe_comp_unq1')
def test_signed_op(signed_op, signed):
a = getattr(pe, signed_op)(signed)
tests = complete(a, 4, 16)
compile(f'test_{signed_op}_complete', 'test_pe_comp_unq1', a.opcode, tests)
run_verilator_test('test_pe_comp_unq1', f'sim_test_{signed_op}_complete', 'test_pe_comp_unq1')
def test_signed_op(signed_op, signed, strategy):
a = getattr(pe, signed_op)(signed)
tests = get_tests(a, strategy, signed)
compile('harness', 'test_pe_comp_unq1', a.instruction, tests)
run_verilator_test('test_pe_comp_unq1', 'harness', 'test_pe_comp_unq1')
run_ncsim_test(signed_op, a.instruction, tests, strategy)
def test_and():
a = and_()
tests = complete(a, 4, 16)
compile('test_pe_comp_unq1', a.opcode, tests)
assert not subprocess.call(
"verilator -I../rtl -Wno-fatal --cc test_pe_comp_unq1 --exe sim_test_pe_comp_unq1.cpp",
shell=True,
cwd="build")
assert not subprocess.call(
"make -C obj_dir -j -f Vtest_pe_comp_unq1.mk Vtest_pe_comp_unq1",
shell=True,
cwd="build")
assert not subprocess.call(
"./obj_dir/Vtest_pe_comp_unq1", shell=True, cwd="build")
def test_op(op):
a = getattr(pe, op)()
tests = complete(a, 4, 16)
compile(f'test_{op}_complete', 'test_pe_comp_unq1', a.opcode, tests)
run_verilator_test('test_pe_comp_unq1', f'sim_test_{op}_complete', 'test_pe_comp_unq1')
if os.environ.get("TRAVIS", True):
# Skip on Travis because cadence tools not available
# FIXME: Should check for cadence tools available instead
return
ncsim.compile(f'test_{op}_complete', a.opcode, tests)
RTL_FOLDER = "../../hardware/generator_z/top/genesis_verif"
result = delegator.run(f"""
irun -top test_pe_comp_unq1_tb -timescale 1ns/1ps -l irun.log -access +rwc -notimingchecks -input ../../hardware/generator_z/impl/verif/cmd.tcl build/ncsim_test_{op}_complete_tb.v /nobackup/nikhil3/arm_mems/arm/tsmc/cln40g/sram_sp_hsc_rvt_hvt_rvt/r10p2/sram_512w_16b/sram_512w_16b.v {RTL_FOLDER}/cb_unq1.v {RTL_FOLDER}/cb_unq2.v {RTL_FOLDER}/cb_unq3.v {RTL_FOLDER}/global_signal_tile_unq1.v {RTL_FOLDER}/io1bit_unq1.v {RTL_FOLDER}/io1bit_unq2.v {RTL_FOLDER}/io1bit_unq3.v {RTL_FOLDER}/io1bit_unq4.v {RTL_FOLDER}/jtag_unq1.sv {RTL_FOLDER}/memory_core_unq1.v {RTL_FOLDER}/memory_tile_unq1.v {RTL_FOLDER}/mem_unq1.v {RTL_FOLDER}/pe_tile_new_unq1.v {RTL_FOLDER}/sb_unq1.v {RTL_FOLDER}/sb_unq2.v {RTL_FOLDER}/sb_unq3.v {RTL_FOLDER}/test_cmpr.sv {RTL_FOLDER}/test_full_add.sv {RTL_FOLDER}/test_lut.sv {RTL_FOLDER}/test_mult_add.sv {RTL_FOLDER}/test_opt_reg.sv {RTL_FOLDER}/test_pe_comp_unq1.sv {RTL_FOLDER}/test_pe_unq1.sv {RTL_FOLDER}/test_shifter_unq1.sv {RTL_FOLDER}/top.v
""")
assert not result.return_code, result.out + "\n" + result.err
assert "Failed!" not in result.out, result.out + "\n" + result.err
from pe import and_
from testvectors import complete
from verilator import compile
a = and_()
tests = complete(a, 4, 16)
compile('test_pe_comp_unq1', a.opcode, tests)