示例#1
0
文件: fsm.py 项目: yinxx/veriloggen
    def make_case(self):
        indexes = set(self.body.keys())
        indexes.update(set(self.jump.keys()))

        for index in indexes:
            self._add_mark(index)

        ret = []
        ret.extend(self.seq.make_code())
        ret.extend(self._get_delayed_substs())

        for delay, dct in sorted(self.delayed_body.items(),
                                 key=lambda x: x[0],
                                 reverse=True):
            body = tuple([
                self._get_delayed_when_statement(index, delay)
                for index in sorted(dct.keys(), key=lambda x: x)
            ])
            case = vtypes.Case(self._get_delayed_state(delay))(*body)
            ret.append(case)

        body = tuple([
            self._get_when_statement(index)
            for index in sorted(indexes, key=lambda x: x)
        ])
        case = vtypes.Case(self.state)(*body)

        if len(case.statement) > 0:
            ret.append(case)
示例#2
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文件: rom.py 项目: yinxx/veriloggen
def mkROMDefinition(name,
                    values,
                    size,
                    datawidth,
                    sync=False,
                    with_enable=False):
    if not sync and with_enable:
        raise ValueError('Async ROM cannot have enable signals')

    m = Module(name)

    clk = m.Input('CLK') if sync else None
    addr = m.Input('addr', size)
    if with_enable:
        enable = m.Input('enable')
    val = m.OutputReg('val', datawidth)

    if clk is not None:
        alw = m.Always(vtypes.Posedge(clk))
    else:
        alw = m.Always()

    patterns = [
        vtypes.When(i)(val(v, blk=not sync)) for i, v in enumerate(values)
    ]

    body = vtypes.Case(addr)(*patterns)

    if with_enable:
        body = vtypes.If(enable)(body)

    alw(body)

    return m
示例#3
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 def visit_Case(self, node):
     comp = self.visit(node.comp)
     statement = self.visit(node.statement)
     ret = vtypes.Case(comp)
     ret.statement = statement
     ret.last = node.last
     return ret
示例#4
0
文件: rom.py 项目: jszheng/codegen
def mkROMDefinition(name, values, size, datawidth, sync=False):
    m = Module(name)

    clk = m.Input('CLK') if sync else None
    addr = m.Input('addr', size)
    val = m.OutputReg('val', datawidth)

    if clk is not None:
        alw = m.Always(vtypes.Posedge(clk))
    else:
        alw = m.Always()

    patterns = [
        vtypes.When(i)(val(v, blk=not sync)) for i, v in enumerate(values)
    ]

    alw(vtypes.Case(addr)(*patterns))

    return m
示例#5
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        statement = to_tuple(self.visit(node.statement))
        _for = vtypes.For(pre, condition, post)
        _for = _for(*statement)
        return _for

    def visit_WhileStatement(self, node):
        condition = self.visit(node.cond)
        statement = to_tuple(self.visit(node.statement))
        _while = vtypes.While(condition)
        _while = _while(*statement)
        return _while

    def visit_CaseStatement(self, node):
        comp = self.visit(node.comp)
        statement = tuple([self.visit(case) for case in node.caselist])
        case = vtypes.Case(comp)
        case = case(*statement)
        return case

    def visit_CasexStatement(self, node):
        comp = self.visit(node.comp)
        statement = tuple([self.visit(case) for case in node.caselist])
        case = vtypes.Casex(comp)
        case = case(*statement)
        return case

    def visit_Case(self, node):
        condition = tuple([self.visit(c)
                           for c in node.cond]) if node.cond else [None]
        statement = to_tuple(self.visit(node.statement))
        when = vtypes.When(*condition)