def mkMain(): m = Module('main') clk = m.Input('CLK') rst = m.Input('RST') df1 = dataflow.DataflowManager(m, clk, rst) df2 = dataflow.DataflowManager(m, clk, rst) df3 = dataflow.DataflowManager(m, clk, rst) # Even if the same manager is used, they provide same result #df2 = df1 #df3 = df2 x = df1.Counter() y = df2.Counter() z = df3.Counter() # oldest dataflow manager is used as the base manager a = x + y + z b = y + z + x c = z + x + y a.output('adata', 'avalid') b.output('bdata', 'bvalid') c.output('cdata', 'cvalid') return m
def mkMain(n=128, datawidth=32, numports=2): m = Module('main') clk = m.Input('CLK') rst = m.Input('RST') df = dataflow.DataflowManager(m, clk, rst) a = df.Constant(2) b = df.Counter(1, initval=0, maxval=8) b = b.prev(1) c = df.Iadd(a, reset=(b == 0)) b.output('bdata', 'bvalid', 'bready') c.output('cdata', 'cvalid', 'cready') ready = 1 bdata, bvalid = b.read(ready) cdata, cvalid = c.read(ready) seq = Seq(m, 'seq', clk, rst) seq.If(bvalid)(Systask('display', 'b=%d', bdata)) seq.If(cvalid)(Systask('display', 'c=%d', cdata)) return m
def mkMain(): m = Module('main') clk = m.Input('CLK') rst = m.Input('RST') myaxi = axi.AxiMaster(m, 'myaxi', clk, rst) myaxi.disable_write() df = dataflow.DataflowManager(m, clk, rst) req_fsm = FSM(m, 'req_fsm', clk, rst) # read request araddr = 1024 arlen = 64 ack, counter = myaxi.read_request(araddr, arlen, cond=req_fsm) req_fsm.If(ack).goto_next() # read dataflow (AXI -> Dataflow) data, last, done = myaxi.read_dataflow() sum = df.ReduceAdd(data, reset=last.prev(1)) # verify sum_data, sum_valid = sum.read() last_data, last_valid = last.read() expected_sum = ((araddr + araddr + arlen - 1) * arlen) // 2 data_seq = Seq(m, 'data_seq', clk, rst) data_seq.If(Ands(sum_valid, last_valid, last_data == 1)).Delay(1)( Systask('display', 'sum=%d expected_sum=%d', sum_data, expected_sum) ) return m
def mkMain(n=128, datawidth=32, numports=2): m = Module('main') clk = m.Input('CLK') rst = m.Input('RST') addrwidth = int(math.log(n, 2)) * 2 myram = ram.SyncRAMManager(m, 'myram', clk, rst, datawidth, addrwidth) df = dataflow.DataflowManager(m, clk, rst) # df.enable_draw_graph() fsm = FSM(m, 'fsm', clk, rst) length = 8 a = df.Counter() b = df.Counter(maxval=length) c = b == 0 wport = 0 waddr = 0 wlen = 32 done = myram.write_dataflow(wport, waddr, a, wlen, cond=fsm, when=c) fsm.goto_next() fsm.If(done).goto_next() seq = Seq(m, 'seq', clk, rst) seq.If(myram[0].wenable)(Systask('display', '[%d] <- %d', myram[0].addr, myram[0].wdata)) return m
def mkMain(n=128, datawidth=32, numports=2): m = Module('main') clk = m.Input('CLK') rst = m.Input('RST') df = dataflow.DataflowManager(m, clk, rst) a = df.Counter(step=1, size=8, initval=0) b = df.Counter(step=1, initval=0, enable=(a == 0)) c = df.Counter(step=1, initval=0, enable=df.Or(a == 0, a == 4)) a.output('adata', 'avalid', 'aready') b.output('bdata', 'bvalid', 'bready') c.output('cdata', 'cvalid', 'cready') ready = 1 adata, avalid = a.read(ready) bdata, bvalid = b.read(ready) cdata, cvalid = c.read(ready) seq = Seq(m, 'seq', clk, rst) seq.If(bvalid)( Systask('display', 'b=%d', bdata) ) seq.If(cvalid)( Systask('display', 'c=%d', cdata) ) return m
def mkMain(): m = Module('main') clk = m.Input('CLK') rst = m.Input('RST') myaxi = axi.AxiMaster(m, 'myaxi', clk, rst) myram = RAM(m, 'myram', clk, rst, numports=1) df = dataflow.DataflowManager(m, clk, rst) fsm = FSM(m, 'fsm', clk, rst) # AXI read request araddr = 1024 arlen = 64 ack, counter = myaxi.read_request_counter(araddr, arlen, cond=fsm) fsm.If(ack).goto_next() # AXI read dataflow (AXI -> Dataflow) axi_data, axi_last, done = myaxi.read_dataflow() sum = df.ReduceAdd(axi_data, reset=axi_last.prev(1)) # RAM write dataflow (Dataflow -> RAM) wport = 0 waddr = 0 wlen = arlen done = myram.write_dataflow(wport, waddr, sum, wlen, cond=fsm) fsm.goto_next() fsm.If(done).goto_next() # AXI write request awaddr = 1024 awlen = 64 ack, counter = myaxi.write_request_counter(awaddr, awlen, cond=fsm) fsm.If(ack).goto_next() # RAM read dataflow (RAM -> Dataflow) rport = 0 raddr = 0 rlen = arlen rdata, rlast, done = myram.read_dataflow(rport, raddr, rlen, cond=fsm) fsm.goto_next() # AXI write dataflow done = myaxi.write_dataflow(rdata, counter) fsm.If(done).goto_next() # verify sum = m.Reg('sum', 32, initval=0) expected_sum = 0 for i in range(arlen): expected_sum += (araddr + araddr + i) * (i + 1) // 2 seq = Seq(m, 'seq', clk, rst) seq.If(Ands(myaxi.wdata.wvalid, myaxi.wdata.wready))(sum.add(myaxi.wdata.wdata)) seq.Then().If(myaxi.wdata.wlast).Delay(1)(Systask( 'display', "sum=%d expected_sum=%d", sum, expected_sum)) return m
def mkMain(n=128, datawidth=32, numports=2): m = Module('main') clk = m.Input('CLK') rst = m.Input('RST') addrwidth = int(math.log(n, 2)) * 2 myram = ram.SyncRAMManager(m, 'myram', clk, rst, datawidth, addrwidth, 2) myram.disable_write(1) df = dataflow.DataflowManager(m, clk, rst) fsm = FSM(m, 'fsm', clk, rst) # dataflow c = df.Counter() value = c - 1 # write dataflow (Dataflow -> RAM) wport = 0 waddr = 0 wlen = 64 done = myram.write_dataflow(wport, waddr, value, wlen, cond=fsm) fsm.goto_next() fsm.If(done).goto_next() fsm.goto_next() # read dataflow (RAM -> Dataflow) rport = 1 raddr = 0 rlen = 32 reuse_size = 4 rdata0, rdata1, rlast, done = myram.read_dataflow_reuse( rport, raddr, rlen, num_outputs=2, reuse_size=reuse_size, cond=fsm) fsm.goto_next() fsm.If(done).goto_next() # verify rdata0_data, rdata0_valid = rdata0.read() rdata1_data, rdata1_valid = rdata1.read() rlast_data, rlast_valid = rlast.read() sum0 = m.Reg('sum0', 32, initval=0) sum1 = m.Reg('sum1', 32, initval=0) expected_sum = ((raddr + raddr + rlen - 1) * rlen // 2) * reuse_size seq = Seq(m, 'seq', clk, rst) seq.If(rdata0_valid)(sum0.add(rdata0_data), Systask('display', 'rdata0_data=%d', rdata0_data)) seq.If(rdata1_valid)(sum1.add(rdata1_data), Systask('display', 'rdata1_data=%d', rdata1_data)) seq.Then().If(rlast_data == 1).Delay(1)(Systask('display', 'sum=%d expected_sum=%d', sum0 + sum1, expected_sum)) return m
def mkMain(): m = Module('main') clk = m.Input('CLK') rst = m.Input('RST') myaxi = axi.AxiMaster(m, 'myaxi', clk, rst) myaxi.disable_write() myram = RAM(m, 'myram', clk, rst, numports=1) df = dataflow.DataflowManager(m, clk, rst) fsm = FSM(m, 'fsm', clk, rst) # AXI read request araddr = 1024 arlen = 64 ack, axi_counter = myaxi.read_request_counter(araddr, arlen, cond=fsm) fsm.If(ack).goto_next() # AXI read dataflow (AXI -> Dataflow) axi_data, axi_last, done = myaxi.read_dataflow() sum = df.ReduceAdd(axi_data, reset=axi_last.prev(1)) # RAM write dataflow (Dataflow -> RAM) wport = 0 waddr = 0 wlen = arlen done = myram.write_dataflow(wport, waddr, sum, wlen, cond=fsm) fsm.goto_next() fsm.If(done).goto_next() # verify # read dataflow (RAM -> Dataflow) rport = 0 raddr = 0 rlen = arlen rdata, rlast, done = myram.read_dataflow(rport, raddr, rlen, cond=fsm) fsm.goto_next() fsm.If(done).goto_next() rdata_data, rdata_valid = rdata.read() rlast_data, rlast_valid = rlast.read() sum = m.Reg('sum', 32, initval=0) expected_sum = 0 for i in range(arlen): expected_sum += (araddr + araddr + i) * (i + 1) // 2 seq = Seq(m, 'seq', clk, rst) seq.If(rdata_valid)(sum.add(rdata_data)) seq.Then().If(rlast_data == 1).Delay(1)( Systask('display', 'sum=%d expected_sum=%d', sum, expected_sum), If(NotEql(sum, expected_sum))(Display('# verify: FAILED')).Else( Display('# verify: PASSED'))) return m
def mkMain(n=128, datawidth=32, numports=2): m = Module('main') clk = m.Input('CLK') rst = m.Input('RST') df = dataflow.DataflowManager(m, clk, rst) # df.enable_draw_graph() # input with register xdata = m.Reg('xdata', 32, initval=0) xvalid = m.Reg('xvalid', initval=0) xready = m.Wire('xready') x = df.Variable(xdata, xvalid, xready, signed=False) # input with name y = df.Variable('ydata', 'yvalid', 'yready', signed=False) # output a = x + y + 1 b = a + x + y a.output('adata', 'avalid', 'aready') b.output('bdata', 'bvalid', 'bready') # write xfsm = FSM(m, 'xfsm', clk, rst) xcount = m.TmpReg(32, initval=0) xack = x.write(xcount, cond=xfsm) xfsm.If(xack)(xcount.inc()) xfsm.Then().If(xcount == 15).goto_next() # write yfsm = FSM(m, 'yfsm', clk, rst) ycount = m.TmpReg(32, initval=0) yack = y.write(ycount, cond=yfsm) yfsm.If(yack)(ycount(ycount + 1)) yfsm.Then().If(ycount == 15).goto_next() # read aseq = Seq(m, 'aseq', clk, rst) adata, avalid = a.read(cond=aseq) aseq.If(avalid)(Systask('display', "adata=%d", adata)) # read bseq = Seq(m, 'bseq', clk, rst) bdata, bvalid = b.read(cond=bseq) bseq.If(bvalid)(Systask('display', "bdata=%d", bdata)) return m
def mkMain(n=128, datawidth=32, numports=2): m = Module('main') clk = m.Input('CLK') rst = m.Input('RST') addrwidth = int(math.log(n, 2)) * 2 mybram = bram.Bram(m, 'mybram', clk, rst, datawidth, addrwidth, 2) mybram.disable_write(1) df = dataflow.DataflowManager(m, clk, rst) fsm = FSM(m, 'fsm', clk, rst) # dataflow c = df.Counter() value = c - 1 # write dataflow (Dataflow -> BRAM) wport = 0 waddr = 0 wlen = 64 done = mybram.write_dataflow(wport, waddr, value, wlen, cond=fsm) fsm.goto_next() fsm.If(done).goto_next() fsm.goto_next() # read dataflow (BRAM -> Dataflow) rport = 1 raddr = 0 rlen = 32 rdata, rlast, done = mybram.read_dataflow(rport, raddr, rlen, cond=fsm) fsm.goto_next() fsm.If(done).goto_next() # verify rdata_data, rdata_valid = rdata.read() rlast_data, rlast_valid = rlast.read() sum = m.Reg('sum', 32, initval=0) expected_sum = (raddr + raddr + rlen - 1) * rlen // 2 seq = Seq(m, 'seq', clk, rst) seq.If(rdata_valid)(sum.add(rdata_data)) seq.Then().If(rlast_data == 1).Delay(1)(Systask('display', 'sum=%d expected_sum=%d', sum, expected_sum)) return m
def mkMain(): m = Module('main') clk = m.Input('CLK') rst = m.Input('RST') df = dataflow.DataflowManager(m, clk, rst) x = df.Counter() y = df.Counter() z = x * 2 - y z.output('zdata', 'zvalid') return m
def mkMain(n=128, datawidth=32, numports=2): m = Module('main') clk = m.Input('CLK') rst = m.Input('RST') addrwidth = int(math.log(n, 2)) * 2 myram = RAM(m, 'myram', clk, rst, datawidth, addrwidth) df = dataflow.DataflowManager(m, clk, rst) # df.enable_draw_graph() fsm = FSM(m, 'fsm', clk, rst) length = 8 a = df.Counter() b = df.Counter(size=length) c = b == 0 wport = 0 waddr = 0 wlen = 32 done = myram.write_dataflow(wport, waddr, a, wlen, cond=fsm, when=c) fsm.goto_next() fsm.If(done).goto_next() # verify sum = m.Reg('sum', 32, initval=0) expected_sum = (waddr + waddr + (wlen - 1) * length) * wlen // 2 seq = Seq(m, 'seq', clk, rst) seq.If(myram[0].wenable)( sum.add(myram[0].wdata) ) seq.Then().If(myram[0].addr == wlen - 1).Delay(2)( Systask('display', 'sum=%d expected_sum=%d', sum, expected_sum), If(NotEql(sum, expected_sum))(Display('# verify: FAILED')).Else(Display('# verify: PASSED')) ) return m
def mkMain(): m = Module('main') clk = m.Input('CLK') rst = m.Input('RST') myaxi = axi.AxiMaster(m, 'myaxi', clk, rst) myaxi.disable_read() df = dataflow.DataflowManager(m, clk, rst) fsm = FSM(m, 'fsm', clk, rst) # write request awaddr = 1024 awlen = 64 ack, counter = myaxi.write_request(awaddr, awlen, cond=fsm) fsm.If(ack).goto_next() # dataflow c = df.Counter() value = c - 1 t = df.Counter(maxval=8).prev(1) when = t == 0 # write dataflow (Dataflow -> AXI) done = myaxi.write_dataflow(value, counter, when=when) fsm.If(done).goto_next() # verify sum = m.Reg('sum', 32, initval=0) expected_sum = 8 * (awlen - 1) * awlen // 2 seq = Seq(m, 'seq', clk, rst) seq.If(Ands(myaxi.wdata.wvalid, myaxi.wdata.wready))( sum.add(myaxi.wdata.wdata), ) seq.Then().If(myaxi.wdata.wlast).Delay(1)( Systask('display', "sum=%d expected_sum=%d", sum, expected_sum) ) return m
def mkMain(n=128, datawidth=32, numports=2): m = Module('main') clk = m.Input('CLK') rst = m.Input('RST') addrwidth = int(math.log(n, 2)) * 2 myram = ram.SyncRAMManager(m, 'myram', clk, rst, datawidth, addrwidth, 2) myram.disable_write(1) df = dataflow.DataflowManager(m, clk, rst) fsm = FSM(m, 'fsm', clk, rst) fsm.goto_next() # dataflow c = df.Counter(maxval=64) value = c - 1 # write dataflow (Dataflow -> RAM) wport = 0 waddr = 0 wlen = 64 done = myram.write_dataflow(wport, waddr, value, wlen, cond=fsm) fsm.goto_next() fsm.If(done).goto_next() # verify sum = m.Reg('sum', 32, initval=0) expected_sum = (waddr + waddr + wlen - 1) * wlen // 2 - wlen seq = Seq(m, 'seq', clk, rst) seq.If(myram[0].wenable)( sum.add(myram[0].wdata) ) seq.Then().If(myram[0].addr == wlen - 1).Delay(2)( Systask('display', 'sum=%d expected_sum=%d', sum, expected_sum) ) return m
def mkMain(): m = Module('main') clk = m.Input('CLK') rst = m.Input('RST') # AXI ports slave = axi.AxiSlave(m, 'slave', clk, rst) master = axi.AxiMaster(m, 'master', clk, rst) # a, b: source, c: result ram_a = ram.SyncRAMManager(m, 'ram_a', clk, rst, numports=1) ram_b = ram.SyncRAMManager(m, 'ram_b', clk, rst, numports=1) ram_c = ram.SyncRAMManager(m, 'ram_c', clk, rst, numports=1) read_fsm = FSM(m, 'read_fsm', clk, rst) write_fsm = FSM(m, 'write_fsm', clk, rst) df = dataflow.DataflowManager(m, clk, rst) # df.enable_draw_graph() read_fsm.goto_next() row_count = m.Reg('row_count', 32, initval=0) read_fsm(row_count(0)) # wait for slave request slave_addr, slave_counter, slave_valid = slave.pull_write_request( cond=read_fsm) read_fsm.If(slave_valid).goto_next() data, mask, valid, last = slave.pull_write_data(slave_counter, cond=read_fsm) read_fsm.If(valid).goto_next() write_fsm.If(read_fsm).goto_next() # computation master_addr = 1024 * 2 ram_addr = 0 length = 16 dma_done = master.dma_read(ram_b, master_addr, ram_addr, length, cond=read_fsm) read_fsm.If(dma_done).goto_next() comp_start = read_fsm.current master_addr = 1024 ram_addr = 0 length = 16 dma_done = master.dma_read(ram_a, master_addr, ram_addr, length, cond=read_fsm) read_fsm.If(dma_done).goto_next() adata, alast, adone = ram_a.read_dataflow(0, ram_addr, length, cond=read_fsm) bdata, blast, bdone = ram_b.read_dataflow(0, ram_addr, length, cond=read_fsm) read_fsm.goto_next() mul = adata * bdata mul_count = df.Counter(maxval=length) wcond = mul_count == 0 cdata = df.Iadd(mul, reset=wcond.prev(1)) read_fsm(row_count.inc()) read_fsm.If(row_count < length - 1).goto(comp_start) read_fsm.If(row_count == length - 1).goto_next() done = ram_c.write_dataflow(0, 0, cdata, length, cond=write_fsm, when=wcond) write_fsm.goto_next() write_fsm.If(done).goto_next() master_addr = 1024 * 3 dma_done = master.dma_write(ram_c, master_addr, ram_addr, length, cond=write_fsm) write_fsm.If(dma_done).goto_next() read_fsm.If(write_fsm).goto_init() write_fsm.goto_init() seq = Seq(m, 'seq', clk, rst) seq.If(ram_c[0].wenable)(Systask('display', '[%d]<-%d', ram_c[0].addr, ram_c[0].wdata)) return m