Python resolve示例

示例#1

文件： resolver_for_loop.py 项目： yongfu-li/veriloggen

def mkLed():
    led = mkOrigLed()
    # resolve() is idempotent
    led = resolver.resolve(led)
    led = resolver.resolve(led)
    led = resolver.resolve(led)
    return resolver.resolve(led)

示例#2

文件： resolver_for_loop.py 项目： PyHDI/veriloggen

def mkLed():
    led = mkOrigLed()
    # resolve() is idempotent
    led = resolver.resolve(led)
    led = resolver.resolve(led)
    led = resolver.resolve(led)
    return resolver.resolve(led)

示例#3

文件： resolver_single_module.py 项目： PyHDI/veriloggen

def mkLed():
    led = mkOrigLed()
    return resolver.resolve(led)

示例#4

文件： componentgen.py 项目： PyHDI/veriloggen

    def generate(self, m, ip_name, bus_interfaces,
                 clk_ports, rst_ports,
                 ext_ports, ext_params,
                 vendor='user.org', library='user', version='1.0',
                 description='user description',
                 supported_families=('zynq', 'zynquplus')):

        self.m = m
        self.ip_name = ip_name
        self.bus_interfaces = bus_interfaces
        self.clk_ports = clk_ports
        self.rst_ports = rst_ports
        self.ext_ports = ext_ports
        self.ext_params = ext_params

        self.resolved_m = resolver.resolve(copy.deepcopy(m))

        self.vendor = vendor
        self.library = library
        self.version = version

        if not supported_families:
            raise ValueError(
                'supported_families must be a list or tuple with valid names.')

        self.supported_families = supported_families

        impl = xml.dom.minidom.getDOMImplementation()
        self.doc = impl.createDocument('spirit', 'spirit:component', None)
        self.top = self.doc.documentElement

        self.setAttribute(self.top, 'xmlns:xilinx', "http://www.xilinx.com")
        self.setAttribute(self.top, 'xmlns:spirit',
                          "http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009")
        self.setAttribute(self.top, 'xmlns:xsi',
                          "http://www.w3.org/2001/XMLSchema-instance")

        self.dependency_consumer = set()

        self.top.appendChild(self.mkVendor())
        self.top.appendChild(self.mkLibrary())
        self.top.appendChild(self.mkName(self.ip_name))
        self.top.appendChild(self.mkVersion())

        self.top.appendChild(self.mkBusInterfaces())

        r = self.mkAddressSpaces()
        if r:
            self.top.appendChild(r)

        r = self.mkMemoryMaps()
        if r:
            self.top.appendChild(r)

        self.top.appendChild(self.mkModel())
        self.top.appendChild(self.mkFileSets())
        self.top.appendChild(self.mkDescription(description))
        self.top.appendChild(self.mkParameters())
        self.top.appendChild(self.mkVendorExtensions())

        return self.doc.toprettyxml(indent='  ')

示例#5

文件： resolver_bram.py 项目： yongfu-li/veriloggen

def mkOrig():
    m = mkMain()
    m = resolver.resolve(m)
    return m

示例#6

文件： resolver_single_module.py 项目： yongfu-li/veriloggen

def mkLed():
    led = mkOrigLed()
    return resolver.resolve(led)

示例#7

文件： componentgen.py 项目： xiaolongn100/veriloggen

    def generate(self,
                 m,
                 ip_name,
                 bus_interfaces,
                 clk_ports,
                 rst_ports,
                 ext_ports,
                 ext_params,
                 vendor='user.org',
                 library='user',
                 version='1.0',
                 description='user description',
                 supported_families=('zynq', 'zynquplus')):

        self.m = m
        self.ip_name = ip_name
        self.bus_interfaces = bus_interfaces
        self.clk_ports = clk_ports
        self.rst_ports = rst_ports
        self.ext_ports = ext_ports
        self.ext_params = ext_params

        self.resolved_m = resolver.resolve(copy.deepcopy(m))

        self.vendor = vendor
        self.library = library
        self.version = version

        if not supported_families:
            raise ValueError(
                'supported_families must be a list or tuple with valid names.')

        self.supported_families = supported_families

        impl = xml.dom.minidom.getDOMImplementation()
        self.doc = impl.createDocument('spirit', 'spirit:component', None)
        self.top = self.doc.documentElement

        self.setAttribute(self.top, 'xmlns:xilinx', "http://www.xilinx.com")
        self.setAttribute(
            self.top, 'xmlns:spirit',
            "http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009")
        self.setAttribute(self.top, 'xmlns:xsi',
                          "http://www.w3.org/2001/XMLSchema-instance")

        self.dependency_consumer = set()

        self.top.appendChild(self.mkVendor())
        self.top.appendChild(self.mkLibrary())
        self.top.appendChild(self.mkName(self.ip_name))
        self.top.appendChild(self.mkVersion())

        self.top.appendChild(self.mkBusInterfaces())

        r = self.mkAddressSpaces()
        if r:
            self.top.appendChild(r)

        r = self.mkMemoryMaps()
        if r:
            self.top.appendChild(r)

        self.top.appendChild(self.mkModel())
        self.top.appendChild(self.mkFileSets())
        self.top.appendChild(self.mkDescription(description))
        self.top.appendChild(self.mkParameters())
        self.top.appendChild(self.mkVendorExtensions())

        return self.doc.toprettyxml(indent='  ')

示例#8

文件： convert.py 项目： PyHDI/hardcheck

def convert(m, ctrl='cpr_ctrl_', signal='cpr_'):
    converter = ModuleConverter(ctrl, signal)
    m = resolver.resolve(m)
    m = converter.convert(m)
    return m

示例#9

文件： resolver_bram.py 项目： PyHDI/veriloggen

def mkOrig():
    m = mkMain()
    m = resolver.resolve(m)
    return m