def mkMain(n=128, datawidth=32, numports=2):
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
addrwidth = int(math.log(n, 2)) * 2
myram = RAM(m, 'myram', clk, rst, datawidth, addrwidth, 1)
# example how to access RAM
count = m.Reg('count', 32, initval=0)
sum = m.Reg('sum', 32, initval=0)
addr = m.Reg('addr', 32, initval=0)
fsm = FSM(m, 'fsm', clk, rst)
fsm(addr(0), count(0), sum(0))
fsm.goto_next()
step = 16
myram.write_rtl(addr, count, port=0, cond=fsm)
fsm(addr.inc(), count.inc())
fsm.If(count == step - 1)(addr(0), count(0))
fsm.Then().goto_next()
read_data, read_valid = myram.read_rtl(addr, port=0, cond=fsm)
fsm(addr.inc(), count.inc())
fsm.If(read_valid)(sum(sum + read_data))
fsm.Then().Delay(1)(Systask('display', "sum=%d", sum))
fsm.If(count == step - 1)(addr(0), count(0)).Then().goto_next()
fsm.If(read_valid)(sum(sum + read_data))
fsm.Then().Delay(1)(Systask('display', "sum=%d", sum))
fsm.goto_next()
fsm(Systask('display', "expected_sum=%d", (step - 1) * step // 2))
fsm.goto_next()
fsm.make_always()
return m
def mkMain(n=128, datawidth=32, numports=2):
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
addrwidth = int(math.log(n, 2)) * 2
myram = RAM(m, 'myram', clk, rst, datawidth, addrwidth, 1)
# example how to access RAM
count = m.Reg('count', 32, initval=0)
sum = m.Reg('sum', 32, initval=0)
addr = m.Reg('addr', 32, initval=0)
fsm = FSM(m, 'fsm', clk, rst)
fsm(
addr(0),
count(0),
sum(0)
)
fsm.goto_next()
step = 16
myram.write_rtl(addr, count, port=0, cond=fsm)
fsm(
addr.inc(),
count.inc()
)
fsm.If(count == step - 1)(
addr(0),
count(0)
)
fsm.Then().goto_next()
read_data, read_valid = myram.read_rtl(addr, port=0, cond=fsm)
fsm(
addr.inc(),
count.inc()
)
fsm.If(read_valid)(
sum(sum + read_data)
)
fsm.Then().Delay(1)(
Systask('display', "sum=%d", sum)
)
fsm.If(count == step - 1)(
addr(0),
count(0)
).Then().goto_next()
fsm.If(read_valid)(
sum(sum + read_data)
)
fsm.Then().Delay(1)(
Systask('display', "sum=%d", sum)
)
fsm.make_always()
return m
def mkStencil(n=16, size=3, datawidth=32, point=16, coe_test=False):
m = Module('stencil')
addrwidth = int(math.log(n, 2))
clk = m.Input('CLK')
rst = m.Input('RST')
start = m.Input('start')
busy = m.OutputReg('busy', initval=0)
done = m.TmpReg(initval=0)
# external RAM I/F
ext_src_rams = [
ram.RAMSlaveInterface(m,
'ext_src_ram%d' % i,
datawidth=datawidth,
addrwidth=addrwidth) for i in range(size)
]
ext_dst_ram = ram.RAMSlaveInterface(m,
'ext_dst_ram',
datawidth=datawidth,
addrwidth=addrwidth)
# RAM
addrwidth = int(math.log(n, 2)) * 2
src_rams = [
RAM(m,
'src_ram%d' % i,
clk,
rst,
datawidth=datawidth,
addrwidth=addrwidth,
numports=2) for i in range(size)
]
dst_ram = RAM(m,
'dst_ram',
clk,
rst,
datawidth=datawidth,
addrwidth=addrwidth,
numports=2)
# connect RAM I/Fs
for src_ram, ext_src_ram in zip(src_rams, ext_src_rams):
src_ram[1].connect(ext_src_ram)
dst_ram[1].connect(ext_dst_ram)
# read FSM
read_fsm = FSM(m, 'read_fsm', clk, rst)
read_count = m.Reg('read_count', 32, initval=0)
read_addr = m.Reg('read_addr', 32, initval=0)
read_fsm(read_addr(0), read_count(0), busy(0))
read_fsm.If(start)(busy(1))
read_fsm.Then().goto_next()
read_fsm(read_addr.inc(), read_count.inc())
idata = []
ivalid = []
for i, src_ram in enumerate(src_rams):
src_ram.disable_write(0)
rdata, rvalid = src_ram.read_rtl(read_addr, port=0, cond=read_fsm)
idata.append(rdata)
ivalid.append(rvalid)
read_fsm.If(read_count == n - 1)(read_addr(0), read_count(0))
read_fsm.Then().goto_next()
read_fsm.If(done)(busy(0))
read_fsm.Then().goto_init()
read_fsm.make_always()
# instance
odata = m.Wire('odata', datawidth)
ovalid = m.Wire('ovalid')
ports = []
ports.append(('CLK', clk))
ports.append(('RST', rst))
for i, (d, v) in enumerate(zip(idata, ivalid)):
ports.append(('idata%d' % i, d))
ports.append(('ivalid%d' % i, v))
ports.append(('odata', odata))
ports.append(('ovalid', ovalid))
coe = None
if coe_test:
coe = [[dataflow.Constant(1, point=point) for i in range(size)]
for j in range(size)]
point = 0
st = mkStencilPipeline2D(size=3, width=datawidth, point=point, coe=coe)
m.Instance(st, 'inst_stencil', ports=ports)
skip_offset = int(math.floor(size / 2))
# write FSM
write_fsm = FSM(m, 'write_fsm', clk, rst)
write_count = m.Reg('write_count', 32, initval=0)
write_addr = m.Reg('write_addr', 32, initval=skip_offset)
write_fsm(done(0))
write_fsm.If(Ands(ovalid, write_count > skip_offset))(write_addr.inc())
dst_ram.write_rtl(write_addr, odata, port=0, cond=write_fsm.then)
write_fsm.If(ovalid)(write_count.inc(), )
write_fsm.If(write_count == n)(write_count(0), write_addr(skip_offset),
done(1))
write_fsm.Then().goto_init()
write_fsm.make_always()
return m
def mkStencil(n=16, size=3, datawidth=32, point=16, coe_test=False):
m = Module('stencil')
addrwidth = int(math.log(n, 2))
clk = m.Input('CLK')
rst = m.Input('RST')
start = m.Input('start')
busy = m.OutputReg('busy', initval=0)
done = m.TmpReg(initval=0)
# external RAM I/F
ext_src_rams = [ram.RAMSlaveInterface(m, 'ext_src_ram%d' % i,
datawidth=datawidth, addrwidth=addrwidth)
for i in range(size)]
ext_dst_ram = ram.RAMSlaveInterface(m, 'ext_dst_ram',
datawidth=datawidth, addrwidth=addrwidth)
# RAM
addrwidth = int(math.log(n, 2)) * 2
src_rams = [RAM(m, 'src_ram%d' % i, clk, rst,
datawidth=datawidth, addrwidth=addrwidth, numports=2)
for i in range(size)]
dst_ram = RAM(m, 'dst_ram', clk, rst,
datawidth=datawidth, addrwidth=addrwidth, numports=2)
# connect RAM I/Fs
for src_ram, ext_src_ram in zip(src_rams, ext_src_rams):
src_ram[1].connect(ext_src_ram)
dst_ram[1].connect(ext_dst_ram)
# read FSM
read_fsm = FSM(m, 'read_fsm', clk, rst)
read_count = m.Reg('read_count', 32, initval=0)
read_addr = m.Reg('read_addr', 32, initval=0)
read_fsm(
read_addr(0),
read_count(0),
busy(0)
)
read_fsm.If(start)(
busy(1)
)
read_fsm.Then().goto_next()
read_fsm(
read_addr.inc(),
read_count.inc()
)
idata = []
ivalid = []
for i, src_ram in enumerate(src_rams):
src_ram.disable_write(0)
rdata, rvalid = src_ram.read_rtl(read_addr, port=0, cond=read_fsm)
idata.append(rdata)
ivalid.append(rvalid)
read_fsm.If(read_count == n - 1)(
read_addr(0),
read_count(0)
)
read_fsm.Then().goto_next()
read_fsm.If(done)(
busy(0)
)
read_fsm.Then().goto_init()
read_fsm.make_always()
# instance
odata = m.Wire('odata', datawidth)
ovalid = m.Wire('ovalid')
ports = []
ports.append(('CLK', clk))
ports.append(('RST', rst))
for i, (d, v) in enumerate(zip(idata, ivalid)):
ports.append(('idata%d' % i, d))
ports.append(('ivalid%d' % i, v))
ports.append(('odata', odata))
ports.append(('ovalid', ovalid))
coe = None
if coe_test:
coe = [[dataflow.Constant(1, point=point) for i in range(size)]
for j in range(size)]
point = 0
st = mkStencilPipeline2D(size=3, width=datawidth, point=point, coe=coe)
m.Instance(st, 'inst_stencil', ports=ports)
skip_offset = int(math.floor(size / 2))
# write FSM
write_fsm = FSM(m, 'write_fsm', clk, rst)
write_count = m.Reg('write_count', 32, initval=0)
write_addr = m.Reg('write_addr', 32, initval=skip_offset)
write_fsm(
done(0)
)
write_fsm.If(Ands(ovalid, write_count > skip_offset))(
write_addr.inc()
)
dst_ram.write_rtl(write_addr, odata, port=0, cond=write_fsm.then)
write_fsm.If(ovalid)(
write_count.inc(),
)
write_fsm.If(write_count == n)(
write_count(0),
write_addr(skip_offset),
done(1)
)
write_fsm.Then().goto_init()
write_fsm.make_always()
return m