def test_compile_project_vhdl_extra_flags(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("modelsim.vcom_flags", ["custom", "flags"])
simif.compile_project(project)
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vcom'),
'-quiet',
'-modelsimini',
modelsim_ini,
'custom',
'flags',
'-2008',
'-work',
'lib',
'file.vhd'])
def test_compile_project_verilog_coverage(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
coverage="best",
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog")
simif.compile_project(project)
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-sv',
'-quiet',
'-modelsimini',
modelsim_ini,
'+cover=best',
'-work',
'lib',
'file.v',
'-L', 'lib'])
def test_compile_project_vhdl_coverage(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
coverage="best",
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project, vhdl_standard="2008")
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vcom'),
'-quiet',
'-modelsimini',
modelsim_ini,
'+cover=best',
'-2008',
'-work',
'lib',
'file.vhd'],
simif._compile_output_consumer) # pylint: disable=protected-access
def test_compile_project_verilog_define(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"})
simif.compile_project(project, vhdl_standard="2008")
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-sv',
'-quiet',
'-modelsimini',
modelsim_ini,
'-work',
'lib',
'file.v',
'-L', 'lib',
'+define+defname=defval'],
simif._compile_output_consumer) # pylint: disable=protected-access
def test_compile_project_vhdl_93(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="93")
simif.compile_project(project)
process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
check_args = [join(self.prefix_path, 'vcom'), '-quiet', '-modelsimini',
join(self.output_path, "modelsim.ini"), '-93',
'-work', 'lib', 'file.vhd']
check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_verilog_define(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"})
simif.compile_project(project)
process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
process_args = [join(self.prefix_path, 'vlog'), '-quiet', '-modelsimini',
join(self.output_path, "modelsim.ini"), '-work', 'lib',
'file.v', '-L', 'lib', '+define+defname=defval']
check_output.assert_called_once_with(process_args, env=simif.get_env())
def test_compile_project_vhdl_extra_flags(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("modelsim.vcom_flags", ["custom", "flags"])
simif.compile_project(project)
process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
check_args = [join(self.prefix_path, 'vcom'), '-quiet', '-modelsimini',
join(self.output_path, "modelsim.ini"), 'custom',
'flags', '-2008', '-work', 'lib', 'file.vhd']
check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_vhdl_93(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="93")
simif.compile_project(project)
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with(
[join('prefix', 'vcom'),
'-quiet',
'-modelsimini',
modelsim_ini,
'-93',
'-work',
'lib',
'file.vhd'])
def test_copies_modelsim_ini_file_from_install(self):
installed_path = join(self.output_path, "prefix")
modelsim_ini = join(self.output_path, "modelsim", "modelsim.ini")
installed_modelsim_ini = join(self.output_path, "modelsim.ini")
user_modelsim_ini = join(self.output_path, "my_modelsim.ini")
renew_path(installed_path)
with open(installed_modelsim_ini, "w") as fptr:
fptr.write("installed")
with open(user_modelsim_ini, "w") as fptr:
fptr.write("user")
ModelSimInterface(prefix=join(self.output_path, "prefix"),
modelsim_ini=modelsim_ini,
persistent=False)
with open(modelsim_ini, "r") as fptr:
self.assertEqual(fptr.read(), "installed")
def test_copies_modelsim_ini_file_from_user(self):
modelsim_ini = join(self.output_path, "modelsim.ini")
installed_modelsim_ini = join(self.prefix_path, "..", "modelsim.ini")
user_modelsim_ini = join(self.test_path, "my_modelsim.ini")
with open(installed_modelsim_ini, "w") as fptr:
fptr.write("installed")
with open(user_modelsim_ini, "w") as fptr:
fptr.write("user")
with set_env(VUNIT_MODELSIM_INI=user_modelsim_ini):
ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
with open(modelsim_ini, "r") as fptr:
self.assertEqual(fptr.read(), "user")
def test_overwrites_modelsim_ini_file_from_install(self):
modelsim_ini = join(self.output_path, "modelsim.ini")
installed_modelsim_ini = join(self.prefix_path, "..", "modelsim.ini")
user_modelsim_ini = join(self.test_path, "my_modelsim.ini")
with open(modelsim_ini, "w") as fptr:
fptr.write("existing")
with open(installed_modelsim_ini, "w") as fptr:
fptr.write("installed")
with open(user_modelsim_ini, "w") as fptr:
fptr.write("user")
ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
with open(modelsim_ini, "r") as fptr:
self.assertEqual(fptr.read(), "installed")
def test_compile_project_vhdl_93(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard=VHDL.standard("93"))
simif.compile_project(project)
process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
check_args = [join(self.prefix_path, 'vcom'), '-quiet', '-modelsimini',
join(self.output_path, "modelsim.ini"), '-93',
'-work', 'lib', 'file.vhd']
check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_verilog_define(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"})
simif.compile_project(project)
process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
process_args = [join(self.prefix_path, 'vlog'), '-quiet', '-modelsimini',
join(self.output_path, "modelsim.ini"), '-work', 'lib',
'file.v', '-L', 'lib', '+define+defname=defval']
check_output.assert_called_once_with(process_args, env=simif.get_env())
def test_compile_project_vhdl_extra_flags(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("modelsim.vcom_flags", ["custom", "flags"])
simif.compile_project(project)
process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
check_args = [join(self.prefix_path, 'vcom'), '-quiet', '-modelsimini',
join(self.output_path, "modelsim.ini"), 'custom',
'flags', '-2008', '-work', 'lib', 'file.vhd']
check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_system_verilog(self, process, check_output):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.sv", "")
project.add_source_file("file.sv", "lib", file_type="systemverilog")
simif.compile_project(project)
process.assert_called_once_with(
[join("prefix", "vlib"), "-unix", "lib_path"], env=simif.get_env())
check_output.assert_called_once_with([
join('prefix', 'vlog'), '-quiet', '-modelsimini', modelsim_ini,
'-sv', '-work', 'lib', 'file.sv', '-L', 'lib'
],
env=simif.get_env())
def test_compile_project_vhdl_coverage(self, process, check_output):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
coverage="best",
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project)
process.assert_called_once_with(
[join("prefix", "vlib"), "-unix", "lib_path"], env=simif.get_env())
check_output.assert_called_once_with([
join('prefix', 'vcom'), '-quiet', '-modelsimini', modelsim_ini,
'+cover=best', '-2008', '-work', 'lib', 'file.vhd'
],
env=simif.get_env())
def test_compile_project_verilog_define(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v",
"lib",
file_type="verilog",
defines={"defname": "defval"})
simif.compile_project(project)
process.assert_called_once_with(
[join("prefix", "vlib"), "-unix", "lib_path"], env=simif.get_env())
run_command.assert_called_once_with([
join('prefix', 'vlog'), '-quiet', '-modelsimini', modelsim_ini,
'-work', 'lib', 'file.v', '-L', 'lib', '+define+defname=defval'
],
env=simif.get_env())
def test_compile_project_verilog(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog")
simif.compile_project(project)
process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
check_args = [
join(self.prefix_path, "vlog"),
"-quiet",
"-modelsimini",
join(self.output_path, "modelsim.ini"),
"-work",
"lib",
"file.v",
"-L",
"lib",
]
check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_vhdl_93(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard="93")
simif.compile_project(project)
process.assert_called_once_with(
[join("prefix", "vlib"), "-unix", "lib_path"], env=simif.get_env())
run_command.assert_called_once_with([
join('prefix', 'vcom'), '-quiet', '-modelsimini', modelsim_ini,
'-93', '-work', 'lib', 'file.vhd'
],
env=simif.get_env())
def test_compile_project_verilog_extra_flags(self, process, check_output):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
source_file = project.add_source_file("file.v",
"lib",
file_type="verilog")
source_file.set_compile_option("modelsim.vlog_flags",
["custom", "flags"])
simif.compile_project(project)
process.assert_called_once_with(
[join("prefix", "vlib"), "-unix", "lib_path"], env=simif.get_env())
check_output.assert_called_once_with([
join('prefix', 'vlog'), '-quiet', '-modelsimini', modelsim_ini,
'custom', 'flags', '-work', 'lib', 'file.v', '-L', 'lib'
],
env=simif.get_env())
def _create_simulator_if(self):
return ModelSimInterface(join(self._output_path, "modelsim.ini"),
persistent=self._persistent_sim
and not self._gui,
gui=self._gui)
