def _preprocess(self, library_name, file_name, preprocessors):
"""
Preprocess file_name within library_name using explicit preprocessors
if preprocessors is None then use implicit globally defined processors
"""
# @TODO dependency checking etc...
if preprocessors is None:
preprocessors = [self._location_preprocessor, self._check_preprocessor]
preprocessors = [p for p in preprocessors if p is not None]
preprocessors = self._external_preprocessors + preprocessors
if len(preprocessors) == 0:
return file_name
code = ostools.read_file(file_name)
for preprocessor in preprocessors:
code = preprocessor.run(code, basename(file_name))
pp_file_name = join(self._preprocessed_path, library_name, basename(file_name))
idx = 1
while ostools.file_exists(pp_file_name):
LOGGER.debug("Preprocessed file exists '%s', adding prefix", pp_file_name)
pp_file_name = join(self._preprocessed_path,
library_name, "%i_%s" % (idx, basename(file_name)))
idx += 1
ostools.write_file(pp_file_name, code)
return pp_file_name
def test_compile_project_vhdl_extra_flags(self, process, check_output):
simif = ActiveHDLInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("activehdl.vcom_flags", ["custom", "flags"])
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
check_output.assert_called_once_with([join('prefix', 'vcom'),
'-quiet',
'-j',
self.output_path,
'custom',
'flags',
'-2008',
'-work',
'lib',
'file.vhd'],
env=simif.get_env())
def test_add_source_file_detects_illegal_vhdl_standard(self):
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
self.assertRaises(ValueError, project.add_source_file, "file.vhd",
library_name="lib", file_type='vhdl', vhdl_standard='2007')
def test_compile_project_vhdl_2002(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002")
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
check_output.assert_called_once_with(
[join('prefix', 'irun'), '-f', args_file],
env=simif.get_env())
self.assertEqual(read_file(args_file).splitlines(),
['-compile',
'-nocopyright',
'-licqueue',
'-nowarn DLCPTH',
'-nowarn DLCVAR',
'-v200x -extv200x',
'-work work',
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"),
'-quiet',
'-nclibdirname ""',
'-makelib lib_path',
'"file.vhd"',
'-endlib'])
def test_compile_project_vhdl_extra_flags(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("modelsim.vcom_flags", ["custom", "flags"])
simif.compile_project(project)
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vcom'),
'-quiet',
'-modelsimini',
modelsim_ini,
'custom',
'flags',
'-2008',
'-work',
'lib',
'file.vhd'])
def test_compile_project_verilog_hdlvar(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, hdlvar="custom_hdlvar")
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines=dict(defname="defval"))
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
check_output.assert_called_once_with(
[join('prefix', 'irun'), '-f', args_file],
env=simif.get_env())
self.assertEqual(read_file(args_file).splitlines(),
['-compile',
'-nocopyright',
'-licqueue',
'-nowarn UEXPSC',
'-nowarn DLCPTH',
'-nowarn DLCVAR',
'-work work',
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-hdlvar "custom_hdlvar"',
'-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
'-quiet',
'-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
'-define defname=defval',
'-nclibdirname ""',
'-makelib lib',
'"file.v"',
'-endlib'])
def test_compile_project_verilog_coverage(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
coverage="best",
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog")
simif.compile_project(project)
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-sv',
'-quiet',
'-modelsimini',
modelsim_ini,
'+cover=best',
'-work',
'lib',
'file.v',
'-L', 'lib'])
def test_compile_project_vhdl_coverage(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
coverage="best",
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project, vhdl_standard="2008")
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vcom'),
'-quiet',
'-modelsimini',
modelsim_ini,
'+cover=best',
'-2008',
'-work',
'lib',
'file.vhd'],
simif._compile_output_consumer) # pylint: disable=protected-access
def test_compile_project_verilog_define(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"})
simif.compile_project(project, vhdl_standard="2008")
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-sv',
'-quiet',
'-modelsimini',
modelsim_ini,
'-work',
'lib',
'file.v',
'-L', 'lib',
'+define+defname=defval'],
simif._compile_output_consumer) # pylint: disable=protected-access
def test_compile_project_verilog_define(self, process, check_output):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"})
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
check_output.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-lc',
library_cfg,
'-work',
'lib',
'file.v',
'-l', 'lib',
'+define+defname=defval'],
env=simif.get_env())
def test_finds_verilog_include_dependencies(self):
def create_project():
"""
Create the test project
"""
self.project = Project()
self.project.add_library("lib", "lib_path")
self.add_source_file("lib", "module.sv", """\
`include "include.svh"
""")
write_file("include.svh", """\
module name;
endmodule
""")
create_project()
self.assert_should_recompile(["module.sv"])
for src_file in self.project.get_files_in_compile_order():
self.update(src_file.name)
create_project()
self.assert_should_recompile([])
write_file("include.svh", """\
module other_name;
endmodule
""")
create_project()
self.assert_should_recompile(["module.sv"])
def _preprocess(self, library_name, file_name, preprocessors):
# @TODO dependency checking etc...
if preprocessors is None:
preprocessors = [self._location_preprocessor, self._check_preprocessor]
preprocessors = [p for p in preprocessors if not p is None]
preprocessors = self._external_preprocessors + preprocessors
if len(preprocessors) == 0:
return file_name
code = ostools.read_file(file_name)
for p in preprocessors:
code = p.run(code, basename(file_name))
pp_file_name = join(self._preprocessed_path, library_name, basename(file_name))
idx = 1
while ostools.file_exists(pp_file_name):
logger.debug("Preprocessed file exists '%s', adding prefix" % pp_file_name)
pp_file_name = join(self._preprocessed_path,
library_name, "%i_%s" % (idx, basename(file_name)))
idx += 1
ostools.write_file(pp_file_name, code)
return pp_file_name
def generate_codecs(input_package_design_unit, codec_package_name, # pylint: disable=too-many-arguments
used_packages, output_file, debug):
"""This function generates codecs for the types in the input package and compile the result into
codec_package_name. used_packages is a list specifying what to include into the result package
other than the input package. A used package on the format 'lib.pkg' will result in a library and
a use statement. A used package on the format 'pkg' is assumed to be located in work. output_file
is where the resulting codec package is written. The debug codecs are generated when debug is set True."""
# The design unit doesn't contain the package so it must be found first in the source file. This file
# may contain other packages
code = read_file(input_package_design_unit.source_file.name)
package = CodecVHDLPackage.find_named_package(code, input_package_design_unit.name)
if package is None:
raise KeyError(input_package_design_unit.name)
# Get all function declarations and definitions derived from the package type definitions
declarations, definitions = package.generate_codecs_and_support_functions(debug)
# Create extra use clauses
use_clauses = ''
libraries = []
for used_package in used_packages if used_packages is not None else []:
if '.' in used_package:
if used_package.split('.')[0] not in libraries:
libraries.append(used_package.split('.')[0])
use_clauses += 'use %s.all;\n' % used_package
else:
use_clauses += 'use work.%s.all;\n' % used_package
if len(libraries) != 0:
use_clauses = 'library ' + ';\nlibrary '.join(libraries) + ';\n' + use_clauses
# Assemble everything and write to output file
codec_package_template = Template("""\
library vunit_lib;
use vunit_lib.string_ops.all;
context vunit_lib.com_context;
use std.textio.all;
use work.$package_name.all;
$use_clauses
package $codec_package_name is
$declarations
end package $codec_package_name;
package body $codec_package_name is
$definitions
end package body $codec_package_name;
""")
codec_package = codec_package_template.substitute(
declarations=declarations,
definitions=definitions,
package_name=package.identifier,
codec_package_name=codec_package_name,
use_clauses=use_clauses)
write_file(output_file, codec_package)
def _create_modelsim_ini(self):
"""
Create the modelsim.ini file if it does not exist
"""
if file_exists(self._modelsim_ini):
return
write_file(self._modelsim_ini, read_file(join(self._prefix, "..", "modelsim.ini")))
def test_compile_project_verilog_hdlvar(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, hdlvar="custom_hdlvar")
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines=dict(defname="defval"))
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn UEXPSC",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-work work",
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-hdlvar "custom_hdlvar"',
'-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
"-quiet",
'-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
"-define defname=defval",
'-nclibdirname ""',
"-makelib lib",
'"file.v"',
"-endlib",
],
)
def test_compile_project_vhdl_2002(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002")
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-v200x -extv200x",
"-work work",
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"),
"-quiet",
'-nclibdirname ""',
"-makelib lib_path",
'"file.vhd"',
"-endlib",
],
)
def _create_cdslib(self):
"""
Create the cds.lib file in the output directory if it does not exist
"""
cds_root_virtuoso = self.find_cds_root_virtuoso()
if cds_root_virtuoso is None:
contents = """\
## cds.lib: Defines the locations of compiled libraries.
softinclude {0}/tools/inca/files/cds.lib
# needed for referencing the library 'basic' for cells 'cds_alias', 'cds_thru' etc. in analog models:
# NOTE: 'virtuoso' executable not found!
# define basic ".../tools/dfII/etc/cdslib/basic"
define work "{1}/libraries/work"
""".format(self._cds_root_irun, self._output_path)
else:
contents = """\
## cds.lib: Defines the locations of compiled libraries.
softinclude {0}/tools/inca/files/cds.lib
# needed for referencing the library 'basic' for cells 'cds_alias', 'cds_thru' etc. in analog models:
define basic "{1}/tools/dfII/etc/cdslib/basic"
define work "{2}/libraries/work"
""".format(self._cds_root_irun, cds_root_virtuoso, self._output_path)
write_file(self._cdslib, contents)
def compile_vhdl_file_command(self, source_file):
"""
Returns command to compile a VHDL file
"""
cmd = join(self._prefix, 'irun')
args = []
args += ['-compile']
args += ['-nocopyright']
args += ['-licqueue']
args += ['-nowarn DLCPTH'] # "cds.lib Invalid path"
args += ['-nowarn DLCVAR'] # "cds.lib Invalid environment variable ''."
args += ['%s' % self._vhdl_std_opt(source_file.get_vhdl_standard())]
args += ['-work work']
args += ['-cdslib "%s"' % self._cdslib]
args += self._hdlvar_args()
args += ['-log "%s"' % join(self._output_path, "irun_compile_vhdl_file_%s.log" % source_file.library.name)]
if not self._log_level == "debug":
args += ['-quiet']
else:
args += ['-messages']
args += ['-libverbose']
args += source_file.compile_options.get('incisive.irun_vhdl_flags', [])
args += ['-nclibdirname "%s"' % dirname(source_file.library.directory)]
args += ['-makelib %s' % source_file.library.directory]
args += ['"%s"' % source_file.name]
args += ['-endlib']
argsfile = join(self._output_path, "irun_compile_vhdl_file_%s.args" % source_file.library.name)
write_file(argsfile, "\n".join(args))
return [cmd, '-f', argsfile]
def test_compile_source_files_check_output_error(self):
simif = create_simulator_interface()
simif.compile_source_file_command.return_value = ["command"]
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
with mock.patch("vunit.simulator_interface.check_output", autospec=True) as check_output:
def check_output_side_effect(command, env=None): # pylint: disable=missing-docstring, unused-argument
raise subprocess.CalledProcessError(returncode=-1, cmd=command, output="bad stuff")
check_output.side_effect = check_output_side_effect
printer = MockPrinter()
self.assertRaises(CompileError, simif.compile_source_files, project, printer=printer)
self.assertEqual(printer.output, """\
Compiling into lib: file.vhd failed
=== Command used: ===
command
=== Command output: ===
bad stuff
Compile failed
""")
check_output.assert_called_once_with(["command"], env=simif.get_env())
self.assertEqual(project.get_files_in_compile_order(incremental=True), [source_file])
def compile_verilog_file_command(self, source_file):
"""
Returns commands to compile a Verilog file
"""
cmd = join(self._prefix, 'vlogan')
args = []
args += ['-compile']
args += ['-debug_all']
args += ['-sverilog'] # SystemVerilog
args += ['+v2k'] # Verilog 2001
args += ['-work %s' % source_file.library.name]
args += source_file.compile_options.get('vcs_verilog_flags', [])
args += ['-l %s/vcs_compile_verilog_file_%s.log' % (self._output_path, source_file.library.name)]
if not self._log_level == "debug":
args += ['-q']
args += ['-nc']
else:
args += ['-V']
args += ['-notice']
args += ['+libverbose']
for include_dir in source_file.include_dirs:
args += ['+incdir+%s' % include_dir]
for key, value in source_file.defines.items():
args += ['+define+%s=%s' % (key, value.replace('"','\\"'))]
args += ['%s' % source_file.name]
argsfile = "%s/vcs_compile_verilog_file_%s.args" % (self._output_path, source_file.library.name)
write_file(argsfile, "\n".join(args))
return [cmd, '-full64', '-f', argsfile]
def test_compile_project_verilog_error(self):
simif = GHDLInterface(prefix="prefix")
write_file("file.v", "")
project = Project()
project.add_library("lib", "lib_path")
project.add_source_file("file.v", "lib", file_type="verilog")
self.assertRaises(CompileError, simif.compile_project, project, vhdl_standard="2008")
def write(self, file_name):
"""
Write cds file to file named 'file_name'
"""
contents = "\n".join(self._other_lines +
['define %s "%s"' % item
for item in sorted(self.items())]) + "\n"
write_file(file_name, contents)
def update(self, source_file):
"""
Mark that source_file has been recompiled, triggers a re-write of the hash file
to update the timestamp
"""
new_content_hash = source_file.content_hash
ostools.write_file(self._hash_file_name_of(source_file), new_content_hash)
LOGGER.debug('Wrote %s content_hash=%s', source_file.name, new_content_hash)
def _post_process(self, report):
"""
Print the report to stdout and optionally write it to an XML file
"""
report.print_str()
if self._xunit_xml is not None:
xml = report.to_junit_xml_str()
ostools.write_file(self._xunit_xml, xml)
def test_add_source_file_has_vhdl_standard(self):
write_file("file.vhd", "")
for std in ('93', '2002', '2008'):
project = Project()
project.add_library("lib", "lib_path")
source_file = project.add_source_file("file.vhd",
library_name="lib", file_type='vhdl', vhdl_standard=std)
self.assertEqual(source_file.get_vhdl_standard(), std)
def add_architecture(self, name, file_name, contents=""):
"""
Add architecture to this entity
"""
self.architecture_names[name] = file_name
write_file(file_name, contents)
if self._add_architecture_callback is not None:
self._add_architecture_callback()
def __init__(self, name, file_name, contents=''):
self.name = name
self.library_name = "lib"
self.is_entity = False
self.is_module = True
self.generic_names = []
self.file_name = file_name
self.original_file_name = file_name
write_file(file_name, contents)
def add_source_file(self, library_name, file_name, contents):
"""
Convenient wrapper arround project.add_source_file
"""
write_file(file_name, contents)
source_file = self.project.add_source_file(file_name,
library_name,
file_type=file_type_of(file_name))
return source_file
def test_compile_project_2002(self, check_output): # pylint: disable=no-self-use
simif = GHDLInterface(prefix="prefix", output_path="")
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002")
simif.compile_project(project)
check_output.assert_called_once_with(
[join("prefix", 'ghdl'), '-a', '--workdir=lib_path', '--work=lib',
'--std=02', '-Plib_path', 'file.vhd'], env=simif.get_env())
def test_compile_project_93(self, run_command): # pylint: disable=no-self-use
simif = GHDLInterface(prefix="prefix")
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="93")
simif.compile_project(project)
run_command.assert_called_once_with(
[join("prefix", 'ghdl'), '-a', '--workdir=lib_path', '--work=lib',
'--std=93', '-Plib_path', 'file.vhd'])
def test_compile_project_vhdl_2008(self, run_command, find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard="2008")
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
run_command.assert_called_once_with(
[join('prefix', 'irun'), '-f', args_file], env=simif.get_env())
self.assertEqual(
read_file(args_file).splitlines(), [
'-compile', '-nocopyright', '-licqueue', '-nowarn DLCPTH',
'-nowarn DLCVAR', '-v200x -extv200x', '-work work',
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' %
join(self.output_path, "irun_compile_vhdl_file_lib.log"),
'-quiet', '-nclibdirname ""', '-makelib lib_path',
'"file.vhd"', '-endlib'
])
self.assertEqual(
read_file(join(self.output_path, "cds.lib")), """\
## cds.lib: Defines the locations of compiled libraries.
softinclude cds_root_irun/tools/inca/files/cds.lib
# needed for referencing the library 'basic' for cells 'cds_alias', 'cds_thru' etc. in analog models:
# NOTE: 'virtuoso' executable not found!
# define basic ".../tools/dfII/etc/cdslib/basic"
define lib "lib_path"
define work "%s/libraries/work"
""" % self.output_path)
def test_compile_project_verilog(self, check_output, find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog")
simif.compile_project(project)
args_file = str(
Path(self.output_path) / "irun_compile_verilog_file_lib.args")
check_output.assert_called_once_with(
[str(Path("prefix") / "irun"), "-f", args_file],
env=simif.get_env())
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn UEXPSC",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-work work",
'-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"),
'-log "%s"' % str(
Path(self.output_path) /
"irun_compile_verilog_file_lib.log"),
"-quiet",
'-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
'-nclibdirname "."',
"-makelib lib",
'"file.v"',
"-endlib",
],
)
def compile_vhdl_file_command(self, source_file):
"""
Returns command to compile a VHDL file
"""
cmd = join(self._prefix, "irun")
args = []
args += ["-compile"]
args += ["-nocopyright"]
args += ["-licqueue"]
args += ["-nowarn DLCPTH"] # "cds.lib Invalid path"
args += ["-nowarn DLCVAR"
] # "cds.lib Invalid environment variable ''."
args += ["%s" % self._vhdl_std_opt(source_file.get_vhdl_standard())]
args += ["-work work"]
args += ['-cdslib "%s"' % self._cdslib]
args += self._hdlvar_args()
args += [
'-log "%s"' % join(
self._output_path,
"irun_compile_vhdl_file_%s.log" % source_file.library.name,
)
]
if not self._log_level == "debug":
args += ["-quiet"]
else:
args += ["-messages"]
args += ["-libverbose"]
args += source_file.compile_options.get("incisive.irun_vhdl_flags", [])
args += ['-nclibdirname "%s"' % dirname(source_file.library.directory)]
args += ["-makelib %s" % source_file.library.directory]
args += ['"%s"' % source_file.name]
args += ["-endlib"]
argsfile = join(
self._output_path,
"irun_compile_vhdl_file_%s.args" % source_file.library.name,
)
write_file(argsfile, "\n".join(args))
return [cmd, "-f", argsfile]
def test_compile_project_vhdl_extra_flags(self, _find_prefix, process,
check_output):
simif = RivieraProInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd",
"lib",
file_type="vhdl")
source_file.set_compile_option("rivierapro.vcom_flags",
["custom", "flags"])
simif.compile_project(project)
process.assert_any_call(
[str(Path("prefix") / "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env(),
)
process.assert_called_with(
[str(Path("prefix") / "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env(),
)
check_output.assert_called_once_with(
[
str(Path("prefix") / "vcom"),
"-quiet",
"-j",
self.output_path,
"custom",
"flags",
"-2008",
"-work",
"lib",
"file.vhd",
],
env=simif.get_env(),
)
def test_compile_project_verilog_include(self, _find_prefix, process,
check_output):
library_cfg = str(Path(self.output_path) / "library.cfg")
simif = RivieraProInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v",
"lib",
file_type="verilog",
include_dirs=["include"])
simif.compile_project(project)
process.assert_any_call(
[str(Path("prefix") / "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=None,
)
process.assert_called_with(
[str(Path("prefix") / "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env(),
)
check_output.assert_called_once_with(
[
str(Path("prefix") / "vlog"),
"-quiet",
"-lc",
library_cfg,
"-work",
"lib",
"file.v",
"-l",
"lib",
"+incdir+include",
],
env=simif.get_env(),
)
def test_compile_source_files_check_output_error(self):
simif = create_simulator_interface()
simif.compile_source_file_command.return_value = ["command"]
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd",
"lib",
file_type="vhdl")
with mock.patch("vunit.simulator_interface.check_output",
autospec=True) as check_output:
def check_output_side_effect(command, **kwargs): # pylint: disable=missing-docstring
raise subprocess.CalledProcessError(returncode=-1,
cmd=command,
output="bad stuff")
check_output.side_effect = check_output_side_effect
printer = MockPrinter()
self.assertRaises(CompileError,
simif.compile_source_files,
project,
printer=printer)
self.assertEqual(
printer.output, """\
Compiling into lib: file.vhd failed
=== Command used: ===
command
=== Command output: ===
bad stuff
Compile failed
""")
check_output.assert_called_once_with(["command"],
env=simif.get_env())
self.assertEqual(project.get_files_in_compile_order(incremental=True),
[source_file])
def test_compile_project_verilog_define(self, process, check_output):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v",
"lib",
file_type="verilog",
defines={"defname": "defval"})
simif.compile_project(project)
process.assert_called_once_with(
[join("prefix", "vlib"), "-unix", "lib_path"], env=simif.get_env())
check_output.assert_called_once_with([
join('prefix', 'vlog'), '-quiet', '-modelsimini', modelsim_ini,
'-work', 'lib', 'file.v', '-L', 'lib', '+define+defname=defval'
],
env=simif.get_env())
def test_compile_source_files(self):
simif = create_simulator_interface()
simif.compile_source_file_command.side_effect = iter([["command1"], ["command2"]])
project = Project()
project.add_library("lib", "lib_path")
write_file("file1.vhd", "")
file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl")
write_file("file2.vhd", "")
file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl")
project.add_manual_dependency(file2, depends_on=file1)
with mock.patch("vunit.simulator_interface.check_output", autospec=True) as check_output:
check_output.side_effect = iter(["", ""])
printer = MockPrinter()
simif.compile_source_files(project, printer=printer)
check_output.assert_has_calls([mock.call(["command1"], env=simif.get_env()),
mock.call(["command2"], env=simif.get_env())])
self.assertEqual(printer.output, """\
Compiling into lib: file1.vhd passed
Compiling into lib: file2.vhd passed
Compile passed
""")
self.assertEqual(project.get_files_in_compile_order(incremental=True), [])
def test_compile_project_vhdl_2002(self, process, check_output):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard="2002")
simif.compile_project(project)
process.assert_called_once_with(
[join("prefix", "vlib"), "-unix", "lib_path"], env=simif.get_env())
check_output.assert_called_once_with([
join('prefix', 'vcom'), '-quiet', '-modelsimini', modelsim_ini,
'-2002', '-work', 'lib', 'file.vhd'
],
env=simif.get_env())
def test_compile_project_verilog_extra_flags(self, process, check_output):
library_cfg = join(self.output_path, "library.cfg")
simif = RivieraProInterface(prefix="prefix", library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
source_file = project.add_source_file("file.v",
"lib",
file_type="verilog")
source_file.set_compile_option("rivierapro.vlog_flags",
["custom", "flags"])
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
check_output.assert_called_once_with([
join('prefix', 'vlog'), '-quiet', '-lc', library_cfg, 'custom',
'flags', '-work', 'lib', 'file.v', '-l', 'lib'
],
env=simif.get_env())
def test_compile_project_93(self, check_output):
simif = GHDLInterface(prefix="prefix", output_path="")
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard=VHDL.standard("93"))
simif.compile_project(project)
check_output.assert_called_once_with(
[
str(Path("prefix") / "ghdl"),
"-a",
"--workdir=lib_path",
"--work=lib",
"--std=93",
"-Plib_path",
"file.vhd",
],
env=simif.get_env(),
)
def test_compile_project_verilog_include(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v",
"lib",
file_type="verilog",
include_dirs=["include"])
simif.compile_project(project)
process.assert_called_once_with(
[join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([
join('prefix',
'vlog'), '-sv', '-quiet', '-modelsimini', modelsim_ini,
'-work', 'lib', 'file.v', '-L', 'lib', '+incdir+include'
])
def test_compile_project_verilog_include(self, process, check_output):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v",
"lib",
file_type="verilog",
include_dirs=["include"])
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
check_output.assert_called_once_with([
join('prefix', 'vlog'), '-quiet', '-lc', library_cfg, '-work',
'lib', 'file.v', '-l', 'lib', '+incdir+include'
],
env=simif.get_env())
def test_compile_project_vhdl_extra_flags(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd",
"lib",
file_type="vhdl")
source_file.set_compile_option("modelsim.vcom_flags",
["custom", "flags"])
simif.compile_project(project)
process.assert_called_once_with(
[join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([
join('prefix', 'vcom'), '-quiet', '-modelsimini', modelsim_ini,
'custom', 'flags', '-2008', '-work', 'lib', 'file.vhd'
])
def test_compile_project_vhdl_93(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project, vhdl_standard="93")
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with(
[join('prefix', 'vcom'),
'-quiet',
'-modelsimini',
modelsim_ini,
'-93',
'-work',
'lib',
'file.vhd'])
def test_compile_project_verilog(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog")
simif.compile_project(project)
process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
check_args = [
join(self.prefix_path, "vlog"),
"-quiet",
"-modelsimini",
join(self.output_path, "modelsim.ini"),
"-work",
"lib",
"file.v",
"-L",
"lib",
]
check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_verilog_extra_flags(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
source_file = project.add_source_file("file.v", "lib", file_type="verilog")
source_file.set_compile_option("activehdl.vlog_flags", ["custom", "flags"])
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-sv2k12',
'-lc',
library_cfg,
'custom',
'flags',
'-work',
'lib',
'file.v',
'-l', 'lib'])
def test_compile_project_vhdl_extra_flags(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("modelsim.vcom_flags", ["custom", "flags"])
simif.compile_project(project)
process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
check_args = [
str(Path(self.prefix_path) / "vcom"),
"-quiet",
"-modelsimini",
str(Path(self.output_path) / "modelsim.ini"),
"custom",
"flags",
"-2008",
"-work",
"lib",
"file.vhd",
]
check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_verilog_define(self, process, check_output):
library_cfg = join(self.output_path, "library.cfg")
simif = RivieraProInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v",
"lib",
file_type="verilog",
defines={"defname": "defval"})
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
check_output.assert_called_once_with([
join('prefix', 'vlog'), '-quiet', '-lc', library_cfg, '-work',
'lib', 'file.v', '-l', 'lib', '+define+defname=defval'
],
env=simif.get_env())
def test_compile_project_vhdl_extra_flags(self, process, check_output):
simif = RivieraProInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd",
"lib",
file_type="vhdl")
source_file.set_compile_option("rivierapro.vcom_flags",
["custom", "flags"])
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
check_output.assert_called_once_with([
join('prefix', 'vcom'), '-quiet', '-j', self.output_path, 'custom',
'flags', '-2008', '-work', 'lib', 'file.vhd'
],
env=simif.get_env())
def preprocess(self, code, file_name="fn.v", include_paths=None):
"""
Tokenize & Preprocess
"""
tokenizer = VerilogTokenizer()
preprocessor = VerilogPreprocessor(tokenizer)
write_file(file_name, code)
tokens = tokenizer.tokenize(code, file_name=file_name)
defines = {}
included_files = []
with mock.patch(
"vunit.parsing.verilog.preprocess.LOGGER", autospec=True
) as logger:
tokens = preprocessor.preprocess(
tokens, defines, include_paths, included_files
)
return PreprocessResult(
self,
tokens,
defines,
[fname for _, fname in included_files if fname is not None],
logger,
)
def test_compile_project_extra_flags(self, check_output):
simif = GHDLInterface(prefix="prefix", output_path="")
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("ghdl.flags", ["custom", "flags"])
simif.compile_project(project)
check_output.assert_called_once_with(
[
str(Path("prefix") / "ghdl"),
"-a",
"--workdir=lib_path",
"--work=lib",
"--std=08",
"-Plib_path",
"custom",
"flags",
"file.vhd",
],
env=simif.get_env(),
)
def test_compile_project_verilog_define(self, process, check_output):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v",
"lib",
file_type="verilog",
defines={"defname": "defval"})
simif.compile_project(project)
process.assert_any_call(
[join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env(),
)
process.assert_called_with(
[join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env(),
)
check_output.assert_called_once_with(
[
join("prefix", "vlog"),
"-quiet",
"-lc",
library_cfg,
"-work",
"lib",
"file.v",
"-l",
"lib",
"+define+defname=defval",
],
env=simif.get_env(),
)
def run(self, output_path, read_output):
"""
Run selected test cases within the test suite
Returns a dictionary of test results
"""
results = {}
for name in self._test_cases:
results[name] = FAILED
if not self._config.call_pre_config(output_path,
self._simulator_if.output_path):
return results
# Ensure result file exists
ostools.write_file(get_result_file_name(output_path), "")
sim_ok = self._simulate(output_path)
if self._elaborate_only:
for name in self._test_cases:
results[name] = PASSED if sim_ok else FAILED
return results
results = self._read_test_results(
file_name=get_result_file_name(output_path))
# Do not run post check unless all passed
for status in results.values():
if status != PASSED:
return results
if not self._config.call_post_check(output_path, read_output):
for name in self._test_cases:
results[name] = FAILED
return results
def test_compile_project_vhdl_2002(self, check_output, find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard=VHDL.standard("2002"))
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
check_output.assert_called_once_with(
[join("prefix", "irun"), "-f", args_file], env=simif.get_env())
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-v200x -extv200x",
"-work work",
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' %
join(self.output_path, "irun_compile_vhdl_file_lib.log"),
"-quiet",
'-nclibdirname ""',
"-makelib lib_path",
'"file.vhd"',
"-endlib",
],
)
def test_compile_source_files_continue_on_error(self):
simif = create_simulator_interface()
project = Project()
project.add_library("lib", "lib_path")
write_file("file1.vhd", "")
file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl")
write_file("file2.vhd", "")
file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl")
write_file("file3.vhd", "")
file3 = project.add_source_file("file3.vhd", "lib", file_type="vhdl")
project.add_manual_dependency(file2, depends_on=file1)
def compile_source_file_command(source_file):
"""
Dummy compile command
"""
if source_file == file1:
return ["command1"]
if source_file == file2:
return ["command2"]
if source_file == file3:
return ["command3"]
raise AssertionError
def check_output_side_effect(command, env=None): # pylint: disable=missing-docstring, unused-argument
if command == ["command1"]:
raise subprocess.CalledProcessError(returncode=-1, cmd=command, output="bad stuff")
return ""
simif.compile_source_file_command.side_effect = compile_source_file_command
with mock.patch("vunit.simulator_interface.check_output", autospec=True) as check_output:
check_output.side_effect = check_output_side_effect
printer = MockPrinter()
self.assertRaises(CompileError, simif.compile_source_files,
project, printer=printer, continue_on_error=True)
self.assertEqual(printer.output, """\
Compiling into lib: file3.vhd passed
Compiling into lib: file1.vhd failed
=== Command used: ===
command1
=== Command output: ===
bad stuff
Compiling into lib: file2.vhd skipped
Compile failed
""")
self.assertEqual(len(check_output.mock_calls), 2)
check_output.assert_has_calls([mock.call(["command1"], env=simif.get_env()),
mock.call(["command3"], env=simif.get_env())], any_order=True)
self.assertEqual(project.get_files_in_compile_order(incremental=True), [file1, file2])
def test_compile_project_vhdl(self, process, check_output):
simif = ActiveHDLInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
check_output.assert_called_once_with(
[join('prefix', 'vcom'),
'-quiet',
'-j',
self.output_path,
'-2008',
'-work',
'lib',
'file.vhd'],
env=simif.get_env())
def test_compile_project_verilog(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog")
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-lc',
library_cfg,
'-work',
'lib',
'file.v',
'-l', 'lib'],
env=simif.get_env())
def test_compile_project_verilog_extra_flags(self, process, check_output):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
source_file = project.add_source_file("file.v",
"lib",
file_type="verilog")
source_file.set_compile_option("modelsim.vlog_flags",
["custom", "flags"])
simif.compile_project(project)
process.assert_called_once_with(
[join("prefix", "vlib"), "-unix", "lib_path"], env=simif.get_env())
check_output.assert_called_once_with([
join('prefix', 'vlog'), '-quiet', '-modelsimini', modelsim_ini,
'custom', 'flags', '-work', 'lib', 'file.v', '-L', 'lib'
],
env=simif.get_env())
def simulate(
self,
output_path, # pylint: disable=too-many-arguments
library_name,
entity_name,
architecture_name,
config,
elaborate_only):
"""
Run a test bench
"""
sim_output_path = abspath(join(output_path, self.name))
common_file_name = join(sim_output_path, "common.do")
gui_load_file_name = join(sim_output_path, "gui_load.do")
gui_run_file_name = join(sim_output_path, "gui_run.do")
batch_file_name = join(sim_output_path, "batch.do")
write_file(
common_file_name,
self._create_common_script(library_name,
entity_name,
architecture_name,
config,
output_path=sim_output_path))
write_file(gui_load_file_name,
self._create_gui_load_script(common_file_name))
write_file(gui_run_file_name,
self._create_gui_run_script(common_file_name))
write_file(batch_file_name,
self._create_batch_script(common_file_name, elaborate_only))
if self._gui_mode == "load":
return self._run_batch_file(gui_load_file_name, gui=True)
elif self._gui_mode == "run":
return self._run_batch_file(gui_run_file_name, gui=True)
elif self._persistent:
return self._run_persistent(common_file_name, elaborate_only)
else:
return self._run_batch_file(batch_file_name)
