def _assert_is_invalid(standard_string):
"""
Check that the standard string produces an exception
"""
try:
VHDL.standard(standard_string)
except ValueError:
pass
else:
raise AssertionError("Exception not raised")
def test_compile_project_vhdl_2002(self, process, check_output):
simif = ActiveHDLInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard=VHDL.standard("2002"))
simif.compile_project(project)
process.assert_any_call(
[join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env(),
)
process.assert_called_with(
[join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env(),
)
check_output.assert_called_once_with(
[
join("prefix", "vcom"),
"-quiet",
"-j",
self.output_path,
"-2002",
"-work",
"lib",
"file.vhd",
],
env=simif.get_env(),
)
def test_elaborate_e_project(self):
design_unit = Entity("tb_entity", file_name=str(Path("tempdir") / "file.vhd"))
design_unit.original_file_name = str(Path("tempdir") / "other_path" / "original_file.vhd")
design_unit.generic_names = ["runner_cfg", "tb_path"]
config = Configuration("name", design_unit, sim_options={"ghdl.elab_e": True})
simif = GHDLInterface(prefix="prefix", output_path="")
simif._vhdl_standard = VHDL.standard("2008") # pylint: disable=protected-access
simif._project = Project() # pylint: disable=protected-access
simif._project.add_library("lib", "lib_path") # pylint: disable=protected-access
self.assertEqual(
simif._get_command( # pylint: disable=protected-access
config, str(Path("output_path") / "ghdl"), True, True, None
),
[
str(Path("prefix") / "ghdl"),
"-e",
"--std=08",
"--work=lib",
"--workdir=lib_path",
"-Plib_path",
"-o",
str(Path("output_path") / "ghdl" / "tb_entity-arch"),
"tb_entity",
"arch",
],
)
def test_compile_project_vhdl_93(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard=VHDL.standard("93"))
simif.compile_project(project)
process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
check_args = [
join(self.prefix_path, "vcom"),
"-quiet",
"-modelsimini",
join(self.output_path, "modelsim.ini"),
"-93",
"-work",
"lib",
"file.vhd",
]
check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_vhdl_2002(self, check_output, find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard=VHDL.standard("2002"))
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
check_output.assert_called_once_with(
[join('prefix', 'irun'), '-f', args_file], env=simif.get_env())
self.assertEqual(
read_file(args_file).splitlines(), [
'-compile', '-nocopyright', '-licqueue', '-nowarn DLCPTH',
'-nowarn DLCVAR', '-v200x -extv200x', '-work work',
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' %
join(self.output_path, "irun_compile_vhdl_file_lib.log"),
'-quiet', '-nclibdirname ""', '-makelib lib_path',
'"file.vhd"', '-endlib'
])
def test_elaborate_e_project(self):
design_unit = Entity('tb_entity', file_name=join("tempdir", "file.vhd"))
design_unit.original_file_name = join("tempdir", "other_path", "original_file.vhd")
design_unit.generic_names = ["runner_cfg", "tb_path"]
config = Configuration("name", design_unit, sim_options={"ghdl.elab_e": True})
simif = GHDLInterface(prefix="prefix", output_path="")
simif._vhdl_standard = VHDL.standard("2008") # pylint: disable=protected-access
simif._project = Project() # pylint: disable=protected-access
simif._project.add_library("lib", "lib_path") # pylint: disable=protected-access
self.assertEqual(
simif._get_command(config, join('output_path', 'ghdl'), True), # pylint: disable=protected-access
[
join('prefix', 'ghdl'),
'-e',
'--std=08',
'--work=lib',
'--workdir=lib_path',
'-Plib_path',
'-o', join('output_path', 'ghdl', 'tb_entity-arch'),
'tb_entity', 'arch'
]
)
def test_compile_project_93(self, check_output): # pylint: disable=no-self-use
simif = GHDLInterface(prefix="prefix", output_path="")
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard=VHDL.standard("93"))
simif.compile_project(project)
check_output.assert_called_once_with(
[join("prefix", 'ghdl'), '-a', '--workdir=lib_path', '--work=lib',
'--std=93', '-Plib_path', 'file.vhd'], env=simif.get_env())
def test_compile_project_vhdl_2008(self, check_output, find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard=VHDL.standard("2008"))
simif.compile_project(project)
args_file = str(
Path(self.output_path) / "irun_compile_vhdl_file_lib.args")
check_output.assert_called_once_with(
[str(Path("prefix") / "irun"), "-f", args_file],
env=simif.get_env())
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-v200x -extv200x",
"-work work",
'-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"),
'-log "%s"' %
str(Path(self.output_path) / "irun_compile_vhdl_file_lib.log"),
"-quiet",
'-nclibdirname "."',
"-makelib lib_path",
'"file.vhd"',
"-endlib",
],
)
self.assertEqual(
read_file(str(Path(self.output_path) / "cds.lib")),
"""\
## cds.lib: Defines the locations of compiled libraries.
softinclude cds_root_irun/tools/inca/files/cds.lib
# needed for referencing the library 'basic' for cells 'cds_alias', 'cds_thru' etc. in analog models:
# NOTE: 'virtuoso' executable not found!
# define basic ".../tools/dfII/etc/cdslib/basic"
define lib "lib_path"
define work "%s/libraries/work"
""" % self.output_path,
)
def test_compile_project_93(self, check_output):
simif = GHDLInterface(prefix="prefix", output_path="")
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard=VHDL.standard("93"))
simif.compile_project(project)
check_output.assert_called_once_with(
[
str(Path("prefix") / "ghdl"),
"-a",
"--workdir=lib_path",
"--work=lib",
"--std=93",
"-Plib_path",
"file.vhd",
],
env=simif.get_env(),
)
def test_compile_project_vhdl_2002(self, process, check_output):
simif = RivieraProInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard=VHDL.standard("2002"))
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
check_output.assert_called_once_with([
join('prefix', 'vcom'), '-quiet', '-j', self.output_path, '-2002',
'-work', 'lib', 'file.vhd'
],
env=simif.get_env())
def test_compile_project_vhdl_2002(self, check_output, find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard=VHDL.standard("2002"))
simif.compile_project(project)
args_file = str(
Path(self.output_path) / "irun_compile_vhdl_file_lib.args")
check_output.assert_called_once_with(
[str(Path("prefix") / "irun"), "-f", args_file],
env=simif.get_env())
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-v200x -extv200x",
"-work work",
'-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"),
'-log "%s"' %
str(Path(self.output_path) / "irun_compile_vhdl_file_lib.log"),
"-quiet",
'-nclibdirname "."',
"-makelib lib_path",
'"file.vhd"',
"-endlib",
],
)
def test_str():
assert str(VHDL.standard("1993")) == "93"
assert str(VHDL.standard("2002")) == "2002"
def test_comparison():
assert VHDL.standard("1993") < VHDL.standard("2002")
assert VHDL.standard("2002") < VHDL.standard("2008")
assert VHDL.standard("2008") < VHDL.standard("2019")
def test_equality():
assert VHDL.standard("2008") == VHDL.standard("2008")
assert VHDL.standard("1993") != VHDL.standard("2008")
assert VHDL.standard("93") == VHDL.standard("1993")
def test_valid_standards():
for std in ["93", "02", "08", "19", "1993", "2002", "2008", "2019"]:
VHDL.standard(std)
def load_runner_hooks(python_file=r''):
if len(python_file) > 0:
return load_module_from_file('vunit_runner_hooks', python_file)
else:
return __import__('edalize.vunit_hooks', fromlist=['vunit_hooks'])
runner = load_runner_hooks().VUnitRunner()
# Override this hook to allow custom creation configuration of the VUnit instance:
vu = runner.create()
lib = vu.add_library("vunit_test_runner_lib")
lib.add_source_files("sv_file.sv")
lib.add_source_files("vlog_file.v")
lib.add_source_files("vlog05_file.v")
lib.add_source_files("vhdl_file.vhd")
lib.add_source_files("vhdl2008_file", vhdl_standard=VHDL.standard("2008"))
# Override this hook to customize the library, e.g. compile-flags etc.
# This allows full access to vunit.ui.Library interface:
runner.handle_library("vunit_test_runner_lib", lib)
lib = vu.add_library("libx")
lib.add_source_files("vhdl_lfile")
# Override this hook to customize the library, e.g. compile-flags etc.
# This allows full access to vunit.ui.Library interface:
runner.handle_library("libx", lib)
# override this hook to perform final customization and parametrization of VUnit, custom invokation, etc.
runner.main(vu)
