def half_adder(in1, in2, sum, carry, the_agenda):
d = wire.wire()
e = wire.wire()
or_gate(in1, in2, d, the_agenda)
and_gate(in1, in2, carry, the_agenda)
inverter(carry, e, the_agenda)
and_gate(d, e, sum, the_agenda)
def add_wire(self, layers, coordinates):
"""Connects a routing path on given layer,coordinates,width.
The layers are the (horizontal, via, vertical). """
import wire
# add an instance of our path that breaks down into rectangles and contacts
wire.wire(obj=self,
layer_stack=layers,
position_list=coordinates)
def and_gate_test(the_agenda):
in1 = wire.wire()
in2 = wire.wire()
out = wire.wire()
andg = basics.and_gate(in1, in2, out, the_agenda)
utils.probe("in1", in1, the_agenda)
utils.probe("in2", in2, the_agenda)
utils.probe("out", out, the_agenda)
def half_adder_test(the_agenda):
in1 = wire.wire()
in2 = wire.wire()
sum = wire.wire()
carry = wire.wire()
basics.half_adder(in1, in2, sum, carry, the_agenda)
in1.set_signal(1)
utils.probe("sum", sum, the_agenda)
utils.probe("carry", carry, the_agenda)
utils.propagate(the_agenda)
in2.set_signal(1)
utils.propagate(the_agenda)
def get_wire(variable, bit_val, wires, the_agenda):
in_wire = wire.wire()
output_wire = in_wire
# check whether the bit corresponding to the
# variable is turned on or not
if bit_val == qm.bit_one:
strvar = variable
else: # bit_zero
strvar = '~' + variable
output_wire = wire.wire()
basics.inverter(in_wire, output_wire, the_agenda)
# cache the wires to avoid duplicating inputs
if strvar not in wires:
wires[strvar] = output_wire
return wires[strvar]
def build_circuitry(wires, the_agenda, gate):
ckt_output = wires.pop()
while len(wires) > 0:
cur_output = wire.wire()
cur_wire = wires.pop()
gate(ckt_output, cur_wire, cur_output, the_agenda)
ckt_output = cur_output
return ckt_output
def removeMergePoint(self, startpoint, endpoint):
wire_list = self.wires
for a_wire in self.wires:
if a_wire.startpoint == endpoint or a_wire.endpoint == startpoint:
if a_wire.startpoint == endpoint:
new_endpoint = a_wire.endpoint
wire_list.remove(a_wire)
else:
new_startpoint = a_wire.startpoint
wire_list.remove(a_wire)
wire_list.append(wire(new_startpoint, new_endpoint))
self.wires = wire_list
def merge(points, seg_length):
new_points = []
new_wires = []
end_point_location = get_center(points)
end_point = M_Point(location=end_point_location)
end_point.set_gid(points[0].get_gid())
for i in range(len(points)):
direct_wire = wire(end_point, points[i])
new_points += [end_point, points[i]]
new_wires += [direct_wire]
return end_point, new_points, new_wires
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import wire
import tech
import design
layer_stacks = [tech.poly_stack] + tech.beol_stacks
for reverse in [False, True]:
for stack in layer_stacks:
if reverse:
layer_stack = stack[::-1]
else:
layer_stack = stack
# Just make a conservative spacing. Make it wire pitch instead?
min_space = 2 * (
tech.drc["minwidth_{}".format(layer_stack[0])] +
tech.drc["minwidth_{}".format(layer_stack[2])])
position_list = [[0, 0], [0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space],
[4 * min_space, 0], [7 * min_space, 0],
[7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space],
[-1 * min_space, 0]]
position_list = [[x - min_space, y - min_space]
for x, y in position_list]
w = design.design("wire_test_{}".format("_".join(layer_stack)))
wire.wire(w, layer_stack, position_list)
self.local_drc_check(w)
globals.end_openram()
def add_wire(self, layers, coordinates, offset=None):
"""Connects a routing path on given layer,coordinates,width.
The layers are the (vertical, via, horizontal). """
import wire
debug.info(3, "add wire " + str(layers) + " " + str(coordinates))
# Wires/paths are created so that the first point is (0,0)
# therefore we offset the instantiation to the first point
# however, we can override this
if offset == None:
inst_offset = coordinates[0]
else:
inst_offset = offset
# add an instance of our path that breaks down into rectangles and contacts
route = wire.wire(layer_stack=layers, position_list=coordinates)
self.add_mod(route)
self.add_inst(name=route.name, mod=route, offset=inst_offset)
# We don't model the logical connectivity of wires/paths
self.connect_inst([])
return route
def runTest(self):
globals.init_AMC("config_20_{0}".format(OPTS.tech_name))
global calibre
import calibre
OPTS.check_lvsdrc = False
import wire
import tech
import design
min_space = 2 * (tech.drc["minwidth_poly"] +
tech.drc["minwidth_metal1"])
layer_stack = ("poly", "contact", "metal1")
old_position_list = [[0, 0], [0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space],
[4 * min_space, 0], [7 * min_space, 0],
[7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space],
[-1 * min_space, 0]]
position_list = [[x - min_space, y - min_space]
for x, y in old_position_list]
w = design.design("wire_test1")
wire.wire(w, layer_stack, position_list)
self.local_drc_check(w)
min_space = 2 * (tech.drc["minwidth_poly"] +
tech.drc["minwidth_metal1"])
layer_stack = ("metal1", "contact", "poly")
old_position_list = [[0, 0], [0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space],
[4 * min_space, 0], [7 * min_space, 0],
[7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space],
[-1 * min_space, 0]]
position_list = [[x + min_space, y + min_space]
for x, y in old_position_list]
w = design.design("wire_test2")
wire.wire(w, layer_stack, position_list)
self.local_drc_check(w)
min_space = 2 * (tech.drc["minwidth_metal2"] +
tech.drc["minwidth_metal1"])
layer_stack = ("metal1", "via1", "metal2")
position_list = [[0, 0], [0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space], [4 * min_space, 0],
[7 * min_space, 0], [7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space], [-1 * min_space, 0]]
w = design.design("wire_test3")
wire.wire(w, layer_stack, position_list)
self.local_drc_check(w)
min_space = 2 * (tech.drc["minwidth_metal2"] +
tech.drc["minwidth_metal1"])
layer_stack = ("metal2", "via1", "metal1")
position_list = [[0, 0], [0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space], [4 * min_space, 0],
[7 * min_space, 0], [7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space], [-1 * min_space, 0]]
w = design.design("wire_test4")
wire.wire(w, layer_stack, position_list)
self.local_drc_check(w)
min_space = 2 * (tech.drc["minwidth_metal2"] +
tech.drc["minwidth_metal3"])
layer_stack = ("metal2", "via2", "metal3")
position_list = [[0, 0], [0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space], [4 * min_space, 0],
[7 * min_space, 0], [7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space], [-1 * min_space, 0]]
position_list.reverse()
w = design.design("wire_test5")
wire.wire(w, layer_stack, position_list)
self.local_drc_check(w)
min_space = 2 * (tech.drc["minwidth_metal2"] +
tech.drc["minwidth_metal3"])
layer_stack = ("metal3", "via2", "metal2")
position_list = [[0, 0], [0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space], [4 * min_space, 0],
[7 * min_space, 0], [7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space], [-1 * min_space, 0]]
position_list.reverse()
w = design.design("wire_test6")
wire.wire(w, layer_stack, position_list)
self.local_drc_check(w)
# return it back to it's normal state
OPTS.check_lvsdrc = True
globals.end_AMC()
from wire import wire
from findIntersections import findIntersections
from writeOutput import writeOutput
wire1 = wire('data', 0)
wire2 = wire('data', 1)
intersections = findIntersections(wire1.turnCoords, wire2.turnCoords)
writeOutput(wire1, wire2, intersections)
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import wire
import tech
min_space = 2 * (tech.drc["minwidth_poly"] +
tech.drc["minwidth_metal1"])
layer_stack = ("poly", "contact", "metal1")
position_list = [[0, 0], [0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space], [4 * min_space, 0],
[7 * min_space, 0], [7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space], [-1 * min_space, 0]]
OPTS.check_lvsdrc = False
w = wire.wire(layer_stack, position_list)
OPTS.check_lvsdrc = True
self.local_check(w)
min_space = 2 * (tech.drc["minwidth_poly"] +
tech.drc["minwidth_metal1"])
layer_stack = ("metal1", "contact", "poly")
position_list = [[0, 0], [0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space], [4 * min_space, 0],
[7 * min_space, 0], [7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space], [-1 * min_space, 0]]
OPTS.check_lvsdrc = False
w = wire.wire(layer_stack, position_list)
OPTS.check_lvsdrc = True
self.local_check(w)
min_space = 2 * (tech.drc["minwidth_metal2"] +
tech.drc["minwidth_metal1"])
layer_stack = ("metal1", "via1", "metal2")
position_list = [[0, 0], [0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space], [4 * min_space, 0],
[7 * min_space, 0], [7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space], [-1 * min_space, 0]]
OPTS.check_lvsdrc = False
w = wire.wire(layer_stack, position_list)
OPTS.check_lvsdrc = True
self.local_check(w)
min_space = 2 * (tech.drc["minwidth_metal2"] +
tech.drc["minwidth_metal1"])
layer_stack = ("metal2", "via1", "metal1")
position_list = [[0, 0], [0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space], [4 * min_space, 0],
[7 * min_space, 0], [7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space], [-1 * min_space, 0]]
OPTS.check_lvsdrc = False
w = wire.wire(layer_stack, position_list)
OPTS.check_lvsdrc = True
self.local_check(w)
min_space = 2 * (tech.drc["minwidth_metal2"] +
tech.drc["minwidth_metal3"])
layer_stack = ("metal2", "via2", "metal3")
position_list = [[0, 0], [0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space], [4 * min_space, 0],
[7 * min_space, 0], [7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space], [-1 * min_space, 0]]
position_list.reverse()
OPTS.check_lvsdrc = False
w = wire.wire(layer_stack, position_list)
OPTS.check_lvsdrc = True
self.local_check(w)
min_space = 2 * (tech.drc["minwidth_metal2"] +
tech.drc["minwidth_metal3"])
layer_stack = ("metal3", "via2", "metal2")
position_list = [[0, 0], [0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space], [4 * min_space, 0],
[7 * min_space, 0], [7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space], [-1 * min_space, 0]]
position_list.reverse()
OPTS.check_lvsdrc = False
w = wire.wire(layer_stack, position_list)
OPTS.check_lvsdrc = True
self.local_check(w)
# return it back to it's normal state
OPTS.check_lvsdrc = True
globals.end_openram()
def changeToWire(self):
return wire(self.startpoint, self.endpoint)
def inverter_test(the_agenda):
a = wire.wire()
b = wire.wire()
inv = basics.inverter(a, b, the_agenda)
utils.probe("a", a, the_agenda)
utils.probe("b", b, the_agenda)
def hieraMerge(self):
# merge in bottom-up order
branchs = self.num_branchs[::-1]
l_branch = len(branchs)
merge_times = len(self.sinks)
merged_points = []
for i, branch in enumerate(branchs):
seg_length = []
candidate = []
if i == 0:
# merge sinks
merge_times /= branch
points = sorted(self.sinks, key=lambda u: u.get_gid()[-2])
for j in range(int(merge_times)):
seg_length.append(
get_seg_length(points[branch * j:branch * (j + 1)]))
target_seg_length = max(seg_length)
self.wirelength.append(target_seg_length)
for j in range(int(merge_times)):
merged_point, nodes, wires = merge(
points[branch * j:branch * (j + 1)], target_seg_length)
self.nodes.extend(nodes)
self.nodes.append(merged_point)
self.wires.extend(wires)
new_point, candidate_buffer = self.candidateBuffer(
merged_point)
candidate.append(candidate_buffer)
self.nodes.append(new_point)
merged_points.append(new_point)
self.candidates.append(candidate)
elif i < (l_branch - 1):
# merge sub-level points
new_merged_points = []
merge_times /= branch
points = sorted(merged_points,
key=lambda point: point.get_gid()[-2 - i])
for j in range(int(merge_times)):
seg_length.append(
get_seg_length(points[branch * j:branch * (j + 1)]))
target_seg_length = max(seg_length)
self.wirelength.append(target_seg_length)
for j in range(int(merge_times)):
merged_point, nodes, wires = merge(
points[branch * j:branch * (j + 1)], target_seg_length)
self.nodes.extend(nodes)
self.nodes.append(merged_point)
self.wires.extend(wires)
new_point, candidate_buffer = self.candidateBuffer(
merged_point)
candidate.append(candidate_buffer)
self.nodes.append(new_point)
new_merged_points.append(new_point)
self.candidates.append(candidate)
merged_points = new_merged_points
else:
# merge to get clock tree root point
target_seg_length = get_seg_length(merged_points)
self.wirelength.append(target_seg_length)
root, nodes, wires = merge(merged_points, target_seg_length)
self.nodes.extend(nodes)
self.nodes.append(root)
self.wires.extend(wires)
new_root, candidate_buffer = self.candidateBuffer(root)
self.nodes.append(new_root)
self.candidates.append([candidate_buffer])
# link root to sourcenode at (0,0)
self.wires.append(wire(Point(0, 0), new_root))
self.wirelength.append(root.location.real + root.location.imag)
# reverse order to top-down
self.wirelength = self.wirelength[::-1]
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import wire
import tech
import design
min_space = 2 * (tech.drc["minwidth_poly"] +
tech.drc["minwidth_metal1"])
layer_stack = ("poly", "contact", "metal1")
old_position_list = [[0, 0],
[0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space],
[4 * min_space, 0],
[7 * min_space, 0],
[7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space],
[-1 * min_space, 0]]
position_list = [[x-min_space, y-min_space] for x,y in old_position_list]
w = design.design("wire_test1")
wire.wire(w, layer_stack, position_list)
self.local_drc_check(w)
min_space = 2 * (tech.drc["minwidth_poly"] +
tech.drc["minwidth_metal1"])
layer_stack = ("metal1", "contact", "poly")
old_position_list = [[0, 0],
[0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space],
[4 * min_space, 0],
[7 * min_space, 0],
[7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space],
[-1 * min_space, 0]]
position_list = [[x+min_space, y+min_space] for x,y in old_position_list]
w = design.design("wire_test2")
wire.wire(w, layer_stack, position_list)
self.local_drc_check(w)
min_space = 2 * (tech.drc["minwidth_metal2"] +
tech.drc["minwidth_metal1"])
layer_stack = ("metal1", "via1", "metal2")
position_list = [[0, 0],
[0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space],
[4 * min_space, 0],
[7 * min_space, 0],
[7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space],
[-1 * min_space, 0]]
w = design.design("wire_test3")
wire.wire(w, layer_stack, position_list)
self.local_drc_check(w)
min_space = 2 * (tech.drc["minwidth_metal2"] +
tech.drc["minwidth_metal1"])
layer_stack = ("metal2", "via1", "metal1")
position_list = [[0, 0],
[0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space],
[4 * min_space, 0],
[7 * min_space, 0],
[7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space],
[-1 * min_space, 0]]
w = design.design("wire_test4")
wire.wire(w, layer_stack, position_list)
self.local_drc_check(w)
min_space = 2 * (tech.drc["minwidth_metal2"] +
tech.drc["minwidth_metal3"])
layer_stack = ("metal2", "via2", "metal3")
position_list = [[0, 0],
[0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space],
[4 * min_space, 0],
[7 * min_space, 0],
[7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space],
[-1 * min_space, 0]]
position_list.reverse()
w = design.design("wire_test5")
wire.wire(w, layer_stack, position_list)
self.local_drc_check(w)
min_space = 2 * (tech.drc["minwidth_metal2"] +
tech.drc["minwidth_metal3"])
layer_stack = ("metal3", "via2", "metal2")
position_list = [[0, 0],
[0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space],
[4 * min_space, 0],
[7 * min_space, 0],
[7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space],
[-1 * min_space, 0]]
position_list.reverse()
w = design.design("wire_test6")
wire.wire(w, layer_stack, position_list)
self.local_drc_check(w)
globals.end_openram()
