示例#1
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 def visit_MLIL_CMP_ULE(self, expr):
     left, right = self.visit_both_sides(expr)
     if right.size() != left.size():
         right = ZeroExt(left.size() - right.size(), right)
     return ULE(left, right)
示例#2
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    def visit_MLIL_CMP_ULE(self, expr):
        left, right = self.visit_both_sides(expr)

        return ULE(left, right)
示例#3
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from rule import Rule
from z3 import BitVec,  BitVecVal, ULE

"""
Rule:
SIGNEXTEND(A, SHR(B, X)) -> SAR(B, X)
given
    B % 8 == 0 AND
    A <= WordSize AND
    B <= wordSize AND
    (WordSize - B) / 8 == A + 1
"""

n_bits = 256

# Input vars
X = BitVec('X', n_bits)
Y = BitVec('Y', n_bits)
A = BitVec('A', n_bits)
B = BitVec('B', n_bits)

rule = Rule()
rule.require(B % 8 == 0)
rule.require(ULE(A, n_bits))
rule.require(ULE(B, n_bits))
rule.require((BitVecVal(n_bits, n_bits) - B) / 8 == A + 1)
rule.check(
    SIGNEXTEND(A, SHR(B, X)),
    SAR(B, X)
)
示例#4
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from opcodes import BYTE, SHL
from rule import Rule
from z3 import BitVec, ULE
"""
byte(A, shl(B, X))
given B % 8 == 0 && A <= 32 && B <= 256
->
byte(A + B / 8, X)
"""

rule = Rule()

n_bits = 256

# Input vars
X = BitVec('X', n_bits)
A = BitVec('A', n_bits)
B = BitVec('B', n_bits)

# Non optimized result
nonopt = BYTE(A, SHL(B, X))
# Optimized result
opt = BYTE(A + B / 8, X)

rule.require(B % 8 == 0)
rule.require(ULE(A, 32))
rule.require(ULE(B, 256))

rule.check(nonopt, opt)
示例#5
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 def is_consistent(self):
     return super().is_consistent() + [
         ULE(self.partition.start, self.start),
         ULT(self.end, self.partition.end)
     ]
示例#6
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 def contains(self, addr):
     return And(ULE(self.start, addr), ULT(addr, self.end))
示例#7
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 def is_enabled(self, addr):
     return And(self.enabled, ULE(self.start, addr), ULT(addr, self.end))