def create_system(self):
mdesc = SysConfig(disk="linux-x86.img")
system = FSConfig.makeLinuxX86System(self.mem_mode, numCPUs=self.num_cpus, mdesc=mdesc)
system.kernel = FSConfig.binary("x86_64-vmlinux-2.6.22.9")
self.init_system(system)
return system
def create_system(self):
mdesc = SysConfig(disk = 'linux-x86.img')
system = FSConfig.makeLinuxX86System(self.mem_mode,
numCPUs=self.num_cpus,
mdesc=mdesc)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
self.init_system(system)
return system
import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
from Benchmarks import SysConfig
import FSConfig
from Caches import *
mem_size = '128MB'
#cpu
cpu = AtomicSimpleCPU(cpu_id=0)
#the system
mdesc = SysConfig(disk = 'linux-x86.img')
system = FSConfig.makeLinuxX86System('atomic', mdesc=mdesc)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
system.cpu = cpu
#create the iocache
system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4),
L2(size = '4MB', assoc = 8),
PageTableWalkerCache(),
PageTableWalkerCache())
# create the interrupt controller
# races between requests and writebacks.
options.l1d_size = "32kB"
options.l1i_size = "32kB"
options.l2_size = "4MB"
options.l1d_assoc = 2
options.l1i_assoc = 2
options.l2_assoc = 2
options.num_cpus = 2
# the system
mdesc = SysConfig(disk="linux-x86.img")
system = FSConfig.makeLinuxX86System("timing", options.num_cpus, mdesc=mdesc, Ruby=True)
# Dummy voltage domain for all our clock domains
system.voltage_domain = VoltageDomain(voltage=options.sys_voltage)
system.kernel = FSConfig.binary("x86_64-vmlinux-2.6.22.9.smp")
system.clk_domain = SrcClockDomain(clock="1GHz", voltage_domain=system.voltage_domain)
system.cpu_clk_domain = SrcClockDomain(clock="2GHz", voltage_domain=system.voltage_domain)
system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain=system.cpu_clk_domain) for i in xrange(options.num_cpus)]
Ruby.create_system(options, True, system, system.iobus, system._dma_ports)
# Create a seperate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(clock=options.ruby_clock, voltage_domain=system.voltage_domain)
# Connect the ruby io port to the PIO bus,
# assuming that there is just one such port.
system.iobus.master = system.ruby._io_port.slave
for (i, cpu) in enumerate(system.cpu):
# create the interrupt controller
