Python FSConfig.makeLinuxAlphaSystem Beispiele

Beispiel #1

Datei: tsunami-inorder.py Projekt: nvgreensocs/gem5-systemc-armmodel

    block_size = 64
    latency = '50ns'
    mshrs = 20
    size = '1kB'
    tgts_per_mshr = 12
    addr_range=AddrRange(0, size='8GB')
    forward_snoops = False
    is_top_level = True

#cpu
cpu = InOrderCPU(cpu_id=0)
cpu.stageWidth = 4
cpu.fetchBuffSize = 1

#the system
system = FSConfig.makeLinuxAlphaSystem('timing')

system.cpu = cpu
#create the l1/l2 bus
system.toL2Bus = Bus()
system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.port
system.iocache.mem_side = system.membus.port


#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.port
system.l2c.mem_side = system.membus.port

Beispiel #2

# Authors: Steve Reinhardt

import m5
from m5.objects import *

m5.util.addToPath('../configs/common')
import FSConfig
from Caches import *

#cpu
cpu = InOrderCPU(cpu_id=0)
cpu.stageWidth = 4
cpu.fetchBuffSize = 1

#the system
system = FSConfig.makeLinuxAlphaSystem('timing')

system.cpu = cpu

#create the iocache
system.iocache = IOCache(clock='1GHz', addr_ranges=[AddrRange('8GB')])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave

#connect up the cpu and caches
cpu.addTwoLevelCacheHierarchy(L1(size='32kB', assoc=1), L1(size='32kB',
                                                           assoc=4),
                              L2(size='4MB', assoc=8))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu and caches to the rest of the system

Beispiel #3

Datei: tsunami-simple-atomic-dual.py Projekt: koparasy/faultinjection-gem5

# ---------------------
class IOCache(BaseCache):
    assoc = 8
    block_size = 64
    latency = '50ns'
    mshrs = 20
    size = '1kB'
    tgts_per_mshr = 12
    addr_range=AddrRange(0, size='8GB')
    forward_snoops = False
    is_top_level = True

#cpu
cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
#the system
system = FSConfig.makeLinuxAlphaSystem('atomic')
system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.port
system.iocache.mem_side = system.membus.port

system.cpu = cpus
#create the l1/l2 bus
system.toL2Bus = Bus()

#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.port
system.l2c.mem_side = system.membus.port
system.l2c.num_cpus = 2

Beispiel #4

Datei: tsunami-simple-atomic-dual.py Projekt: liangwang/m5

# ---------------------
class IOCache(BaseCache):
    assoc = 8
    block_size = 64
    latency = '50ns'
    mshrs = 20
    size = '1kB'
    tgts_per_mshr = 12
    addr_range = AddrRange(0, size='8GB')
    forward_snoops = False


#cpu
cpus = [AtomicSimpleCPU(cpu_id=i) for i in xrange(2)]
#the system
system = FSConfig.makeLinuxAlphaSystem('atomic')
system.bridge.filter_ranges_a = [AddrRange(0, Addr.max)]
system.bridge.filter_ranges_b = [AddrRange(0, size='8GB')]
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.port
system.iocache.mem_side = system.membus.port

system.cpu = cpus
#create the l1/l2 bus
system.toL2Bus = Bus()

#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.port
system.l2c.mem_side = system.membus.port
system.l2c.num_cpus = 2

Beispiel #5

Datei: tsunami-simple-timing-dual.py Projekt: koparasy/faultinjection-gem5

class IOCache(BaseCache):
    assoc = 8
    block_size = 64
    latency = "50ns"
    mshrs = 20
    size = "1kB"
    tgts_per_mshr = 12
    addr_range = AddrRange(0, size="8GB")
    forward_snoops = False
    is_top_level = True


# cpu
cpus = [TimingSimpleCPU(cpu_id=i) for i in xrange(2)]
# the system
system = FSConfig.makeLinuxAlphaSystem("timing")
system.bridge.filter_ranges_a = [AddrRange(0, Addr.max)]
system.bridge.filter_ranges_b = [AddrRange(0, size="8GB")]
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.port
system.iocache.mem_side = system.membus.port

system.cpu = cpus
# create the l1/l2 bus
system.toL2Bus = Bus()

# connect up the l2 cache
system.l2c = L2(size="4MB", assoc=8)
system.l2c.cpu_side = system.toL2Bus.port
system.l2c.mem_side = system.membus.port
system.l2c.num_cpus = 2

Beispiel #6

Datei: alpha_generic.py Projekt: eepalms/gem5-newcache

 def create_system(self):
     system = FSConfig.makeLinuxAlphaSystem(self.mem_mode, DDR3_1600_x64)
     self.init_system(system)
     return system

Beispiel #7

Datei: alpha_generic.py Projekt: souravsanyal06/gem5

 def create_system(self):
     system = FSConfig.makeLinuxAlphaSystem(self.mem_mode, SimpleDDR3)
     self.init_system(system)
     return system

Beispiel #8

Datei: tsunami-simple-atomic.py Projekt: hoangt/gem5v

# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Steve Reinhardt

import m5
from m5.objects import *

m5.util.addToPath("../configs/common")
import FSConfig
from Caches import *

# cpu
cpu = AtomicSimpleCPU(cpu_id=0)
# the system
system = FSConfig.makeLinuxAlphaSystem("atomic")

system.cpu = cpu

# create the iocache
system.iocache = IOCache(clock="1GHz", addr_ranges=[AddrRange("8GB")])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave

# connect up the cpu and caches
cpu.addTwoLevelCacheHierarchy(L1(size="32kB", assoc=1), L1(size="32kB", assoc=4), L2(size="4MB", assoc=8))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu and caches to the rest of the system
cpu.connectAllPorts(system.membus)
# set the cpu clock along with the caches and l1-l2 bus

Beispiel #9

Datei: alpha_generic.py Projekt: joerocklin/gem5

 def create_system(self):
     system = FSConfig.makeLinuxAlphaSystem(self.mem_mode, SimpleDDR3)
     self.init_system(system)
     return system