voltage_domain=VoltageDomain(voltage='1V'))
mem_range = AddrRange(options.mem_size)
system.mem_ranges = [mem_range]
# do not worry about reserving space for the backing store
system.mmap_using_noreserve = True
# currently not exposed as command-line options, set here for now
options.mem_channels = 1
options.mem_ranks = 1
options.external_memory_system = 0
options.tlm_memory = 0
options.elastic_trace_en = 0
MemConfig.config_mem(options, system)
# there is no point slowing things down by saving any data
for ctrl in system.mem_ctrls:
ctrl.null = True
# the following assumes that we are using the native DRAM
# controller, check to be sure
if isinstance(ctrl, m5.objects.DRAMCtrl):
# make the DRAM refresh interval sufficiently infinite to avoid
# latency spikes
ctrl.tREFI = '100s'
# use the same concept as the utilisation sweep, and print the config
# so that we can later read it in
cfg_file_name = os.path.join(m5.options.outdir, "lat_mem_rd.cfg")
for i in xrange(np):
ruby_port = system.ruby._cpu_ports[i]
# Create the interrupt controller and connect its ports to Ruby
# Note that the interrupt controller is always present but only
# in x86 does it have message ports that need to be connected
system.cpu[i].createInterruptController()
# Connect the cpu's cache ports to Ruby
system.cpu[i].icache_port = ruby_port.slave
system.cpu[i].dcache_port = ruby_port.slave
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].interrupts.pio = ruby_port.master
system.cpu[i].interrupts.int_master = ruby_port.slave
system.cpu[i].interrupts.int_slave = ruby_port.master
system.cpu[i].itb.walker.port = ruby_port.slave
system.cpu[i].dtb.walker.port = ruby_port.slave
else: ### THIS IS WHERE WE END UP ###
MemClass = Simulation.setMemClass(options)
system.membus = CoherentXBar()
system.system_port = system.membus.slave
CacheConfig.config_cache(options, system)
MemConfig.config_mem(options, system)
root = Root(full_system = False, system = system)
Simulation.run(options, root, system, FutureClass)
# Sanity check
if options.fastmem:
if TestCPUClass != AtomicSimpleCPU:
fatal("Fastmem can only be used with atomic CPU!")
if (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].fastmem = True
if options.checker:
test_sys.cpu[i].addCheckerCpu()
test_sys.cpu[i].createThreads()
CacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
if len(bm) == 2:
if buildEnv['TARGET_ISA'] == 'alpha':
drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
elif buildEnv['TARGET_ISA'] == 'mips':
drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
elif buildEnv['TARGET_ISA'] == 'sparc':
drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
elif buildEnv['TARGET_ISA'] == 'x86':
drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1])
elif buildEnv['TARGET_ISA'] == 'arm':
drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
# Create a top-level voltage domain
drive_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage)
def build_test_system(np):
cmdline = cmd_line_template()
if buildEnv['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode,
bm[0],
options.ruby,
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode,
options.num_cpus,
bm[0],
options.ruby,
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(
test_mem_mode,
options.machine_type,
options.num_cpus,
bm[0],
options.dtb_filename,
bare_metal=options.bare_metal,
cmdline=cmdline,
external_memory=options.external_memory_system)
if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
# Set the cache line size for the entire system
test_sys.cache_line_size = options.cacheline_size
# Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage)
# Create a source clock for the system and set the clock period
test_sys.clk_domain = SrcClockDomain(
clock=options.sys_clock, voltage_domain=test_sys.voltage_domain)
# Create a CPU voltage domain
test_sys.cpu_voltage_domain = VoltageDomain()
# Create a source clock for the CPUs and set the clock period
test_sys.cpu_clk_domain = SrcClockDomain(
clock=options.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain)
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
if options.lpae:
test_sys.have_lpae = True
if options.virtualisation:
test_sys.have_virtualization = True
#change the bootloader here
#print "change boot loader"
#print test_sys.boot_loader
test_sys.boot_loader = options.issd_bootloader
#print test_sys.boot_loader
test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain
test_sys.cpu = [
TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
for i in xrange(np)
]
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM()
if options.ruby:
# Check for timing mode because ruby does not support atomic accesses
if not (options.cpu_type == "detailed"
or options.cpu_type == "timing"):
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1)
Ruby.create_system(options, True, test_sys, test_sys.iobus,
test_sys._dma_ports)
# Create a seperate clock domain for Ruby
test_sys.ruby.clk_domain = SrcClockDomain(
clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain)
# Connect the ruby io port to the PIO bus,
# assuming that there is just one such port.
test_sys.iobus.master = test_sys.ruby._io_port.slave
for (i, cpu) in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.clk_domain = test_sys.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] == "x86":
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master
cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
else:
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
elif not options.external_memory_system:
test_sys.iobridge = Bridge(delay='50ns',
ranges=test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
# Sanity check
if options.fastmem:
if TestCPUClass != AtomicSimpleCPU:
fatal("Fastmem can only be used with atomic CPU!")
if (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
if options.simpoint_profile:
if not options.fastmem:
# Atomic CPU checked with fastmem option already
fatal(
"SimPoint generation should be done with atomic cpu and fastmem"
)
if np > 1:
fatal(
"SimPoint generation not supported with more than one CPUs"
)
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].fastmem = True
if options.simpoint_profile:
test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
if options.checker:
test_sys.cpu[i].addCheckerCpu()
test_sys.cpu[i].createThreads()
CacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
return test_sys
def run_system_with_cpu(
process, options, output_dir,
warmup_cpu_class=None,
warmup_instructions=0,
real_cpu_create_function=lambda cpu_id: DerivO3CPU(cpu_id=cpu_id),
):
# Override the -d outdir --outdir option to gem5
m5.options.outdir = output_dir
m5.core.setOutputDir(m5.options.outdir)
m5.stats.reset()
max_tick = options.abs_max_tick
if options.rel_max_tick:
max_tick = options.rel_max_tick
elif options.maxtime:
max_tick = int(options.maxtime * 1000 * 1000 * 1000 * 1000)
eprint("Simulating until tick=%s" % (max_tick))
real_cpus = [real_cpu_create_function(0)]
mem_mode = real_cpus[0].memory_mode()
if warmup_cpu_class:
warmup_cpus = [warmup_cpu_class(cpu_id=0)]
warmup_cpus[0].max_insts_any_thread = warmup_instructions
else:
warmup_cpus = real_cpus
system = System(cpu = warmup_cpus,
mem_mode = mem_mode,
mem_ranges = [AddrRange(options.mem_size)],
cache_line_size = options.cacheline_size)
system.multi_thread = False
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
system.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = system.voltage_domain)
system.cpu_voltage_domain = VoltageDomain()
system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
voltage_domain =
system.cpu_voltage_domain)
system.cache_line_size = options.cacheline_size
if warmup_cpu_class:
for cpu in real_cpus:
cpu.clk_domain = system.cpu_clk_domain
cpu.workload = process
cpu.system = system
cpu.switched_out = True
cpu.createThreads()
system.switch_cpus = real_cpus
for cpu in system.cpu:
cpu.clk_domain = system.cpu_clk_domain
cpu.workload = process
if options.prog_interval:
cpu.progress_interval = options.prog_interval
cpu.createThreads();
MemClass = Simulation.setMemClass(options)
system.membus = SystemXBar()
system.system_port = system.membus.slave
system.cpu[0].connectAllPorts(system.membus)
MemConfig.config_mem(options, system)
root = Root(full_system = False, system = system)
m5.options.outdir = output_dir
m5.instantiate(None) # None == no checkpoint
if warmup_cpu_class:
eprint("Running warmup with warmup CPU class (%d instrs.)" % (warmup_instructions))
eprint("Starting simulation")
exit_event = m5.simulate(max_tick)
if warmup_cpu_class:
max_tick -= m5.curTick()
m5.stats.reset()
debug_print("Finished warmup; running real simulation")
m5.switchCpus(system, real_cpus)
exit_event = m5.simulate(max_tick)
eprint("Done simulation @ tick = %s: %s" % (m5.curTick(), exit_event.getCause()))
m5.stats.dump()
def build_test_system(np):
cmdline = cmd_line_template()
if buildEnv['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby,
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
options.ruby, cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(test_mem_mode, options.machine_type,
options.num_cpus, bm[0], options.dtb_filename,
bare_metal=options.bare_metal,
cmdline=cmdline,
external_memory=options.external_memory_system)
if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
# Set the cache line size for the entire system
test_sys.cache_line_size = options.cacheline_size
# Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
# Create a source clock for the system and set the clock period
test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = test_sys.voltage_domain)
# Create a CPU voltage domain
test_sys.cpu_voltage_domain = VoltageDomain()
# Create a source clock for the CPUs and set the clock period
test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
voltage_domain =
test_sys.cpu_voltage_domain)
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
if options.lpae:
test_sys.have_lpae = True
if options.virtualisation:
test_sys.have_virtualization = True
test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain
test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i,
function_trace=options.enable_trace)
for i in xrange(np)]
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM()
if options.ruby:
# Check for timing mode because ruby does not support atomic accesses
if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1)
Ruby.create_system(options, True, test_sys, test_sys.iobus,
test_sys._dma_ports)
# Create a seperate clock domain for Ruby
test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = test_sys.voltage_domain)
# Connect the ruby io port to the PIO bus,
# assuming that there is just one such port.
test_sys.iobus.master = test_sys.ruby._io_port.slave
for (i, cpu) in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.clk_domain = test_sys.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] == "x86":
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
else:
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
elif not options.external_memory_system:
test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
# Sanity check
if options.fastmem:
if TestCPUClass != AtomicSimpleCPU:
fatal("Fastmem can only be used with atomic CPU!")
if (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
if options.simpoint_profile:
if not options.fastmem:
# Atomic CPU checked with fastmem option already
fatal("SimPoint generation should be done with atomic cpu and fastmem")
if np > 1:
fatal("SimPoint generation not supported with more than one CPUs")
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].fastmem = True
if options.simpoint_profile:
test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
if options.checker:
test_sys.cpu[i].addCheckerCpu()
test_sys.cpu[i].createThreads()
# If elastic tracing is enabled when not restoring from checkpoint and
# when not fast forwarding using the atomic cpu, then check that the
# TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
# passes then attach the elastic trace probe.
# If restoring from checkpoint or fast forwarding, the code that does this for
# FutureCPUClass is in the Simulation module. If the check passes then the
# elastic trace probe is attached to the switch CPUs.
if options.elastic_trace_en and options.checkpoint_restore == None and \
not options.fast_forward:
CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
CacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
return test_sys
def build_test_system(np):
if buildEnv['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
options.ruby)
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(test_mem_mode,
options.machine_type,
bm[0],
options.dtb_filename,
bare_metal=options.bare_metal,
sdcard_image=options.sdcard_image)
if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
# Set the cache line size for the entire system
test_sys.cache_line_size = options.cacheline_size
# Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage)
# Create a source clock for the system and set the clock period
test_sys.clk_domain = SrcClockDomain(
clock=options.sys_clock, voltage_domain=test_sys.voltage_domain)
#Create a clk running contantly at 1.4GHz for L2
test_sys.clk_domain_const = SrcClockDomain(
clock=["1.4GHz"], voltage_domain=test_sys.voltage_domain)
# Create a CPU voltage domain
test_sys.cpu_voltage_domain = VoltageDomain()
# Create a source clock for the CPUs and set the clock period
#test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
# voltage_domain =
# test_sys.cpu_voltage_domain)
#test_sys.cpu_clk_domain = SrcClockDomain(clock = ["3GHz","2GHz","1GHz"],
test_sys.cpu_clk_domain = SrcClockDomain(
clock=[
"1.4GHz", "1.3GHz", "1.2GHz", "1.1GHz", "1GHz", "0.9GHz", "0.8GHz",
"0.7GHz", "0.6GHz", "0.5GHz", "0.4GHz", "0.3GHz", "0.2GHz"
],
voltage_domain=test_sys.cpu_voltage_domain,
domain_id=0)
test_sys.cpu_clk_domain1 = SrcClockDomain(
clock=[
"1.4GHz", "1.3GHz", "1.2GHz", "1.1GHz", "1GHz", "0.9GHz", "0.8GHz",
"0.7GHz", "0.6GHz", "0.5GHz", "0.4GHz", "0.3GHz", "0.2GHz"
],
voltage_domain=test_sys.cpu_voltage_domain,
domain_id=1)
test_sys.cpu_clk_domain2 = SrcClockDomain(
clock=[
"1.4GHz", "1.3GHz", "1.2GHz", "1.1GHz", "1GHz", "0.9GHz", "0.8GHz",
"0.7GHz", "0.6GHz", "0.5GHz", "0.4GHz", "0.3GHz", "0.2GHz"
],
voltage_domain=test_sys.cpu_voltage_domain,
domain_id=2)
test_sys.cpu_clk_domain3 = SrcClockDomain(
clock=[
"1.4GHz", "1.3GHz", "1.2GHz", "1.1GHz", "1GHz", "0.9GHz", "0.8GHz",
"0.7GHz", "0.6GHz", "0.5GHz", "0.4GHz", "0.3GHz", "0.2GHz"
],
voltage_domain=test_sys.cpu_voltage_domain,
domain_id=3)
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
if options.lpae:
test_sys.have_lpae = True
if options.virtualisation:
test_sys.have_virtualization = True
test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain
#test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
# for i in xrange(np)]
test_sys.cpu = [
TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=0,
socket_id=0),
TestCPUClass(clk_domain=test_sys.cpu_clk_domain1,
cpu_id=1,
socket_id=1),
TestCPUClass(clk_domain=test_sys.cpu_clk_domain2,
cpu_id=2,
socket_id=2),
TestCPUClass(clk_domain=test_sys.cpu_clk_domain3,
cpu_id=3,
socket_id=3)
]
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM()
test_sys.dvfs_handler.enable = True
test_sys.dvfs_handler.transform_enable = True # We do want O3 CPU to transform
test_sys.dvfs_handler.domains = [
test_sys.cpu_clk_domain, test_sys.cpu_clk_domain1,
test_sys.cpu_clk_domain2, test_sys.cpu_clk_domain3
]
if options.ruby:
# Check for timing mode because ruby does not support atomic accesses
if not (options.cpu_type == "detailed"
or options.cpu_type == "timing"):
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1)
Ruby.create_system(options, test_sys, test_sys.iobus,
test_sys._dma_ports)
# Create a seperate clock domain for Ruby
test_sys.ruby.clk_domain = SrcClockDomain(
clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain)
for (i, cpu) in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.clk_domain = test_sys.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] == "x86":
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master
cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
test_sys.ruby._cpu_ports[i].access_phys_mem = True
# Create the appropriate memory controllers
# and connect them to the IO bus
test_sys.mem_ctrls = [
TestMemClass(range=r) for r in test_sys.mem_ranges
]
for i in xrange(len(test_sys.mem_ctrls)):
test_sys.mem_ctrls[i].port = test_sys.iobus.master
else:
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
else:
test_sys.iobridge = Bridge(delay='50ns',
ranges=test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
# Sanity check
if options.fastmem:
if TestCPUClass != AtomicSimpleCPU:
fatal("Fastmem can only be used with atomic CPU!")
if (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].fastmem = True
if options.checker:
test_sys.cpu[i].addCheckerCpu()
test_sys.cpu[i].createThreads()
CacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
return test_sys
def build_test_system(np):
if buildEnv['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
options.ruby)
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(test_mem_mode, options.machine_type,
options.num_cpus, bm[0], options.dtb_filename,
bare_metal=options.bare_metal)
if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
# Set the cache line size for the entire system
test_sys.cache_line_size = options.cacheline_size
# Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
# Create a source clock for the system and set the clock period
test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = test_sys.voltage_domain)
# Create a CPU voltage domain
test_sys.cpu_voltage_domain = VoltageDomain()
# Create a source clock for the CPUs and set the clock period
test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
voltage_domain =
test_sys.cpu_voltage_domain)
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
if options.lpae:
test_sys.have_lpae = True
if options.virtualisation:
test_sys.have_virtualization = True
test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain
test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
for i in xrange(np)]
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM()
if options.ruby:
# Check for timing mode because ruby does not support atomic accesses
if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1)
Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports)
# Create a seperate clock domain for Ruby
test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = test_sys.voltage_domain)
for (i, cpu) in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.clk_domain = test_sys.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] == "x86":
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master
cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
test_sys.ruby._cpu_ports[i].access_phys_mem = True
# Create the appropriate memory controllers
# and connect them to the IO bus
test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
for i in xrange(len(test_sys.mem_ctrls)):
test_sys.mem_ctrls[i].port = test_sys.iobus.master
else:
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
else:
test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
# Sanity check
if options.fastmem:
if TestCPUClass != AtomicSimpleCPU:
fatal("Fastmem can only be used with atomic CPU!")
if (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].fastmem = True
if options.checker:
test_sys.cpu[i].addCheckerCpu()
test_sys.cpu[i].createThreads()
BaseCacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
return test_sys
# I/D Cache configuration
for i in xrange(np):
sys0.cpu[i].icache = L1Cache(size='32kB')
sys0.cpu[i].icache.cpu_side = sys0.cpu[i].icache_port
sys0.cpu[i].icache.mem_side = sys0.membus.slave
sys0.cpu[i].dcache = L1Cache(size='32kB')
sys0.cpu[i].dcache.cpu_side = sys0.cpu[i].dcache_port
sys0.cpu[i].dcache.mem_side = sys0.membus.slave
sys0.iocache = IOCache(addr_ranges=sys0.mem_ranges)
sys0.iocache.cpu_side = sys0.iobus.master
sys0.iocache.mem_side = sys0.membus.slave
MemConfig.config_mem(options, sys0)
# Create a top-level voltage domain
sys0.voltage_domain = VoltageDomain(voltage=options.sys_voltage)
# Create a source clock for the system and set the clock period
sys0.clk_domain = SrcClockDomain(clock=options.sys_clock,
voltage_domain=sys0.voltage_domain)
# Hierarchy configuration
root = Root(full_system=True)
root.trace_system = sys0
#-------------------------------------------
#-- Run simulation.
#-------------------------------------------
def build_test_system(np):
cmdline = cmd_line_template()
if buildEnv['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby,
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
options.ruby, cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(test_mem_mode, options.machine_type,
options.num_cpus, bm[0], options.dtb_filename,
bare_metal=options.bare_metal,
cmdline=cmdline,
external_memory=options.external_memory_system)
if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
# Set the cache line size for the entire system
test_sys.cache_line_size = options.cacheline_size
# Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
# Create a source clock for the system and set the clock period
test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = test_sys.voltage_domain)
# Create a CPU voltage domain
test_sys.cpu_voltage_domain = VoltageDomain()
# Create a source clock for the CPUs and set the clock period
test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
voltage_domain =
test_sys.cpu_voltage_domain)
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
print "fs.py 131#: {}".format(test_sys.readfile)
else:
print "fs.py 133#: options.script is None."
if options.lpae:
test_sys.have_lpae = True
if options.virtualisation:
test_sys.have_virtualization = True
test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain
test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
for i in xrange(np)]
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM()
test_sys.gpu = NoMaliGpu(
gpu_type="T760",
ver_maj=0, ver_min=0, ver_status=1,
int_job=118, int_mmu=119, int_gpu=120,
pio_addr=0x2b400000,
pio=test_sys.membus.master)
if options.ruby:
# Check for timing mode because ruby does not support atomic accesses
if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1)
Ruby.create_system(options, True, test_sys, test_sys.iobus,
test_sys._dma_ports)
# Create a seperate clock domain for Ruby
test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = test_sys.voltage_domain)
# Connect the ruby io port to the PIO bus,
# assuming that there is just one such port.
test_sys.iobus.master = test_sys.ruby._io_port.slave
for (i, cpu) in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.clk_domain = test_sys.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] == "x86":
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
else:
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
elif not options.external_memory_system:
test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
# Sanity check
if options.fastmem:
if TestCPUClass != AtomicSimpleCPU:
fatal("Fastmem can only be used with atomic CPU!")
if (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
if options.simpoint_profile:
if not options.fastmem:
# Atomic CPU checked with fastmem option already
fatal("SimPoint generation should be done with atomic cpu and fastmem")
if np > 1:
fatal("SimPoint generation not supported with more than one CPUs")
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].fastmem = True
if options.simpoint_profile:
test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
if options.checker:
test_sys.cpu[i].addCheckerCpu()
test_sys.cpu[i].createThreads()
# If elastic tracing is enabled when not restoring from checkpoint and
# when not fast forwarding using the atomic cpu, then check that the
# TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
# passes then attach the elastic trace probe.
# If restoring from checkpoint or fast forwarding, the code that does this for
# FutureCPUClass is in the Simulation module. If the check passes then the
# elastic trace probe is attached to the switch CPUs.
if options.elastic_trace_en and options.checkpoint_restore == None and \
not options.fast_forward:
CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
CacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
return test_sys
# Sanity check
if options.fastmem:
if TestCPUClass != AtomicSimpleCPU:
fatal("Fastmem can only be used with atomic CPU!")
if (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].fastmem = True
if options.checker:
test_sys.cpu[i].addCheckerCpu()
test_sys.cpu[i].createThreads()
CacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
if len(bm) == 2:
if buildEnv['TARGET_ISA'] == 'alpha':
drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
elif buildEnv['TARGET_ISA'] == 'mips':
drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
elif buildEnv['TARGET_ISA'] == 'sparc':
drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
elif buildEnv['TARGET_ISA'] == 'x86':
drive_sys = makeX86System(drive_mem_mode, np, bm[1])
elif buildEnv['TARGET_ISA'] == 'arm':
drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
# Create a top-level voltage domain
drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
# We are fine with 256 MB memory for now.
mem_range = AddrRange('256MB')
# Start address is 0
system.mem_ranges = [mem_range]
# Do not worry about reserving space for the backing store
system.mmap_using_noreserve = True
# Force a single channel to match the assumptions in the DRAM traffic
# generator
args.mem_channels = 1
args.external_memory_system = 0
args.tlm_memory = 0
args.elastic_trace_en = 0
MemConfig.config_mem(args, system)
# Sanity check for memory controller class.
if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
fatal("This script assumes the memory is a DRAMCtrl subclass")
# There is no point slowing things down by saving any data.
system.mem_ctrls[0].null = True
# Set the address mapping based on input argument
# Default to RoRaBaCoCh
if args.addr_map == 0:
system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh"
elif args.addr_map == 1:
system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh"
else:
def build_test_system(np):
cmdline = cmd_line_template()
if buildEnv['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby,
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
options.ruby, options, cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(test_mem_mode, options.machine_type,
options.num_cpus, bm[0], options.dtb_filename,
options,
bare_metal=options.bare_metal,
cmdline=cmdline)
if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
# Set the cache line size for the entire system
test_sys.cache_line_size = options.cacheline_size
# Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
# Create a source clock for the system and set the clock period
test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = test_sys.voltage_domain)
# Create a clk running contantly at 3GHz for L2
test_sys.clk_domain_const = SrcClockDomain(clock = ["3GHz"],
voltage_domain = test_sys.voltage_domain)
# Create a CPU voltage domain
#test_sys.cpu_voltage_domain = VoltageDomain(voltage = ['1V','0.9V','0.8V'])
test_sys.cpu_voltage_domain = VoltageDomain() # lokeshjindal15
# Create a source clock for the CPUs and set the clock period
# vailable frequency steps: 3.10 GHz, 3.10 GHz, 2.90 GHz, 2.80 GHz, 2.60 GHz, 2.40 GHz, 2.30 GHz, 2.10 GHz, 1.90 GHz, 1.80 GHz, 1.60 GHz, 1.50 GHz, 1.30 GHz, 1.10 GHz, 1000 MHz, 800 MHz
haswell_pstates = ["3.10GHz", "2.90GHz", "2.80GHz", "2.60GHz", "2.40GHz", "2.30GHz", "2.10GHz", "1.90GHz", "1.80GHz", "1.60GHz", "1.50GHz", "1.30GHz", "1.10GHz", "1000MHz", "800MHz"]
test_sys.cpu_clk_domain = SrcClockDomain(clock = haswell_pstates,
voltage_domain =
test_sys.cpu_voltage_domain,
domain_id = 0)
test_sys.cpu_clk_domain1 = SrcClockDomain(clock = haswell_pstates,
voltage_domain =
test_sys.cpu_voltage_domain,
domain_id = 1)
test_sys.cpu_clk_domain2 = SrcClockDomain(clock = haswell_pstates,
voltage_domain =
test_sys.cpu_voltage_domain,
domain_id = 2)
test_sys.cpu_clk_domain3 = SrcClockDomain(clock = haswell_pstates,
voltage_domain =
test_sys.cpu_voltage_domain,
domain_id = 3)
test_sys.dvfs_handler.transition_latency = '40us'
test_sys.dvfs_handler.domains = [test_sys.cpu_clk_domain, test_sys.cpu_clk_domain1, test_sys.cpu_clk_domain2, test_sys.cpu_clk_domain3]
test_sys.dvfs_handler.enable = 1
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
if options.lpae:
test_sys.have_lpae = True
if options.virtualisation:
test_sys.have_virtualization = True
test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain
test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=0, socket_id=0), TestCPUClass(clk_domain=test_sys.cpu_clk_domain1, cpu_id=1, socket_id=1), TestCPUClass(clk_domain=test_sys.cpu_clk_domain2, cpu_id=2, socket_id=2), TestCPUClass(clk_domain=test_sys.cpu_clk_domain3, cpu_id=3, socket_id=3)]
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM()
if options.ruby:
# Check for timing mode because ruby does not support atomic accesses
if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1)
Ruby.create_system(options, True, test_sys, test_sys.iobus,
test_sys._dma_ports)
# Create a seperate clock domain for Ruby
test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = test_sys.voltage_domain)
# Connect the ruby io port to the PIO bus,
# assuming that there is just one such port.
test_sys.iobus.master = test_sys.ruby._io_port.slave
for (i, cpu) in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.clk_domain = test_sys.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] == "x86":
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master
cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
else:
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
else:
test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
# Sanity check
if options.fastmem:
if TestCPUClass != AtomicSimpleCPU:
fatal("Fastmem can only be used with atomic CPU!")
if (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
if options.simpoint_profile:
if not options.fastmem:
# Atomic CPU checked with fastmem option already
fatal("SimPoint generation should be done with atomic cpu and fastmem")
if np > 1:
fatal("SimPoint generation not supported with more than one CPUs")
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].fastmem = True
if options.simpoint_profile:
test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
if options.checker:
test_sys.cpu[i].addCheckerCpu()
test_sys.cpu[i].createThreads()
CacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
return test_sys
def build_test_system(np):
cmdline = cmd_line_template()
if buildEnv['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode,
bm[0],
options.ruby,
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode,
options.num_cpus,
bm[0],
options.ruby,
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(
test_mem_mode,
options.machine_type,
options.num_cpus,
bm[0],
options.dtb_filename,
bare_metal=options.bare_metal,
cmdline=cmdline,
external_memory=options.external_memory_system)
if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
# Set the cache line size for the entire system
test_sys.cache_line_size = options.cacheline_size
# Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage)
# Create a source clock for the system and set the clock period
test_sys.clk_domain = SrcClockDomain(
clock=options.sys_clock, voltage_domain=test_sys.voltage_domain)
# Create a CPU voltage domain
test_sys.cpu_voltage_domain = VoltageDomain()
# Create a source clock for the CPUs and set the clock period
test_sys.cpu_clk_domain = SrcClockDomain(
clock=options.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain)
if options.accel_cfg_file:
config = ConfigParser.SafeConfigParser()
print options.accel_cfg_file
config.read(options.accel_cfg_file)
accels = config.sections()
if not accels:
fatal("No accelerators were specified!")
datapaths = []
for accel in accels:
memory_type = config.get(accel, 'memory_type').lower()
# Accelerators need their own clock domain!
cycleTime = config.getint(accel, "cycle_time")
clock = "%1.3fGHz" % (1 / cycleTime)
clk_domain = SrcClockDomain(
clock=clock, voltage_domain=test_sys.cpu_voltage_domain)
# Set the globally required parameters.
datapath = HybridDatapath(
clk_domain=clk_domain,
benchName=config.get(accel, "bench_name"),
traceFilesFolder=config.get(accel, "trace_files_folder"),
configFileName=config.get(accel, "config_file_name"),
acceleratorName="datapath%d" %
config.getint(accel, "accelerator_id"),
acceleratorId=config.getint(accel, "accelerator_id"),
cycleTime=cycleTime,
useDb=config.getboolean(accel, "use_db"),
experimentName=config.get(accel, "experiment_name"),
enableStatsDump=options.enable_stats_dump,
executeStandalone=(np == 0))
datapath.dmaSetupOverhead = config.getint(accel,
"dma_setup_overhead")
datapath.maxDmaRequests = config.getint(accel, "max_dma_requests")
datapath.multiChannelDMA = config.getboolean(
accel, "dma_multi_channel")
datapath.dmaChunkSize = config.getint(accel, "dma_chunk_size")
datapath.pipelinedDma = config.getboolean(accel, "pipelined_dma")
datapath.ignoreCacheFlush = config.getboolean(
accel, "ignore_cache_flush")
datapath.invalidateOnDmaStore = config.getboolean(
accel, "invalidate_on_dma_store")
if memory_type == "cache":
options.cacheline_size = config.getint(accel, "cache_line_sz")
datapath.cacheSize = config.get(accel, "cache_size")
datapath.cacheBandwidth = config.get(accel, "cache_bandwidth")
datapath.cacheQueueSize = config.get(accel, "cache_queue_size")
datapath.cacheAssoc = config.getint(accel, "cache_assoc")
datapath.cacheHitLatency = config.getint(
accel, "cache_hit_latency")
datapath.cacheLineSize = config.getint(accel, "cache_line_sz")
datapath.cactiCacheConfig = config.get(accel,
"cacti_cache_config")
datapath.tlbEntries = config.getint(accel, "tlb_entries")
datapath.tlbAssoc = config.getint(accel, "tlb_assoc")
datapath.tlbHitLatency = config.getint(accel,
"tlb_hit_latency")
datapath.tlbMissLatency = config.getint(
accel, "tlb_miss_latency")
datapath.tlbCactiConfig = config.get(accel, "cacti_tlb_config")
datapath.tlbPageBytes = config.getint(accel, "tlb_page_size")
datapath.numOutStandingWalks = config.getint(
accel, "tlb_max_outstanding_walks")
datapath.tlbBandwidth = config.getint(accel, "tlb_bandwidth")
if (memory_type != "cache" and memory_type != "spad"):
fatal(
"Aladdin configuration file specified invalid memory type %s for "
"accelerator %s." % (memory_type, accel))
datapaths.append(datapath)
test_sys.datapaths = datapaths
camera = CameraModel(enabled=True,
images_dir="images",
imageBytes=691200)
test_sys.camera = camera
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
if options.lpae:
test_sys.have_lpae = True
if options.virtualisation:
test_sys.have_virtualization = True
test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain
test_sys.cpu = [
TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
for i in xrange(np)
]
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM()
if options.ruby:
# Check for timing mode because ruby does not support atomic accesses
if not (options.cpu_type == "detailed"
or options.cpu_type == "timing"):
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1)
else:
print "Running Ruby with %s CPU model" % options.cpu_type
Ruby.create_system(options, True, test_sys, test_sys.iobus,
test_sys._dma_ports)
# Create a seperate clock domain for Ruby
test_sys.ruby.clk_domain = SrcClockDomain(
clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain)
# Connect the ruby io port to the PIO bus,
# assuming that there is just one such port.
test_sys.iobus.master = test_sys.ruby._io_port.slave
test_sys.camera.pio = test_sys.iobus.master
test_sys.camera.dma = test_sys.iobus.slave
for (i, cpu) in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.clk_domain = test_sys.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] == "x86":
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master
cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
elif buildEnv['TARGET_ISA'] == "arm":
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
else:
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
elif not options.external_memory_system:
test_sys.iobridge = Bridge(delay='50ns',
ranges=test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
test_sys.camera.pio = test_sys.membus.master
test_sys.camera.dma = test_sys.membus.slave
# Sanity check
if options.fastmem:
if TestCPUClass != AtomicSimpleCPU:
fatal("Fastmem can only be used with atomic CPU!")
if (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
if options.simpoint_profile:
if not options.fastmem:
# Atomic CPU checked with fastmem option already
fatal(
"SimPoint generation should be done with atomic cpu and fastmem"
)
if np > 1:
fatal(
"SimPoint generation not supported with more than one CPUs"
)
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].fastmem = True
if options.simpoint_profile:
test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
if options.checker:
test_sys.cpu[i].addCheckerCpu()
test_sys.cpu[i].createThreads()
CacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
return test_sys
def build_test_system(np):
if buildEnv['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
options.ruby)
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(test_mem_mode,
options.machine_type,
bm[0],
options.dtb_filename,
bare_metal=options.bare_metal)
if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
# Set the cache line size for the entire system
test_sys.cache_line_size = options.cacheline_size
# Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage)
# Create a source clock for the system and set the clock period
test_sys.clk_domain = SrcClockDomain(
clock=options.sys_clock, voltage_domain=test_sys.voltage_domain)
# Create a CPU voltage domain
test_sys.cpu_voltage_domain = VoltageDomain()
# Create a source clock for the CPUs and set the clock period
test_sys.cpu_clk_domain = SrcClockDomain(
clock=options.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain)
#my frequencies
# test_sys.cpufreq3GHz = SrcClockDomain(clock = '3GHz',
# voltage_domain = VoltageDomain(voltage = '1.2V'))
#######################################################################################################
#######################################################################################################
test_sys.cpufreq2GHz = SrcClockDomain(
clock='2GHz', voltage_domain=VoltageDomain(voltage='1.1V'))
test_sys.cpufreq1900MHz = SrcClockDomain(
clock='1.9GHz', voltage_domain=VoltageDomain(voltage='1.03V'))
test_sys.cpufreq1800MHz = SrcClockDomain(
clock='1.8GHz', voltage_domain=VoltageDomain(voltage='0.95V'))
test_sys.cpufreq1700MHz = SrcClockDomain(
clock='1.7GHz', voltage_domain=VoltageDomain(voltage='0.92V'))
test_sys.cpufreq1600MHz = SrcClockDomain(
clock='1.6GHz', voltage_domain=VoltageDomain(voltage='0.88V'))
test_sys.cpufreq1500MHz = SrcClockDomain(
clock='1.5GHz', voltage_domain=VoltageDomain(voltage='0.82V'))
test_sys.cpufreq1400MHz = SrcClockDomain(
clock='1.4GHz', voltage_domain=VoltageDomain(voltage='0.8V'))
test_sys.cpufreq1300MHz = SrcClockDomain(
clock='1.3GHz', voltage_domain=VoltageDomain(voltage='0.8V'))
test_sys.cpufreq1200MHz = SrcClockDomain(
clock='1.2GHz', voltage_domain=VoltageDomain(voltage='0.8V'))
test_sys.cpufreq1100MHz = SrcClockDomain(
clock='1.1GHz', voltage_domain=VoltageDomain(voltage='0.8V'))
test_sys.cpufreq1GHz = SrcClockDomain(
clock='1GHz', voltage_domain=VoltageDomain(voltage='0.8V'))
test_sys.cpufreq800MHz = SrcClockDomain(
clock='800MHz', voltage_domain=VoltageDomain(voltage='0.8V'))
test_sys.cpufreq500MHz = SrcClockDomain(
clock='500MHz', voltage_domain=VoltageDomain(voltage='0.8V'))
#######################################################################################################
#######################################################################################################
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
if options.lpae:
test_sys.have_lpae = True
if options.virtualisation:
test_sys.have_virtualization = True
test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain
test_sys.cpu = [
TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
for i in xrange(np)
]
#######################################################################################################
#######################################################################################################
TIMING_CPU = 0
OOO_CPU = 1
#my cpulists###########################################################################################
#######################################################################################################
#######################################################################################################
if TIMING_CPU:
test_sys.FREQ_2GHz = [
TimingSimpleCPU(switched_out=True,
clk_domain=test_sys.cpufreq2GHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_1900MHz = [
TimingSimpleCPU(switched_out=True,
clk_domain=test_sys.cpufreq1900MHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_1800MHz = [
TimingSimpleCPU(switched_out=True,
clk_domain=test_sys.cpufreq1900MHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_1700MHz = [
TimingSimpleCPU(switched_out=True,
clk_domain=test_sys.cpufreq1700MHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_1600MHz = [
TimingSimpleCPU(switched_out=True,
clk_domain=test_sys.cpufreq1600MHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_1500MHz = [
TimingSimpleCPU(switched_out=True,
clk_domain=test_sys.cpufreq1500MHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_1400MHz = [
TimingSimpleCPU(switched_out=True,
clk_domain=test_sys.cpufreq1400MHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_1300MHz = [
TimingSimpleCPU(switched_out=True,
clk_domain=test_sys.cpufreq1300MHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_1200MHz = [
TimingSimpleCPU(switched_out=True,
clk_domain=test_sys.cpufreq1200MHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_1100MHz = [
TimingSimpleCPU(switched_out=True,
clk_domain=test_sys.cpufreq1100MHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_1GHz = [
TimingSimpleCPU(switched_out=True,
clk_domain=test_sys.cpufreq1GHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_800MHz = [
TimingSimpleCPU(switched_out=True,
clk_domain=test_sys.cpufreq800MHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_500MHz = [
TimingSimpleCPU(switched_out=True,
clk_domain=test_sys.cpufreq500MHz,
cpu_id=i) for i in xrange(np)
]
#######################################################################################################
#######################################################################################################
if OOO_CPU:
test_sys.FREQ_2GHz = [
DerivO3CPU(switched_out=True,
clk_domain=test_sys.cpufreq2GHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_1900MHz = [
DerivO3CPU(switched_out=True,
clk_domain=test_sys.cpufreq1900MHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_1800MHz = [
DerivO3CPU(switched_out=True,
clk_domain=test_sys.cpufreq1900MHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_1700MHz = [
DerivO3CPU(switched_out=True,
clk_domain=test_sys.cpufreq1700MHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_1600MHz = [
DerivO3CPU(switched_out=True,
clk_domain=test_sys.cpufreq1600MHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_1500MHz = [
DerivO3CPU(switched_out=True,
clk_domain=test_sys.cpufreq1500MHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_1400MHz = [
DerivO3CPU(switched_out=True,
clk_domain=test_sys.cpufreq1400MHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_1300MHz = [
DerivO3CPU(switched_out=True,
clk_domain=test_sys.cpufreq1300MHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_1200MHz = [
DerivO3CPU(switched_out=True,
clk_domain=test_sys.cpufreq1200MHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_1100MHz = [
DerivO3CPU(switched_out=True,
clk_domain=test_sys.cpufreq1100MHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_1GHz = [
DerivO3CPU(switched_out=True,
clk_domain=test_sys.cpufreq1GHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_800MHz = [
DerivO3CPU(switched_out=True,
clk_domain=test_sys.cpufreq800MHz,
cpu_id=i) for i in xrange(np)
]
test_sys.FREQ_500MHz = [
DerivO3CPU(switched_out=True,
clk_domain=test_sys.cpufreq500MHz,
cpu_id=i) for i in xrange(np)
]
#######################################################################################################
#######################################################################################################
# test_sys.FREQ_2GHz = [DerivO3CPU(switched_out = True,clk_domain=test_sys.cpufreq2GHz, cpu_id=0),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq2GHz, cpu_id=1),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq2GHz, cpu_id=2),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq2GHz, cpu_id=3)]
# test_sys.FREQ_1900MHz = [DerivO3CPU(switched_out = True,clk_domain=test_sys.cpufreq1900MHz, cpu_id=0),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1900MHz, cpu_id=1),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1900MHz, cpu_id=2),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1900MHz, cpu_id=3)]
# test_sys.FREQ_1800MHz = [DerivO3CPU(switched_out = True,clk_domain=test_sys.cpufreq1800MHz, cpu_id=0),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1800MHz, cpu_id=1),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1800MHz, cpu_id=2),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1800MHz, cpu_id=3)]
# test_sys.FREQ_1700MHz = [DerivO3CPU(switched_out = True,clk_domain=test_sys.cpufreq1700MHz, cpu_id=0),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1700MHz, cpu_id=1),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1700MHz, cpu_id=2),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1700MHz, cpu_id=3)]
# test_sys.FREQ_1600MHz = [DerivO3CPU(switched_out = True,clk_domain=test_sys.cpufreq1600MHz, cpu_id=0),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1600MHz, cpu_id=1),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1600MHz, cpu_id=2),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1600MHz, cpu_id=3)]
# test_sys.FREQ_1500MHz = [DerivO3CPU(switched_out = True,clk_domain=test_sys.cpufreq1500MHz, cpu_id=0),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1500MHz, cpu_id=1),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1500MHz, cpu_id=2),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1500MHz, cpu_id=3)]
# test_sys.FREQ_1400MHz = [DerivO3CPU(switched_out = True,clk_domain=test_sys.cpufreq1400MHz, cpu_id=0),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1400MHz, cpu_id=1),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1400MHz, cpu_id=2),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1400MHz, cpu_id=3)]
#
# test_sys.FREQ_1300MHz = [DerivO3CPU(switched_out = True,clk_domain=test_sys.cpufreq1300MHz, cpu_id=0),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1300MHz, cpu_id=1),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1300MHz, cpu_id=2),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1300MHz, cpu_id=3)]
# test_sys.FREQ_1200MHz = [DerivO3CPU(switched_out = True,clk_domain=test_sys.cpufreq1200MHz, cpu_id=0),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1200MHz, cpu_id=1),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1200MHz, cpu_id=2),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1200MHz, cpu_id=3)]
# test_sys.FREQ_1100MHz = [DerivO3CPU(switched_out = True,clk_domain=test_sys.cpufreq1100MHz, cpu_id=0),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1100MHz, cpu_id=1),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1100MHz, cpu_id=2),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1100MHz, cpu_id=3)]
# test_sys.FREQ_1GHz = [DerivO3CPU(switched_out = True,clk_domain=test_sys.cpufreq1GHz, cpu_id=0),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1GHz, cpu_id=1),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1GHz, cpu_id=2),
# DerivO3CPU (switched_out = True,clk_domain=test_sys.cpufreq1GHz, cpu_id=3)]
# test_sys.FREQ_800MHz= [DerivO3CPU(switched_out = True,clk_domain=test_sys.cpufreq800MHz, cpu_id=0),
# DerivO3CPU(switched_out = True,clk_domain=test_sys.cpufreq800MHz, cpu_id=1),
# DerivO3CPU(switched_out = True,clk_domain=test_sys.cpufreq800MHz, cpu_id=2),
# DerivO3CPU(switched_out = True,clk_domain=test_sys.cpufreq800MHz, cpu_id=3)]
# test_sys.FREQ_500MHz= [DerivO3CPU(switched_out = True,clk_domain=test_sys.cpufreq500MHz, cpu_id=0),
# DerivO3CPU(switched_out = True,clk_domain=test_sys.cpufreq500MHz, cpu_id=1),
# DerivO3CPU(switched_out = True,clk_domain=test_sys.cpufreq500MHz, cpu_id=2),
# DerivO3CPU(switched_out = True,clk_domain=test_sys.cpufreq500MHz, cpu_id=3)]
#######################################################################################################
#######################################################################################################
# test_sys.FREQ_2GHz = [TimingSimpleCPU(switched_out = True,clk_domain=test_sys.cpufreq2GHz, cpu_id=0),
# TimingSimpleCPU(switched_out = True,clk_domain=test_sys.cpufreq2GHz, cpu_id=1),
# TimingSimpleCPU(switched_out = True,clk_domain=test_sys.cpufreq2GHz, cpu_id=2),
# TimingSimpleCPU(switched_out = True,clk_domain=test_sys.cpufreq2GHz, cpu_id=3)]
# test_sys.FREQ_1GHz = [TimingSimpleCPU(switched_out = True,clk_domain=test_sys.cpufreq1GHz, cpu_id=0),
# TimingSimpleCPU(switched_out = True,clk_domain=test_sys.cpufreq1GHz, cpu_id=1),
# TimingSimpleCPU(switched_out = True,clk_domain=test_sys.cpufreq1GHz, cpu_id=2),
# TimingSimpleCPU(switched_out = True,clk_domain=test_sys.cpufreq1GHz, cpu_id=3)]
# test_sys.FREQ_500MHz= [TimingSimpleCPU(switched_out = True,clk_domain=test_sys.cpufreq500MHz, cpu_id=0),
# TimingSimpleCPU(switched_out = True,clk_domain=test_sys.cpufreq500MHz, cpu_id=1),
# TimingSimpleCPU(switched_out = True,clk_domain=test_sys.cpufreq500MHz, cpu_id=2),
# TimingSimpleCPU(switched_out = True,clk_domain=test_sys.cpufreq500MHz, cpu_id=3)]
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM()
if options.ruby:
# Check for timing mode because ruby does not support atomic accesses
if not (options.cpu_type == "detailed"
or options.cpu_type == "timing"):
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1)
Ruby.create_system(options, test_sys, test_sys.iobus,
test_sys._dma_ports)
#new code
# system.system_port = system.ruby._sys_port_proxy
# Create a seperate clock domain for Ruby
test_sys.ruby.clk_domain = SrcClockDomain(
clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain)
for (i, cpu) in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.clk_domain = test_sys.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] == "x86":
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master
cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
test_sys.ruby._cpu_ports[i].access_phys_mem = True
for i in range(0, np):
test_sys.FREQ_2GHz[i].clk_domain = test_sys.cpufreq2GHz
test_sys.FREQ_1900MHz[i].clk_domain = test_sys.cpufreq1900MHz
test_sys.FREQ_1800MHz[i].clk_domain = test_sys.cpufreq1800MHz
test_sys.FREQ_1700MHz[i].clk_domain = test_sys.cpufreq1700MHz
test_sys.FREQ_1600MHz[i].clk_domain = test_sys.cpufreq1600MHz
test_sys.FREQ_1500MHz[i].clk_domain = test_sys.cpufreq1500MHz
test_sys.FREQ_1400MHz[i].clk_domain = test_sys.cpufreq1400MHz
test_sys.FREQ_1300MHz[i].clk_domain = test_sys.cpufreq1300MHz
test_sys.FREQ_1200MHz[i].clk_domain = test_sys.cpufreq1200MHz
test_sys.FREQ_1100MHz[i].clk_domain = test_sys.cpufreq1100MHz
test_sys.FREQ_1GHz[i].clk_domain = test_sys.cpufreq1GHz
test_sys.FREQ_800MHz[i].clk_domain = test_sys.cpufreq800MHz
test_sys.FREQ_500MHz[i].clk_domain = test_sys.cpufreq500MHz
# Create the appropriate memory controllers
# and connect them to the IO bus
test_sys.mem_ctrls = [
TestMemClass(range=r) for r in test_sys.mem_ranges
]
for i in xrange(len(test_sys.mem_ctrls)):
test_sys.mem_ctrls[i].port = test_sys.iobus.master
else:
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
else:
test_sys.iobridge = Bridge(delay='50ns',
ranges=test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
# Sanity check
if options.fastmem:
if TestCPUClass != AtomicSimpleCPU:
fatal("Fastmem can only be used with atomic CPU!")
if (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].fastmem = True
if options.checker:
test_sys.cpu[i].addCheckerCpu()
test_sys.cpu[i].createThreads()
CacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
# test_sys.mycpu=DerivO3CPU(switched_out = True)
#used in non ruby test_sys.mycpu1=AtomicSimpleCPU(switched_out = True)
# test_sys.mycpu2=DerivO3CPU(switched_out = True)
# test_sys.mycpu3=TimingSimpleCPU(switched_out = True)
return test_sys
# We are fine with 256 MB memory for now.
mem_range = AddrRange('256MB')
# Start address is 0
system.mem_ranges = [mem_range]
# Do not worry about reserving space for the backing store
system.mmap_using_noreserve = True
# Force a single channel to match the assumptions in the DRAM traffic
# generator
args.mem_channels = 1
args.external_memory_system = 0
args.tlm_memory = 0
args.elastic_trace_en = 0
MemConfig.config_mem(args, system)
# Sanity check for memory controller class.
if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
fatal("This script assumes the memory is a DRAMCtrl subclass")
# There is no point slowing things down by saving any data.
system.mem_ctrls[0].null = True
# Set the address mapping based on input argument
# Default to RoRaBaCoCh
if args.addr_map == 0:
system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh"
elif args.addr_map == 1:
system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh"
else:
