# MiSaSiM MIPS ISA Simulator # Written by Linda and Scott Wills # (c) 2004-2012 Scott & Linda Wills # # Modification for multi-core by Xiao Yu, [email protected] from Logging import LogFactory Logger = LogFactory.getLogger('Memory') class Memory: """Memory Unit.""" def __init__(Self): Self.Data = {} # Data is stored in the granularity of word Self.Cores = [] # To do: should be a list of cache controllers def AddCores(Self, Cores): Self.Cores = Cores def Peek(Self, Address): assert (Address % 4) == 0, 'Memory address not word aligned' if Address in Self.Data: return Self.Data[Address] return 'undefined' def Set(Self, Address, Value): assert (Address % 4) == 0, 'Memory address not word aligned' Self.Data[Address] = Value def Clear(Self): Self.Data.clear()
# MiSaSiM MIPS ISA Simulator # Written by Linda and Scott Wills # (c) 2004-2012 Scott & Linda Wills # Modification for multi-core by Xiao Yu, [email protected] from Logging import LogFactory Logger = LogFactory.getLogger('Core') class Core: Running = 0 Done = 1 Error = 2 STATUS_STRINGS = ['Running', 'Done', 'Error'] def __init__(Self, CoreID, Sim): Self.StartingSP = Sim.StartingSP Self.ReturnIP = Sim.ReturnIP Self.NumCores = Sim.NumCores Self.Regs = {0:0, 29:Self.StartingSP, 31:Self.ReturnIP} Self.SpecRegs = {'Res':False, 'ResAddr':None} Self.CoreID = CoreID Self.Tracer = Sim.Tracer Self.IP = 0 Self.Executor = InstExecutor(Self) Self.Mem = Sim.Mem #To do: should be a cache controller. Self.Status = Self.Running Self.Code = None def Load_Code(Self, Code):
# MiSaSiM MIPS ISA Simulator # Written by Linda and Scott Wills # (c) 2004-2012 Scott & Linda Wills # # Modification for multi-core by Xiao Yu, [email protected] from Logging import LogFactory from Opcodes import * from Parser import * Logger = LogFactory.getLogger('Instructions') class Instruction : def __init__(Self, Opcode, Address) : Self.Address = Address Self.Opcode = Opcode def __repr__(Self) : return '[%04i: %s]' % (Self.Address, Self.Opcode) def Opcode(Self) : return Self.Opcode def Adjust_IP(Self, Executor) : Executor.Inc_IP() # def Log_In_Trace(Self, Result, OldValue) : # Self.Sim.Trace.append((Self, Result, OldValue)) def Has_Dest(Self) :
# (c) 2004-2012 Scott & Linda Wills # # Modification for multi-core by Xiao Yu, [email protected] from os import listdir from random import seed, randint from copy import copy from Core import * from Memory import * from ExecArbitrator import * from Logging import LogFactory from Parser import * from Tracer import * Logger = LogFactory.getLogger('Simulation') class Simulation : def __init__(Self, CodeBase=1000, StackBase=90000, StartingSP=100000, NumCores=2, Tracer=Tracer()): #Self.DataLabels = [] # cached for the benefit of the control flow analyzer #Self.DataBase = Self.DataEnd = 5000 + (randint(0,250) * 4) Self.CodeBase = CodeBase Self.StackBase = StackBase Self.StartingSP = StartingSP Self.ReturnIP = 3000 + (randint(0,250) * 4) Self.Cores = [] Self.Mem = Memory() Self.InitMemImage = {} Self.Tracer = Tracer
# MiSaSiM MIPS ISA Simulator # Written by Linda and Scott Wills # (c) 2004-2012 Scott & Linda Wills # # Modification for multi-core by Xiao Yu, [email protected] from Instructions import * from Opcodes import * from Code import * from Logging import LogFactory Logger = LogFactory.getLogger('Parser') class InstParser: def __init__(Self): Self.Symbols = {} Self.Instructions = [] Self.InitCommands = [] def Tokenize (Self, Line) : """ This routine scans a list of space or comma delimited tokens with comments """ Comment = [] Line = Line.strip() # strip leading and trialing whitespace CN = Line.find('#') # find comment string if CN <> -1 : Comment = [Line[CN:]] # create comment token Line = Line[:CN] # remove comment from line return Line.replace(',', ' ').split() + Comment # tokenize line with whitespace or comma def Parse_Label_Def (Self, String) :
