# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
#------------------------------------------------------------------------------
import common
#------------------------------------------------------------------------------
regs = [
(0x00, 'CR', common.one_bit('swrst')),
(0x04, 'MR', [
('trgen', 1),
('trgsel', 3),
('word', 1),
('sleep', 1),
('fastwkup', 1),
('', 1),
('refresh', 8),
('user_sel', 2),
('', 2),
('tag', 1),
('maxs', 1),
('', 2),
('startup', 6),
('', 2),
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
#------------------------------------------------------------------------------
import common
#------------------------------------------------------------------------------
regs = [
(0x00, 'DSCR', [
('', 9),
('dscr', 23),
]),
(0x08, 'DMA_EN', common.one_bit('dmaen')),
(0x0c, 'DMA_DIS', common.one_bit('dmadis')),
(0x10, 'DMA_SR', common.one_bit('dmasr')),
(0x14, 'DMA_IER', common.one_bit('dmaier')),
(0x18, 'DMA_IDR', common.one_bit('dmaidr')),
(0x1c, 'DMA_IMR', common.one_bit('dmaimr')),
(0x20, 'DMA_ISR', common.one_bit('dmaisr')),
(0x34, 'CR', common.one_bit('reset')),
(0x38, 'MR', [
('enable', 1),
('compare', 1),
('ptype', 2),
('divider', 4),
('', 24),
]),
(0x3c, 'SR'),
(0x0014, 'IDR1', pwm_ints1),
(0x0018, 'IMR1', pwm_ints1),
(0x001c, 'ISR1', pwm_ints1),
(0x0020, 'SCM', [
('sync0', 1),
('sync1', 1),
('sync2', 1),
('sync3', 1),
('', 12),
('updm', 2),
('', 2),
('ptrm', 1),
('ptrcs', 3),
('', 8),
]),
(0x0028, 'SCUC', common.one_bit('updulock')),
(0x002c, 'SCUP', [
('upr', 4),
('uprcnt', 4),
('', 24),
]),
(0x0030, 'SCUPUPD', [
('uprupd', 4),
('', 28),
]),
(0x0034, 'IER2', pwm_ints2),
(0x0038, 'IDR2', pwm_ints2),
(0x003c, 'IMR2', pwm_ints2),
(0x0040, 'ISR2', pwm_ints2),
(0x0044, 'OOV', [
('oovh0', 1),
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
#------------------------------------------------------------------------------
import common
#------------------------------------------------------------------------------
regs = [
(0x00, 'DSCR', [
('', 9),
('dscr', 23),
]),
(0x08, 'DMA_EN', common.one_bit('dmaen')),
(0x0c, 'DMA_DIS', common.one_bit('dmadis')),
(0x10, 'DMA_SR', common.one_bit('dmasr')),
(0x14, 'DMA_IER', common.one_bit('dmaier')),
(0x18, 'DMA_IDR', common.one_bit('dmaidr')),
(0x1c, 'DMA_IMR', common.one_bit('dmaimr')),
(0x20, 'DMA_ISR', common.one_bit('dmaisr')),
(0x34, 'CR', common.one_bit('reset')),
(0x38, 'MR', [
('enable', 1),
('compare', 1),
('ptype', 2),
('divider', 4),
('', 24),
]),
(0x3c, 'SR'),
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
#------------------------------------------------------------------------------
import common
#------------------------------------------------------------------------------
regs = [
(0x00, 'CR', common.one_bit('swrst')),
(0x04, 'MR', [
('selminus', 3),
('', 1),
('selplus', 3),
('', 1),
('acen', 1),
('edgetyp', 2),
('', 1),
('inv', 1),
('selfs', 1),
('fe', 1),
('', 17),
]),
(0x24, 'IER', common.one_bit('ce')),
(0x28, 'IDR', common.one_bit('ce')),
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
#------------------------------------------------------------------------------
import common
#------------------------------------------------------------------------------
regs = [
(0x00, 'CR', common.one_bit('swrst')),
(0x04, 'MR', [
('selminus', 3),
('', 1),
('selplus', 3),
('', 1),
('acen', 1),
('edgetyp', 2),
('', 1),
('inv', 1),
('selfs', 1),
('fe', 1),
('', 17),
]),
(0x24, 'IER', common.one_bit('ce')),
(0x28, 'IDR', common.one_bit('ce')),
(0x0014, 'IDR1', pwm_ints1),
(0x0018, 'IMR1', pwm_ints1),
(0x001c, 'ISR1', pwm_ints1),
(0x0020, 'SCM', [
('sync0', 1),
('sync1', 1),
('sync2', 1),
('sync3', 1),
('', 12),
('updm', 2),
('', 2),
('ptrm', 1),
('ptrcs', 3),
('', 8),
]),
(0x0028, 'SCUC', common.one_bit('updulock')),
(0x002c, 'SCUP', [
('upr', 4),
('uprcnt', 4),
('', 24),
]),
(0x0030, 'SCUPUPD', [
('uprupd', 4),
('', 28),
]),
(0x0034, 'IER2', pwm_ints2),
(0x0038, 'IDR2', pwm_ints2),
(0x003c, 'IMR2', pwm_ints2),
(0x0040, 'ISR2', pwm_ints2),
(0x0044, 'OOV', [
('oovh0', 1),
('', 13),
]),
(0x0070, 'FSMR',
[('fstt%d' % i, 1) for i in range(16)] + [
('rttal', 1),
('rtcal', 1),
('usbal', 1),
('', 2),
('flpm', 2),
('', 9),
]),
(0x0074, 'FSPR',
[('fstp%d' % i, 1) for i in range(16)] + [
('', 16)
]),
(0x0078, 'FOCR', common.one_bit('foclr')),
(0x00e4, 'WPMR', common.wpmr),
(0x00e8, 'WPSR', common.wpsr),
(0x0100, 'PCER1', common.pid1),
(0x0104, 'PCDR1', common.pid1),
(0x0108, 'PCSR1', common.pid1),
(0x0110, 'OCR', [
('cal4', 7),
('sel4', 1),
('cal8', 7),
('sel8', 1),
('cal12', 7),
('sel12', 1),
('', 8),
]),
]
('', 5),
('moscsels', 1),
('moscrcs', 1),
('cfdev', 1),
('', 13),
]),
(0x0070, 'FSMR', [('fstt%d' % i, 1) for i in range(16)] + [
('rttal', 1),
('rtcal', 1),
('usbal', 1),
('', 2),
('flpm', 2),
('', 9),
]),
(0x0074, 'FSPR', [('fstp%d' % i, 1) for i in range(16)] + [('', 16)]),
(0x0078, 'FOCR', common.one_bit('foclr')),
(0x00e4, 'WPMR', common.wpmr),
(0x00e8, 'WPSR', common.wpsr),
(0x0100, 'PCER1', common.pid1),
(0x0104, 'PCDR1', common.pid1),
(0x0108, 'PCSR1', common.pid1),
(0x0110, 'OCR', [
('cal4', 7),
('sel4', 1),
('cal8', 7),
('sel8', 1),
('cal12', 7),
('sel12', 1),
('', 8),
]),
]
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
#------------------------------------------------------------------------------
import common
#------------------------------------------------------------------------------
regs = [
(0x00, 'CR', common.one_bit('swrst')),
(0x04, 'MR', [
('trgen', 1),
('trgsel', 3),
('word', 1),
('sleep', 1),
('fastwkup', 1),
('', 1),
('refresh', 8),
('user_sel', 2),
('', 2),
('tag', 1),
('maxs', 1),
('', 2),
('startup', 6),
('', 2),
