def test_directed(sim_cls):
drv(t=Uint[4], seq=[0, 1, 2, 3, 4, 5, 6, 7, 8]) \
| unary(sim_cls=sim_cls) \
| check(ref=[0x00, 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff])
sim()
def fir_sim(impl, t_b, seq, do_cosim, target='build/fir'):
# get 'b' factors
b = firwin(8, [0.05, 0.95], width=0.05, pass_zero=False)
b_fixp = [t_b(i) for i in b]
# get result
res = np.convolve(seq, b)
# saturate the results value to filter output type if needed
for i, r in enumerate(res):
res[i] = fixp_sat(t_b, r)
# driving
drv(t=t_b, seq=seq) \
| impl(b=b_fixp) \
| Float \
| check(ref=res[:len(seq)], cmp=fir_compare)
# optionally generate HDL code do co-simulation in verilator
if do_cosim:
cosim(f'{impl}', 'verilator', outdir=target, timeout=1000)
# simulation start
sim(target, check_activity=False)
return res
def test_uint(sim_cls):
res = drv(t=Uint[8], seq=[0xa1, 0xa2, 0xa3, 0xa4]) >> 4
assert res.dtype == Uint[4]
res | check(ref=[0xa] * 4)
find('/shr').params['sim_cls'] = sim_cls
sim()
def test_int_logical(sim_cls):
inp = drv(t=Int[9], seq=[-0xa1, -0xa2, -0xa3, -0xa4])
res = (inp >> Uint) >> 4
res | check(ref=[(-0xa1 & 0x1ff) >> 4] * 4)
find('/shr').params['sim_cls'] = sim_cls
sim()
def test_int(sim_cls):
res = drv(t=Int[9], seq=[-0xa1, -0xa2, -0xa3, -0xa4]) >> 4
assert res.dtype == Int[5]
res | check(ref=[-0xb] * 4)
find('/shr').params['sim_cls'] = sim_cls
sim()
def test_uint(cosim_cls):
res = drv(t=Uint[4], seq=[0xa, 0xb, 0xc, 0xd]) << 4
assert res.dtype == Uint[8]
res | check(ref=[0xa0, 0xb0, 0xc0, 0xd0])
find('/shl').params['sim_cls'] = cosim_cls
sim()
def test_int(sim_cls):
res = drv(t=Int[5], seq=[-0xa, -0xb, -0xc, -0xd]) << 4
assert res.dtype == Int[9]
res | check(ref=[-0xa0, -0xb0, -0xc0, -0xd0])
find('/shl').params['sim_cls'] = sim_cls
sim()
def test_fir_direct(tmpdir, impl):
b = firwin(8, [0.05, 0.95], width=0.05, pass_zero=False)
t_b = Fixp[1, 15]
b_fixp = [t_b(i) for i in b]
x = np.random.random(size=(10, ))
res = np.convolve(x, b)
drv(t=t_b, seq=x) \
| impl(b=b_fixp) \
| Float \
| check(ref=res[:len(x)], cmp=lambda x, y: abs(x-y) < 1e-3)
sim(tmpdir, check_activity=False)
def iir_sim(impl,
t_coef,
t_in,
t_out,
seq,
target='build/iir',
do_cosim=False):
# create SOS referent filter and factors
sos = signal.butter(N=5,
Wn=30000 / 100000,
btype='lowpass',
analog=False,
output='sos')
# get a,b coefficient from the created filter
a, b = [], []
for s in sos:
b.append(list(s[0:3]))
a.append(list(s[3:]))
# convert coefficient to wanted Fixp type
b = [[t_coef(coef) for coef in section] for section in b]
a = [[t_coef(coef) for coef in section] for section in a]
log.debug(f'Generated B coeff: {b}')
log.debug(f'Generated A coeff: {a}')
gain = [t_in(1)] * len(b)
ref = signal.sosfilt(sos, seq)
# fp_ref = [float(r) for r in ref]
# saturate the results value to filter output type if needed
for i, r in enumerate(ref):
ref[i] = fixp_sat(t_out, float(r))
log.debug(f'Generated sequence: {seq}')
log.debug(f'Refferenc result: {ref}')
drv(t=t_in, seq=seq) \
| impl(a=a, b=b, gain=gain, ogain=t_in(1)) \
| Float \
| check(ref=ref[:len(seq)], cmp=iir_compare)
# optionally generate HDL code do co-simulation in verilator
if do_cosim:
cosim(f'{impl}', 'verilator', outdir=target, timeout=1000)
sim(target, check_activity=False)
return ref
def test_iir_direct(tmpdir, impl, seed, do_cosim):
reg['sim/rand_seed'] = seed
random.seed(reg['sim/rand_seed'])
log.info(
f'Running test_fir_direct tmpdir: {tmpdir}, impl: {impl}, seed: {seed}'
)
reg['sim/clk_freq'] = 100000
t = list(range(reg['sim/clk_freq']))[0:100]
fs = reg['sim/clk_freq']
f1 = 1000
f2 = 70000
seq = []
for n in t:
seq.append(1 * sin(2 * pi * f1 / fs * n) +
0.1 * sin(2 * pi * f2 / fs * n))
sos = signal.butter(N=5,
Wn=30000 / 100000,
btype='lowpass',
analog=False,
output='sos')
a, b = [], []
for s in sos:
b.append(list(s[0:3]))
a.append(list(s[3:]))
t_coef = Fixp[5, 32]
b = [[t_coef(coef) for coef in section] for section in b]
a = [[t_coef(coef) for coef in section] for section in a]
gain = [Fixp[2, 23](1)] * len(b)
ref = signal.sosfilt(sos, seq)
fp_ref = [float(r) for r in ref]
log.debug(f'Generated sequence: {seq}')
drv(t=Fixp[5, 24], seq=seq) \
| impl(a=a, b=b, gain=gain, ogain=Fixp[5, 24](1)) \
| Float \
| check(ref=fp_ref[:len(seq)], cmp=lambda x, y: abs(x - y) < 1e-3)
if do_cosim:
cosim(f'{impl}', 'verilator', outdir=tmpdir, timeout=1000)
sim(tmpdir, check_activity=False)
def test_iir_direct(tmpdir, impl):
config['sim/clk_freq'] = 100000
t = list(range(config['sim/clk_freq']))[0:100]
fs = config['sim/clk_freq']
f1 = 1000
f2 = 70000
seq = []
for n in t:
seq.append(1 * sin(2 * pi * f1 / fs * n) +
0.1 * sin(2 * pi * f2 / fs * n))
sos = signal.butter(N=5,
Wn=30000 / 100000,
btype='lowpass',
analog=False,
output='sos')
a, b = [], []
for s in sos:
b.append(list(s[0:3]))
a.append(list(s[3:]))
t_coef = Fixp[2, 32]
b = [[t_coef(coef) for coef in section] for section in b]
a = [[t_coef(coef) for coef in section] for section in a]
gain = [Fixp[1, 23](1)] * len(b)
ref = signal.sosfilt(sos, seq)
fp_ref = [float(r) for r in ref]
drv(t=Fixp[5, 24], seq=seq) \
| impl(a=a,b=b, gain=gain, ogain=1) \
| Float \
| check(ref=fp_ref[:len(seq)], cmp=lambda x, y: abs(x-y) < 1e-3)
sim(tmpdir, check_activity=False)
from pygears.lib import drv, check, rng, flatten, decouple from pygears.typing import Uint rng_vals = drv(t=Uint[4], seq=[6]) | rng | flatten rng_vals_incr = (rng_vals | decouple) + 1 rng_vals_incr | check(ref=[1, 2, 3, 4, 5, 6])
from pygears.lib import qdeal, check, drv from pygears.typing import Uint, Queue seq = [[1, 2], [3, 4], [5, 6], [7, 8]] din = drv(t=Queue[Uint[4], 2], seq=[seq]) do1, do2 = din | qdeal(num=2, lvl=1) do1 | check(ref=[[1, 2], [5, 6]]) do2 | check(ref=[[3, 4], [7, 8]])
from pygears.lib import drv, check, chop
from pygears.typing import Uint, Queue
drv(t=Queue[Uint[4]], seq=[list(range(10))]) \
| chop(size=4) \
| check(ref=[list(range(4)), list(range(4, 8)), list(range(8, 10))])
from pygears.lib import check, drv, flatten
from pygears.typing import Uint, Queue
seq = [[[0, 1], [10, 11]], [[100, 101], [110, 111]]]
ref = [[0, 1, 10, 11], [100, 101, 110, 111]]
drv(t=Queue[Uint[8], 3], seq=[seq]) \
| flatten \
| check(ref=[ref])
from pygears.lib import drv, check from pygears.typing import Uint a = drv(t=Uint[4], seq=[1, 2, 3, 4, 5]) b = drv(t=Uint[4], seq=[4, 4, 4, 4, 4]) (a > b) | check(ref=[False, False, False, False, True])
from pygears.lib import qcnt, check, drv
from pygears.typing import Uint, Queue
drv(t=Queue[Uint[4]], seq=[[1, 2, 3, 4, 5]]) \
| qcnt \
| check(ref=[5])
from pygears.lib import drv, check from pygears.typing import Uint a = drv(t=Uint[4], seq=[0, 1, 2]) b = drv(t=Uint[4], seq=[0, 1, 2]) (a + b) | check(ref=[0, 2, 4])
# generate random inputs
x = np.random.random(size=(10, ))
# calculated expected outputs
ref = np.convolve(x, b_coef)
# saturate the results value to filter output type if needed
for i, r in enumerate(ref):
ref[i] = fixp_sat(b_coef_type, float(r))
try:
if test_sel == 0:
drv(t=b_coef_type, seq=x) \
| fir_direct(b=b_coef_fixp) \
| Float \
| check(ref=ref[:len(x)], cmp=lambda x, y: abs(x-y) < 1e-3)
if enable_svgen:
cosim('fir_direct',
'verilator',
outdir='../../outputs/fir/rtl',
timeout=1000)
else:
drv(t=b_coef_type, seq=x) \
| fir_transposed(b=b_coef_fixp) \
| Float \
| check(ref=ref[:len(x)], cmp=lambda x, y: abs(x-y) < 1e-3)
if enable_svgen:
cosim('fir_transposed',
'verilator',
from pygears.lib import drv, check, cart from pygears.typing import Queue, Uint op1 = drv(t=Queue[Uint[5]], seq=[[10, 11, 12], [20, 21, 22]]) op2 = drv(t=Uint[1], seq=[0, 1]) cart(op1, op2) | check(ref=[[(10, 0), (11, 0), (12, 0)], [(20, 1), (21, 1), (22, 1)]])
from pygears.lib import replicate, check, drv
from pygears.typing import Uint
drv(t=Uint[4], seq=[5]) \
| replicate(4) \
| check(ref=[[5, 5, 5, 5]])
from pygears import datagear
from pygears.lib import filt, drv, check
from pygears.typing import Queue, Uint, Bool
@datagear
def even(x: Uint) -> Bool:
return not x[0]
drv(t=Queue[Uint[8]], seq=[[0, 1, 3, 5, 7, 9]]) \
| filt(f=even) \
| check(ref=[[0]])
from pygears.lib import group, check, drv
from pygears.typing import Uint
size = drv(t=Uint[3], seq=[3, 4])
drv(t=Uint[4], seq=[1, 2, 3, 4, 5, 6, 7]) \
| group(size=size) \
| check(ref=[[1, 2, 3], [4, 5, 6, 7]])
from pygears.lib import drv, check from pygears.typing import Uint a = drv(t=Uint[4], seq=[0, 2, 4, 6, 8]) (a % 3) | check(ref=[0, 2, 1, 0, 2])
def test_sin_signed(sim_cls):
drv(t=Fixp[2, 16], seq=[math.pi/12*i for i in range(-6, 5)]) \
| funclut(f=math.sin, sim_cls=sim_cls) \
| check(ref=[math.sin(math.pi/12*i) for i in range(-6, 5)], cmp=lambda x, y: abs(x-y) <= 1)
sim()
from pygears.lib import check, mux, drv
from pygears.typing import Uint
ctrl = drv(t=Uint[2], seq=[0, 1, 2, 0, 1, 2])
a = drv(t=Uint[4], seq=[10, 11])
b = drv(t=Uint[5], seq=[20, 21])
c = drv(t=Uint[6], seq=[30, 31])
mux(ctrl, a, b, c) \
| check(ref=[(10, 0), (20, 1), (30, 2), (11, 0), (21, 1), (31, 2)])
def test_sqrt(sim_cls):
drv(t=Ufixp[8, 8], seq=[0, 4, 64, 121]) \
| funclut(f=math.sqrt, precision=4, sim_cls=sim_cls) \
| check(ref=[0, 2, 8, 11])
sim()
from pygears.lib import reduce, drv, check
from pygears.typing import Queue, Uint
(drv(t=Queue[Uint[8]], seq=[[0, 1, 0, 1, 0, 1, 0]]),
drv(t=Uint[8], seq=[1])) \
| reduce(f=lambda x, y: (x << 1) | y) \
| check(ref=[0xaa])
from pygears.lib import qcnt, check, drv
from pygears.typing import Uint, Queue
drv(t=Queue[Uint[4]], seq=[[1, 2, 3, 4, 5]]) \
| qcnt(running=True) \
| check(ref=[[1, 2, 3, 4, 5]])
from pygears.lib import drv, check, czip from pygears.typing import Queue, Uint x = drv(t=Queue[Uint[5]], seq=[[10, 11], [13, 14, 15]]) y = drv(t=Queue[Uint[5]], seq=[[20, 21, 22], [23, 24]]) czip(x, y) | check(ref=[[(10, 20), (11, 22)], [(13, 23), (15, 24)]])
