def _file_content_hash(file_name, encoding, database=None, newline=None):
"""
Returns the file content as well as the hash of the content
Use the database to keep a persistent cache of the last content
hash. If the file modification date has not changed assume the
hash is the same and do not re-open the file.
"""
if database is None:
content = read_file(file_name, encoding=encoding, newline=newline)
return content, hash_string(content)
key = ("cached._file_content_hash(%s, newline=%s)" % (file_name, newline)).encode()
if key not in database:
content = read_file(file_name, encoding=encoding, newline=newline)
content_hash = hash_string(content)
timestamp = os.path.getmtime(file_name)
database[key] = timestamp, content_hash
return content, content_hash
timestamp = os.path.getmtime(file_name)
last_timestamp, last_content_hash = database[key]
if timestamp != last_timestamp:
content = read_file(file_name, encoding=encoding, newline=newline)
content_hash = hash_string(content)
database[key] = timestamp, content_hash
return content, content_hash
return None, last_content_hash
def _file_content_hash(file_name, encoding, database=None, newline=None):
"""
Returns the file content as well as the hash of the content
Use the database to keep a persistent cache of the last content
hash. If the file modification date has not changed assume the
hash is the same and do not re-open the file.
"""
if database is None:
content = read_file(file_name, encoding=encoding, newline=newline)
return content, hash_string(content)
key = ("cached._file_content_hash(%s, newline=%s)" %
(file_name, newline)).encode()
if key not in database:
content = read_file(file_name, encoding=encoding, newline=newline)
content_hash = hash_string(content)
timestamp = os.path.getmtime(file_name)
database[key] = timestamp, content_hash
return content, content_hash
timestamp = os.path.getmtime(file_name)
last_timestamp, last_content_hash = database[key]
if timestamp != last_timestamp:
content = read_file(file_name, encoding=encoding, newline=newline)
content_hash = hash_string(content)
database[key] = timestamp, content_hash
return content, content_hash
return None, last_content_hash
def cached(key, function, file_name, encoding, database=None, newline=None):
"""
Call function with file content if an update is needed
"""
if database is None:
# Without a database just return the function of the contents
content = read_file(file_name, encoding=encoding, newline=newline)
return function(content)
function_key = ("%s(%s, newline=%s)" % (key, file_name, newline)).encode()
content, content_hash = _file_content_hash(file_name, encoding, database, newline=newline)
if function_key not in database:
# We do not have a cached version of this computation
# recompute and update database
if content is None:
content = read_file(file_name, encoding=encoding, newline=newline)
result = function(content)
database[function_key] = content_hash, result
return result
old_content_hash, old_result = database[function_key]
if old_content_hash == content_hash:
return old_result
# Content hash differs, recompute and update database
if content is None:
content = read_file(file_name, encoding=encoding, newline=newline)
result = function(content)
database[function_key] = content_hash, result
return result
def cached(key, function, file_name, encoding, database=None, newline=None):
"""
Call function with file content if an update is needed
"""
if database is None:
# Without a database just return the function of the contents
content = read_file(file_name, encoding=encoding, newline=newline)
return function(content)
function_key = ("%s(%s, newline=%s)" % (key, file_name, newline)).encode()
content, content_hash = _file_content_hash(file_name,
encoding,
database,
newline=newline)
if function_key not in database:
# We do not have a cached version of this computation
# recompute and update database
if content is None:
content = read_file(file_name, encoding=encoding, newline=newline)
result = function(content)
database[function_key] = content_hash, result
return result
old_content_hash, old_result = database[function_key]
if old_content_hash == content_hash:
return old_result
# Content hash differs, recompute and update database
if content is None:
content = read_file(file_name, encoding=encoding, newline=newline)
result = function(content)
database[function_key] = content_hash, result
return result
def test_simulate_extra_flags(self, run_command, find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path)
config = make_config(
sim_options={"incisive.irun_sim_flags": ["custom", "flags"]})
self.assertTrue(
simif.simulate("sim_output_path", "test_suite_name", config))
elaborate_args_file = join('sim_output_path', 'irun_elaborate.args')
simulate_args_file = join('sim_output_path', 'irun_simulate.args')
run_command.assert_has_calls([
mock.call(
[join('prefix', 'irun'), '-f',
basename(elaborate_args_file)],
cwd=dirname(elaborate_args_file),
env=simif.get_env()),
mock.call(
[join('prefix', 'irun'), '-f',
basename(simulate_args_file)],
cwd=dirname(simulate_args_file),
env=simif.get_env()),
])
args = read_file(elaborate_args_file).splitlines()
self.assertIn("custom", args)
self.assertIn("flags", args)
args = read_file(simulate_args_file).splitlines()
self.assertIn("custom", args)
self.assertIn("flags", args)
def test_simulate_extra_flags(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
config = SimConfig(options={"incisive.irun_sim_flags": ["custom", "flags"]})
self.assertTrue(simif.simulate("sim_output_path", "lib", "modulename", None, config))
elaborate_args_file = join("sim_output_path", "irun_elaborate.args")
simulate_args_file = join("sim_output_path", "irun_simulate.args")
run_command.assert_has_calls(
[
mock.call(
[join("prefix", "irun"), "-f", basename(elaborate_args_file)], cwd=dirname(elaborate_args_file)
),
mock.call(
[join("prefix", "irun"), "-f", basename(simulate_args_file)], cwd=dirname(simulate_args_file)
),
]
)
args = read_file(elaborate_args_file).splitlines()
self.assertIn("custom", args)
self.assertIn("flags", args)
args = read_file(simulate_args_file).splitlines()
self.assertIn("custom", args)
self.assertIn("flags", args)
def test_simulate_gui(self, run_command, find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path,
gui=True)
with mock.patch("vunit.simulator_interface.check_output",
autospec=True,
return_value="") as dummy:
simif.compile_project(project)
config = make_config()
self.assertTrue(
simif.simulate("sim_output_path", "test_suite_name", config))
elaborate_args_file = join('sim_output_path', 'irun_elaborate.args')
simulate_args_file = join('sim_output_path', 'irun_simulate.args')
run_command.assert_has_calls([
mock.call(
[join('prefix', 'irun'), '-f',
basename(elaborate_args_file)],
cwd=dirname(elaborate_args_file),
env=simif.get_env()),
mock.call(
[join('prefix', 'irun'), '-f',
basename(simulate_args_file)],
cwd=dirname(simulate_args_file),
env=simif.get_env()),
])
self.assertEqual(
read_file(elaborate_args_file).splitlines(), [
'-elaborate', '-nocopyright', '-licqueue', '-errormax 10',
'-nowarn WRMNZD', '-nowarn DLCPTH', '-nowarn DLCVAR',
'-ncerror EVBBOL', '-ncerror EVBSTR', '-ncerror EVBNAT',
'-work work',
'-nclibdirname "%s"' % join(self.output_path, "libraries"),
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "sim_output_path/irun_elaborate.log"', '-quiet',
'-reflib "lib_path"', '-access +rwc', '-gui',
'-top lib.ent:arch'
])
self.assertEqual(
read_file(simulate_args_file).splitlines(), [
'-nocopyright', '-licqueue', '-errormax 10', '-nowarn WRMNZD',
'-nowarn DLCPTH', '-nowarn DLCVAR', '-ncerror EVBBOL',
'-ncerror EVBSTR', '-ncerror EVBNAT', '-work work',
'-nclibdirname "%s"' % join(self.output_path, "libraries"),
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "sim_output_path/irun_simulate.log"', '-quiet',
'-reflib "lib_path"', '-access +rwc', '-gui',
'-top lib.ent:arch'
])
def test_compile_project_system_verilog(self, check_output,
find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.sv", "")
project.add_source_file("file.sv", "lib", file_type="systemverilog")
simif.compile_project(project)
args_file = str(
Path(self.output_path) / "irun_compile_verilog_file_lib.args")
check_output.assert_called_once_with(
[str(Path("prefix") / "irun"), "-f", args_file],
env=simif.get_env())
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn UEXPSC",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-work work",
'-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"),
'-log "%s"' % str(
Path(self.output_path) /
"irun_compile_verilog_file_lib.log"),
"-quiet",
'-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
'-nclibdirname "."',
"-makelib lib",
'"file.sv"',
"-endlib",
],
)
self.assertEqual(
read_file(str(Path(self.output_path) / "cds.lib")),
"""\
## cds.lib: Defines the locations of compiled libraries.
softinclude cds_root_irun/tools/inca/files/cds.lib
# needed for referencing the library 'basic' for cells 'cds_alias', 'cds_thru' etc. in analog models:
# NOTE: 'virtuoso' executable not found!
# define basic ".../tools/dfII/etc/cdslib/basic"
define lib "lib_path"
define work "%s/libraries/work"
""" % self.output_path,
)
def generate_codecs(input_package_design_unit, codec_package_name, # pylint: disable=too-many-arguments
used_packages, output_file, debug):
"""This function generates codecs for the types in the input package and compile the result into
codec_package_name. used_packages is a list specifying what to include into the result package
other than the input package. A used package on the format 'lib.pkg' will result in a library and
a use statement. A used package on the format 'pkg' is assumed to be located in work. output_file
is where the resulting codec package is written. The debug codecs are generated when debug is set True."""
# The design unit doesn't contain the package so it must be found first in the source file. This file
# may contain other packages
code = read_file(input_package_design_unit.source_file.name)
package = CodecVHDLPackage.find_named_package(code, input_package_design_unit.name)
if package is None:
raise KeyError(input_package_design_unit.name)
# Get all function declarations and definitions derived from the package type definitions
declarations, definitions = package.generate_codecs_and_support_functions(debug)
# Create extra use clauses
use_clauses = ''
libraries = []
for used_package in used_packages if used_packages is not None else []:
if '.' in used_package:
if used_package.split('.')[0] not in libraries:
libraries.append(used_package.split('.')[0])
use_clauses += 'use %s.all;\n' % used_package
else:
use_clauses += 'use work.%s.all;\n' % used_package
if len(libraries) != 0:
use_clauses = 'library ' + ';\nlibrary '.join(libraries) + ';\n' + use_clauses
# Assemble everything and write to output file
codec_package_template = Template("""\
library vunit_lib;
use vunit_lib.string_ops.all;
context vunit_lib.com_context;
use std.textio.all;
use work.$package_name.all;
$use_clauses
package $codec_package_name is
$declarations
end package $codec_package_name;
package body $codec_package_name is
$definitions
end package body $codec_package_name;
""")
codec_package = codec_package_template.substitute(
declarations=declarations,
definitions=definitions,
package_name=package.identifier,
codec_package_name=codec_package_name,
use_clauses=use_clauses)
write_file(output_file, codec_package)
def test_compile_project_vhdl_2002(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002")
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
check_output.assert_called_once_with(
[join('prefix', 'irun'), '-f', args_file],
env=simif.get_env())
self.assertEqual(read_file(args_file).splitlines(),
['-compile',
'-nocopyright',
'-licqueue',
'-nowarn DLCPTH',
'-nowarn DLCVAR',
'-v200x -extv200x',
'-work work',
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"),
'-quiet',
'-nclibdirname ""',
'-makelib lib_path',
'"file.vhd"',
'-endlib'])
def test_compile_project_verilog_hdlvar(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, hdlvar="custom_hdlvar")
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines=dict(defname="defval"))
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn UEXPSC",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-work work",
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-hdlvar "custom_hdlvar"',
'-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
"-quiet",
'-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
"-define defname=defval",
'-nclibdirname ""',
"-makelib lib",
'"file.v"',
"-endlib",
],
)
def test_simulate_generics_and_parameters(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
config = make_config(verilog=True,
generics={"genstr": "genval",
"genint": 1,
"genbool": True})
self.assertTrue(simif.simulate("suite_output_path", "test_suite_name", config))
elaborate_args_file = join('suite_output_path', simif.name, 'irun_elaborate.args')
simulate_args_file = join('suite_output_path', simif.name, 'irun_simulate.args')
run_command.assert_has_calls([
mock.call([join('prefix', 'irun'), '-f', basename(elaborate_args_file)],
cwd=dirname(elaborate_args_file),
env=simif.get_env()),
mock.call([join('prefix', 'irun'), '-f', basename(simulate_args_file)],
cwd=dirname(simulate_args_file),
env=simif.get_env()),
])
for args_file in [elaborate_args_file, simulate_args_file]:
args = read_file(args_file).splitlines()
self.assertIn('-gpg "modulename.genstr => \\"genval\\""', args)
self.assertIn('-gpg "modulename.genint => 1"', args)
self.assertIn('-gpg "modulename.genbool => \\"True\\""', args)
def test_compile_project_verilog_hdlvar(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, hdlvar="custom_hdlvar")
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines=dict(defname="defval"))
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
check_output.assert_called_once_with(
[join('prefix', 'irun'), '-f', args_file],
env=simif.get_env())
self.assertEqual(read_file(args_file).splitlines(),
['-compile',
'-nocopyright',
'-licqueue',
'-nowarn UEXPSC',
'-nowarn DLCPTH',
'-nowarn DLCVAR',
'-work work',
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-hdlvar "custom_hdlvar"',
'-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
'-quiet',
'-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
'-define defname=defval',
'-nclibdirname ""',
'-makelib lib',
'"file.v"',
'-endlib'])
def _parse(self, entity, architecture_name, verilog):
"""
Parse file for run strings and pragmas
"""
scope = create_scope(entity.library_name, entity.name)
other_file = self._cfg.file_to_scan_for_tests(scope)
if other_file is not None:
file_name = other_file
verilog = file_type_of(other_file) == "verilog"
elif verilog:
file_name = entity.file_name
else:
file_name = entity.architecture_names[architecture_name]
code = ostools.read_file(file_name)
pragmas = self.find_pragmas(code, file_name)
# @TODO use presence of runner_cfg as tb_filter instead of tb_*
has_runner_cfg = verilog or ("runner_cfg" in entity.generic_names)
if has_runner_cfg:
run_strings = self.find_run_strings(code, file_name, verilog)
else:
run_strings = []
return pragmas, run_strings
def _parse(self, entity, architecture_name, verilog):
"""
Parse file for run strings and pragmas
"""
scope = create_scope(entity.library_name, entity.name)
other_file = self._cfg.file_to_scan_for_tests(scope)
if other_file is not None:
file_name = other_file
verilog = file_type_of(other_file) == "verilog"
elif verilog:
file_name = entity.file_name
else:
file_name = entity.architecture_names[architecture_name]
code = ostools.read_file(file_name)
pragmas = self.find_pragmas(code, file_name)
# @TODO use presence of runner_cfg as tb_filter instead of tb_*
has_runner_cfg = verilog or ("runner_cfg" in entity.generic_names)
if has_runner_cfg:
run_strings = self.find_run_strings(code, file_name, verilog)
else:
run_strings = []
return pragmas, run_strings
def _needs_recompile(self, dependency_graph, source_file):
md5 = source_file.md5()
md5_file_name = self._hash_file_name_of(source_file)
if not ostools.file_exists(md5_file_name):
logger.debug("%s has no vunit_hash file at %s and must be recompiled",
source_file.name, md5_file_name)
return True
old_md5 = ostools.read_file(md5_file_name)
if old_md5 != md5:
logger.debug("%s has different hash than last time and must be recompiled",
source_file.name)
return True
for other_file in dependency_graph.get_dependencies(source_file):
other_md5_file_name = self._hash_file_name_of(other_file)
if not ostools.file_exists(other_md5_file_name):
continue
if ostools.get_modification_time(other_md5_file_name) > ostools.get_modification_time(md5_file_name):
logger.debug("%s has dependency compiled earlier and must be recompiled",
source_file.name)
return True
logger.debug("%s has same hash file and must not be recompiled",
source_file.name)
return False
def test_elaborate(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
config = make_config(verilog=True)
self.assertTrue(simif.simulate("suite_output_path", "test_suite_name", config, elaborate_only=True))
elaborate_args_file = join('suite_output_path', simif.name, 'irun_elaborate.args')
run_command.assert_has_calls([
mock.call([join('prefix', 'irun'), '-f', basename(elaborate_args_file)],
cwd=dirname(elaborate_args_file),
env=simif.get_env()),
])
self.assertEqual(
read_file(elaborate_args_file).splitlines(),
['-elaborate',
'-nocopyright',
'-licqueue',
'-errormax 10',
'-nowarn WRMNZD',
'-nowarn DLCPTH',
'-nowarn DLCVAR',
'-ncerror EVBBOL',
'-ncerror EVBSTR',
'-ncerror EVBNAT',
'-work work',
'-nclibdirname "%s"' % join(self.output_path, "libraries"),
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' % join("suite_output_path", simif.name, "irun_elaborate.log"),
'-quiet',
'-access +r',
'-input "@run"',
'-top lib.modulename:sv'])
def _needs_recompile(self, dependency_graph, source_file, timestamps):
"""
Returns True if the source_file needs to be recompiled
given the dependency_graph, the file contents and the last modification time
"""
timestamp = timestamps[source_file]
content_hash_file_name = self._hash_file_name_of(source_file)
if timestamp is None:
LOGGER.debug("%s has no vunit_hash file at %s and must be recompiled",
source_file.name, content_hash_file_name)
return True
old_content_hash = ostools.read_file(content_hash_file_name)
if old_content_hash != source_file.content_hash:
LOGGER.debug("%s has different hash than last time and must be recompiled",
source_file.name)
return True
for other_file in dependency_graph.get_direct_dependencies(source_file):
other_timestamp = timestamps[other_file]
if other_timestamp is None:
# Other file has not been compiled and will trigger recompile of this file
continue
if other_timestamp > timestamp:
LOGGER.debug("%s has dependency compiled earlier and must be recompiled",
source_file.name)
return True
LOGGER.debug("%s has same hash file and must not be recompiled",
source_file.name)
return False
def _preprocess(self, library_name, file_name, preprocessors):
"""
Preprocess file_name within library_name using explicit preprocessors
if preprocessors is None then use implicit globally defined processors
"""
# @TODO dependency checking etc...
if preprocessors is None:
preprocessors = [self._location_preprocessor, self._check_preprocessor]
preprocessors = [p for p in preprocessors if p is not None]
preprocessors = self._external_preprocessors + preprocessors
if len(preprocessors) == 0:
return file_name
code = ostools.read_file(file_name)
for preprocessor in preprocessors:
code = preprocessor.run(code, basename(file_name))
pp_file_name = join(self._preprocessed_path, library_name, basename(file_name))
idx = 1
while ostools.file_exists(pp_file_name):
LOGGER.debug("Preprocessed file exists '%s', adding prefix", pp_file_name)
pp_file_name = join(self._preprocessed_path,
library_name, "%i_%s" % (idx, basename(file_name)))
idx += 1
ostools.write_file(pp_file_name, code)
return pp_file_name
def test_compile_project_vhdl_extra_flags(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("incisive.irun_vhdl_flags", ["custom", "flags"])
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
run_command.assert_called_once_with(
[join('prefix', 'irun'), '-f', args_file])
self.assertEqual(read_file(args_file).splitlines(),
['-compile',
'-nocopyright',
'-licqueue',
'-nowarn DLCPTH',
'-nowarn DLCVAR',
'-v200x -extv200x',
'-work work',
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"),
'-quiet',
'custom', 'flags',
'-nclibdirname ""',
'-makelib lib_path',
'"file.vhd"',
'-endlib'])
def _determine_partial_pass(self, output_path):
"""
In case of simulation failure determine which of the individual test cases failed.
This is done by reading the test_runner_trace.csv file and checking for test case entry points.
"""
log_file = join(output_path, "test_runner_trace.csv")
retval = {}
for name in self.test_cases:
retval[name] = FAILED
if not ostools.file_exists(log_file):
return retval
test_log = ostools.read_file(log_file)
test_starts = []
for test_name in self._test_cases:
if "Test Runner,Test case: " + test_name in test_log:
test_starts.append(test_name)
for test_name in test_starts[:-1]:
retval[self._full_name(test_name)] = PASSED
for test_name in self._test_cases:
if test_name not in test_starts:
retval[self._full_name(test_name)] = SKIPPED
return retval
def _preprocess(self, library_name, file_name, preprocessors):
"""
Preprocess file_name within library_name using explicit preprocessors
if preprocessors is None then use implicit globally defined processors
"""
# @TODO dependency checking etc...
if preprocessors is None:
preprocessors = [self._location_preprocessor, self._check_preprocessor]
preprocessors = [p for p in preprocessors if p is not None]
preprocessors = self._external_preprocessors + preprocessors
if len(preprocessors) == 0:
return file_name
code = ostools.read_file(file_name)
for preprocessor in preprocessors:
code = preprocessor.run(code, basename(file_name))
pp_file_name = join(self._preprocessed_path, library_name, basename(file_name))
idx = 1
while ostools.file_exists(pp_file_name):
LOGGER.debug("Preprocessed file exists '%s', adding prefix", pp_file_name)
pp_file_name = join(self._preprocessed_path,
library_name, "%i_%s" % (idx, basename(file_name)))
idx += 1
ostools.write_file(pp_file_name, code)
return pp_file_name
def generate_codecs(input_package_design_unit, codec_package_name, # pylint: disable=too-many-arguments
used_packages, output_file, debug):
"""This function generates codecs for the types in the input package and compile the result into
codec_package_name. used_packages is a list specifying what to include into the result package
other than the input package. A used package on the format 'lib.pkg' will result in a library and
a use statement. A used package on the format 'pkg' is assumed to be located in work. output_file
is where the resulting codec package is written. The debug codecs are generated when debug is set True."""
# The design unit doesn't contain the package so it must be found first in the source file. This file
# may contain other packages
code = read_file(input_package_design_unit.source_file.name)
package = CodecVHDLPackage.find_named_package(code, input_package_design_unit.name)
if package is None:
raise KeyError(input_package_design_unit.name)
# Get all function declarations and definitions derived from the package type definitions
declarations, definitions = package.generate_codecs_and_support_functions(debug)
# Create extra use clauses
use_clauses = ''
libraries = []
for used_package in used_packages if used_packages is not None else []:
if '.' in used_package:
if used_package.split('.')[0] not in libraries:
libraries.append(used_package.split('.')[0])
use_clauses += 'use %s.all;\n' % used_package
else:
use_clauses += 'use work.%s.all;\n' % used_package
if len(libraries) != 0:
use_clauses = 'library ' + ';\nlibrary '.join(libraries) + ';\n' + use_clauses
# Assemble everything and write to output file
codec_package_template = Template("""\
library vunit_lib;
use vunit_lib.string_ops.all;
context vunit_lib.com_context;
use std.textio.all;
use work.$package_name.all;
$use_clauses
package $codec_package_name is
$declarations
end package $codec_package_name;
package body $codec_package_name is
$definitions
end package body $codec_package_name;
""")
codec_package = codec_package_template.substitute(
declarations=declarations,
definitions=definitions,
package_name=package.identifier,
codec_package_name=codec_package_name,
use_clauses=use_clauses)
write_file(output_file, codec_package)
def parse(self, file_name, include_paths=None, defines=None):
"""
Parse verilog code
"""
defines = {} if defines is None else defines
include_paths = [] if include_paths is None else include_paths
include_paths = [dirname(file_name)] + include_paths
cached = self._lookup_parse_cache(file_name, include_paths, defines)
if cached is not None:
return cached
initial_defines = dict((key, Macro(key, self._tokenizer.tokenize(value)))
for key, value in defines.items())
code = read_file(file_name, encoding=HDL_FILE_ENCODING)
tokens = self._tokenizer.tokenize(code, file_name=file_name)
included_files = []
pp_tokens = self._preprocessor.preprocess(tokens,
include_paths=include_paths,
defines=initial_defines,
included_files=included_files)
included_files_for_design_file = [name for _, name in included_files if name is not None]
result = VerilogDesignFile.parse(pp_tokens, included_files_for_design_file)
if self._database is None:
return result
self._store_result(file_name, result, included_files, defines)
return result
def _needs_recompile(self, dependency_graph, source_file):
"""
Returns True if the source_file needs to be recompiled
given the dependency_graph, the file contents and the last modification time
"""
content_hash = source_file.content_hash
content_hash_file_name = self._hash_file_name_of(source_file)
if not ostools.file_exists(content_hash_file_name):
LOGGER.debug("%s has no vunit_hash file at %s and must be recompiled",
source_file.name, content_hash_file_name)
return True
old_content_hash = ostools.read_file(content_hash_file_name)
if old_content_hash != content_hash:
LOGGER.debug("%s has different hash than last time and must be recompiled",
source_file.name)
return True
for other_file in dependency_graph.get_direct_dependencies(source_file):
other_content_hash_file_name = self._hash_file_name_of(other_file)
if not ostools.file_exists(other_content_hash_file_name):
continue
if more_recent(other_content_hash_file_name, content_hash_file_name):
LOGGER.debug("%s has dependency compiled earlier and must be recompiled",
source_file.name)
return True
LOGGER.debug("%s has same hash file and must not be recompiled",
source_file.name)
return False
def _determine_partial_pass(self, output_path):
"""
@TODO is this a good way?
"""
log_file = join(output_path, "test_runner_trace.csv")
retval = {}
for name in self.test_cases:
retval[name] = FAILED
if not ostools.file_exists(log_file):
return retval
test_log = ostools.read_file(log_file)
test_starts = []
for test_name in self._test_cases:
if ("Test Runner,Test case: " + test_name) in test_log:
test_starts.append(test_name)
for test_name in test_starts[:-1]:
retval[self._full_name(test_name)] = PASSED
for test_name in self._test_cases:
if not test_name in test_starts:
retval[self._full_name(test_name)] = SKIPPED
return retval
def __init__(
self, # pylint: disable=too-many-arguments
name,
library,
verilog_parser,
include_dirs=None,
defines=None,
no_parse=False):
SourceFile.__init__(self, name, library, 'verilog')
self.package_dependencies = []
self.module_dependencies = []
self.include_dirs = include_dirs if include_dirs is not None else []
self.defines = defines.copy() if defines is not None else {}
code = ostools.read_file(self.name, encoding=HDL_FILE_ENCODING)
self._content_hash = hash_string(code)
for path in self.include_dirs:
self._content_hash = hash_string(self._content_hash +
hash_string(path))
for key, value in self.defines.items():
self._content_hash = hash_string(self._content_hash +
hash_string(key))
self._content_hash = hash_string(self._content_hash +
hash_string(value))
if not no_parse:
self.parse(code, verilog_parser, include_dirs)
def _preprocess(self, library_name, file_name, preprocessors):
# @TODO dependency checking etc...
if preprocessors is None:
preprocessors = [
self._location_preprocessor, self._check_preprocessor
]
preprocessors = [p for p in preprocessors if not p is None]
preprocessors = self._external_preprocessors + preprocessors
if len(preprocessors) == 0:
return file_name
code = ostools.read_file(file_name)
for p in preprocessors:
code = p.run(code, basename(file_name))
pp_file_name = join(self._preprocessed_path, library_name,
basename(file_name))
idx = 1
while ostools.file_exists(pp_file_name):
logger.debug("Preprocessed file exists '%s', adding prefix" %
pp_file_name)
pp_file_name = join(self._preprocessed_path, library_name,
"%i_%s" % (idx, basename(file_name)))
idx += 1
ostools.write_file(pp_file_name, code)
return pp_file_name
def _preprocess(self, library_name, file_name, preprocessors):
# @TODO dependency checking etc...
if preprocessors is None:
preprocessors = [self._location_preprocessor, self._check_preprocessor]
preprocessors = [p for p in preprocessors if not p is None]
preprocessors = self._external_preprocessors + preprocessors
if len(preprocessors) == 0:
return file_name
code = ostools.read_file(file_name)
for p in preprocessors:
code = p.run(code, basename(file_name))
pp_file_name = join(self._preprocessed_path, library_name, basename(file_name))
idx = 1
while ostools.file_exists(pp_file_name):
logger.debug("Preprocessed file exists '%s', adding prefix" % pp_file_name)
pp_file_name = join(self._preprocessed_path,
library_name, "%i_%s" % (idx, basename(file_name)))
idx += 1
ostools.write_file(pp_file_name, code)
return pp_file_name
def test_compile_project_verilog_include(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", include_dirs=["include"])
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
run_command.assert_called_once_with(
[join('prefix', 'irun'), '-f', args_file])
self.assertEqual(read_file(args_file).splitlines(),
['-compile',
'-nocopyright',
'-licqueue',
'-nowarn UEXPSC',
'-nowarn DLCPTH',
'-nowarn DLCVAR',
'-work work',
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
'-quiet',
'-incdir "include"',
'-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
'-nclibdirname ""',
'-makelib lib',
'"file.v"',
'-endlib'])
def run(self, output_path):
"""
Run the test case using the output_path
"""
if not call_pre_config(self._config.pre_config, output_path):
return False
enabled_test_cases = [self._test_case]
config = _add_runner_cfg(self._config, output_path, enabled_test_cases)
sim_ok = self._simulator_if.simulate(
join(output_path, self._simulator_if.name),
self._name,
config,
elaborate_only=self._elaborate_only)
if self._elaborate_only:
return sim_ok
vunit_results_file = join(output_path, "vunit_results")
if not ostools.file_exists(vunit_results_file):
return False
test_results = ostools.read_file(vunit_results_file)
expected_results = ""
if self._test_case is not None:
expected_results += "test_start:%s\n" % self._test_case
expected_results += "test_suite_done\n"
if not test_results == expected_results:
return False
if self._config.post_check is None:
return True
return self._config.post_check(output_path)
def test_that_a_valid_license_exists_in_source_files_and_that_global_licensing_information_is_correct(self):
licensed_files = []
for root, _, files in walk(ROOT):
for file_name in files:
if "preprocessed" in root:
continue
if "codecs" in root:
continue
osvvm_directory = abspath(join(ROOT, "vhdl", "osvvm"))
if is_prefix_of(osvvm_directory, abspath(join(root, file_name))):
continue
osvvm_integration_example_directory = abspath(
join(ROOT, "examples", "vhdl", "osvvm_integration", "src")
)
if is_prefix_of(osvvm_integration_example_directory, abspath(join(root, file_name))):
continue
if splitext(file_name)[1] in (".vhd", ".vhdl", ".py", ".v", ".sv"):
licensed_files.append(join(root, file_name))
for file_name in licensed_files:
code = ostools.read_file(file_name)
self._check_license(code, file_name)
if splitext(file_name)[1] in (".vhd", ".vhdl", ".v", ".sv"):
self._check_no_trailing_whitespace(code, file_name)
def test_simulate_hdlvar(self, run_command, find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path,
hdlvar="custom_hdlvar")
config = make_config()
self.assertTrue(
simif.simulate("sim_output_path", "test_suite_name", config))
elaborate_args_file = join('sim_output_path', 'irun_elaborate.args')
simulate_args_file = join('sim_output_path', 'irun_simulate.args')
run_command.assert_has_calls([
mock.call(
[join('prefix', 'irun'), '-f',
basename(elaborate_args_file)],
cwd=dirname(elaborate_args_file),
env=simif.get_env()),
mock.call(
[join('prefix', 'irun'), '-f',
basename(simulate_args_file)],
cwd=dirname(simulate_args_file),
env=simif.get_env()),
])
for args_file in [elaborate_args_file, simulate_args_file]:
args = read_file(args_file).splitlines()
self.assertIn('-hdlvar "custom_hdlvar"', args)
def __init__(self, name, library, vhdl_parser):
SourceFile.__init__(self, name, library, 'vhdl')
self.dependencies = []
self.depending_components = []
code = ostools.read_file(self.name)
self._content_hash = hash_string(code)
self.parse(code, vhdl_parser)
def parse(self, code, parser, include_dirs):
"""
Parse Verilog code and adding dependencies and design units
"""
try:
design_file = parser.parse(code, self.name, include_dirs,
self.defines)
for included_file_name in design_file.included_files:
self._content_hash = hash_string(
self._content_hash + ostools.read_file(included_file_name))
for module in design_file.modules:
self.design_units.append(
ModuleDesignUnit(module.name, self, module.parameters))
for package in design_file.packages:
self.design_units.append(
VerilogDesignUnit(package.name, self, "package"))
for package_name in design_file.imports:
self.package_dependencies.append(package_name)
for package_name in design_file.package_references:
self.package_dependencies.append(package_name)
for instance_name in design_file.instances:
self.module_dependencies.append(instance_name)
except KeyboardInterrupt:
raise
except: # pylint: disable=bare-except
traceback.print_exc()
LOGGER.error("Failed to parse %s", self.name)
def _needs_recompile(self, dependency_graph, source_file):
"""
Returns True if the source_file needs to be recompiled
given the dependency_graph, the file contents and the last modification time
"""
content_hash = source_file.content_hash
content_hash_file_name = self._hash_file_name_of(source_file)
if not ostools.file_exists(content_hash_file_name):
LOGGER.debug("%s has no vunit_hash file at %s and must be recompiled",
source_file.name, content_hash_file_name)
return True
old_content_hash = ostools.read_file(content_hash_file_name)
if old_content_hash != content_hash:
LOGGER.debug("%s has different hash than last time and must be recompiled",
source_file.name)
return True
for other_file in dependency_graph.get_direct_dependencies(source_file):
other_content_hash_file_name = self._hash_file_name_of(other_file)
if not ostools.file_exists(other_content_hash_file_name):
continue
if more_recent(other_content_hash_file_name, content_hash_file_name):
LOGGER.debug("%s has dependency compiled earlier and must be recompiled",
source_file.name)
return True
LOGGER.debug("%s has same hash file and must not be recompiled",
source_file.name)
return False
def test_that_a_valid_license_exists_in_source_files_and_that_global_licensing_information_is_correct(self):
licensed_files = []
for root, _, files in walk(ROOT):
for file_name in files:
if 'preprocessed' in root:
continue
if 'codecs' in root:
continue
if root == join(ROOT, "docs"):
continue
osvvm_directory = abspath(join(VHDL_PATH, 'osvvm'))
if is_prefix_of(osvvm_directory, abspath(join(root, file_name))):
continue
osvvm_integration_example_directory = abspath(
join(ROOT, 'examples', 'vhdl', 'osvvm_integration', 'src'))
if is_prefix_of(osvvm_integration_example_directory, abspath(join(root, file_name))):
continue
if splitext(file_name)[1] in ('.vhd', '.vhdl', '.py', '.v', '.sv'):
licensed_files.append(join(root, file_name))
for file_name in licensed_files:
code = ostools.read_file(file_name)
self._check_license(code, file_name)
if splitext(file_name)[1] in ('.vhd', '.vhdl', '.v', '.sv'):
self._check_no_trailing_whitespace(code, file_name)
def parse(self, code, parser, include_dirs):
"""
Parse Verilog code and adding dependencies and design units
"""
try:
design_file = parser.parse(code, self.name, include_dirs, self.defines)
for included_file_name in design_file.included_files:
self._content_hash = hash_string(self._content_hash +
ostools.read_file(included_file_name, encoding=HDL_FILE_ENCODING))
for module in design_file.modules:
self.design_units.append(ModuleDesignUnit(module.name, self, module.parameters))
for package in design_file.packages:
self.design_units.append(VerilogDesignUnit(package.name, self, "package"))
for package_name in design_file.imports:
self.package_dependencies.append(package_name)
for package_name in design_file.package_references:
self.package_dependencies.append(package_name)
for instance_name in design_file.instances:
self.module_dependencies.append(instance_name)
except KeyboardInterrupt:
raise
except: # pylint: disable=bare-except
traceback.print_exc()
LOGGER.error("Failed to parse %s", self.name)
def test_compile_project_vhdl_2002(self, check_output, find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard="2002")
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
check_output.assert_called_once_with(
[join('prefix', 'irun'), '-f', args_file], env=simif.get_env())
self.assertEqual(
read_file(args_file).splitlines(), [
'-compile', '-nocopyright', '-licqueue', '-nowarn DLCPTH',
'-nowarn DLCVAR', '-v200x -extv200x', '-work work',
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' %
join(self.output_path, "irun_compile_vhdl_file_lib.log"),
'-quiet', '-nclibdirname ""', '-makelib lib_path',
'"file.vhd"', '-endlib'
])
def test_simulate_generics_and_parameters(self, run_command,
find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path)
config = make_config(verilog=True,
generics={
"genstr": "genval",
"genint": 1,
"genbool": True
})
self.assertTrue(
simif.simulate("sim_output_path", "test_suite_name", config))
elaborate_args_file = join('sim_output_path', 'irun_elaborate.args')
simulate_args_file = join('sim_output_path', 'irun_simulate.args')
run_command.assert_has_calls([
mock.call(
[join('prefix', 'irun'), '-f',
basename(elaborate_args_file)],
cwd=dirname(elaborate_args_file),
env=simif.get_env()),
mock.call(
[join('prefix', 'irun'), '-f',
basename(simulate_args_file)],
cwd=dirname(simulate_args_file),
env=simif.get_env()),
])
for args_file in [elaborate_args_file, simulate_args_file]:
args = read_file(args_file).splitlines()
self.assertIn('-gpg "modulename.genstr => \\"genval\\""', args)
self.assertIn('-gpg "modulename.genint => 1"', args)
self.assertIn('-gpg "modulename.genbool => \\"True\\""', args)
def test_that_a_valid_license_exists_in_source_files_and_that_global_licensing_information_is_correct(
self):
for file_name in find_licensed_files():
code = ostools.read_file(file_name)
self._check_license(code, file_name)
if splitext(file_name)[1] in ('.vhd', '.vhdl', '.v', '.sv'):
self._check_no_trailing_whitespace(code, file_name)
def test_compile_project_verilog_hdlvar(self, check_output,
find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path,
hdlvar="custom_hdlvar")
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v",
"lib",
file_type="verilog",
defines=dict(defname="defval"))
simif.compile_project(project)
args_file = join(self.output_path,
"irun_compile_verilog_file_lib.args")
check_output.assert_called_once_with(
[join('prefix', 'irun'), '-f', args_file], env=simif.get_env())
self.assertEqual(
read_file(args_file).splitlines(), [
'-compile', '-nocopyright', '-licqueue', '-nowarn UEXPSC',
'-nowarn DLCPTH', '-nowarn DLCVAR', '-work work',
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-hdlvar "custom_hdlvar"',
'-log "%s"' %
join(self.output_path, "irun_compile_verilog_file_lib.log"),
'-quiet', '-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
'-define defname=defval', '-nclibdirname ""', '-makelib lib',
'"file.v"', '-endlib'
])
def test_compile_project_vhdl_2002(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002")
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-v200x -extv200x",
"-work work",
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"),
"-quiet",
'-nclibdirname ""',
"-makelib lib_path",
'"file.vhd"',
"-endlib",
],
)
def _create_modelsim_ini(self):
"""
Create the modelsim.ini file if it does not exist
"""
if file_exists(self._modelsim_ini):
return
write_file(self._modelsim_ini, read_file(join(self._prefix, "..", "modelsim.ini")))
def test_that_a_valid_license_exists_in_source_files_and_that_global_licensing_information_is_correct(
self, ):
for file_name in find_licensed_files():
code = ostools.read_file(file_name)
self._check_license(code, file_name)
if Path(file_name).suffix in (".vhd", ".vhdl", ".v", ".sv"):
self._check_no_trailing_whitespace(code, file_name)
def __init__(self, name, library, vhdl_parser):
SourceFile.__init__(self, name, library, 'vhdl')
self.dependencies = []
self.depending_components = []
code = ostools.read_file(self.name)
self._content_hash = hash_string(code)
self.parse(code, vhdl_parser)
def test_elaborate(self, run_command, find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path)
config = make_config(verilog=True)
self.assertTrue(
simif.simulate("sim_output_path",
"test_suite_name",
config,
elaborate_only=True))
elaborate_args_file = join('sim_output_path', 'irun_elaborate.args')
run_command.assert_has_calls([
mock.call(
[join('prefix', 'irun'), '-f',
basename(elaborate_args_file)],
cwd=dirname(elaborate_args_file),
env=simif.get_env()),
])
self.assertEqual(
read_file(elaborate_args_file).splitlines(), [
'-elaborate', '-nocopyright', '-licqueue', '-errormax 10',
'-nowarn WRMNZD', '-nowarn DLCPTH', '-nowarn DLCVAR',
'-ncerror EVBBOL', '-ncerror EVBSTR', '-ncerror EVBNAT',
'-work work',
'-nclibdirname "%s"' % join(self.output_path, "libraries"),
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "sim_output_path/irun_elaborate.log"', '-quiet',
'-access +r', '-input "@run"',
'-input "@catch {if {#vunit_pkg::__runner__.exit_without_errors == 1} {exit 0} else {exit 42}}"',
'-input "@catch {if {#run_pkg.runner.exit_without_errors == \\"TRUE\\"} {exit 0} else {exit 42}}"',
'-top lib.modulename:sv'
])
def __init__(self, name, library, verilog_parser, include_dirs):
SourceFile.__init__(self, name, library, 'verilog')
self.package_dependencies = []
self.module_dependencies = []
self.include_dirs = include_dirs if include_dirs is not None else []
code = ostools.read_file(self.name)
self._content_hash = hash_string(code)
self.parse(code, verilog_parser, include_dirs)
def test_compile_project_verilog(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog")
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn UEXPSC",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-work work",
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
"-quiet",
'-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
'-nclibdirname ""',
"-makelib lib",
'"file.v"',
"-endlib",
],
)
self.assertEqual(
read_file(join(self.output_path, "cds.lib")),
"""\
## cds.lib: Defines the locations of compiled libraries.
softinclude cds_root_irun/tools/inca/files/cds.lib
# needed for referencing the library 'basic' for cells 'cds_alias', 'cds_thru' etc. in analog models:
# NOTE: 'virtuoso' executable not found!
# define basic ".../tools/dfII/etc/cdslib/basic"
define lib "lib_path"
define work "%s/libraries/work"
"""
% self.output_path,
)
def __init__(self, name, library, vhdl_parser, vhdl_standard):
SourceFile.__init__(self, name, library, 'vhdl')
self.dependencies = []
self.depending_components = []
self._vhdl_standard = vhdl_standard
check_vhdl_standard(vhdl_standard)
code = ostools.read_file(self.name, encoding=HDL_FILE_ENCODING)
self._content_hash = hash_string(code)
self.parse(code, vhdl_parser)
def _content_hash(self, file_name):
"""
Hash the contents of the file
"""
if file_name is None or not exists(file_name):
return None
if file_name not in self._content_cache:
self._content_cache[file_name] = "sha1:" + hash_string(read_file(file_name))
return self._content_cache[file_name]
def __init__(self, name, library, vhdl_parser, vhdl_standard):
SourceFile.__init__(self, name, library, 'vhdl')
self.dependencies = []
self.depending_components = []
self._vhdl_standard = vhdl_standard
check_vhdl_standard(vhdl_standard)
code = ostools.read_file(self.name, encoding=HDL_FILE_ENCODING)
self._content_hash = hash_string(code)
self.parse(code, vhdl_parser)
def _content_hash(self, file_name):
"""
Hash the contents of the file
"""
if file_name is None or not exists(file_name):
return None
if file_name not in self._content_cache:
self._content_cache[file_name] = "sha1:" + hash_string(read_file(file_name))
return self._content_cache[file_name]
def output(self):
"""
Return test output
"""
file_exists = os.path.isfile(self._output_file_name)
is_readable = os.access(self._output_file_name, os.R_OK)
if file_exists and is_readable:
return read_file(self._output_file_name)
return "Failed to read output file: %s" % self._output_file_name
def output(self):
"""
Return test output
"""
file_exists = os.path.isfile(self._output_file_name)
is_readable = os.access(self._output_file_name, os.R_OK)
if file_exists and is_readable:
return read_file(self._output_file_name)
return "Failed to read output file: %s" % self._output_file_name
def include(self, token, stream, include_paths, included_files, defines): # pylint: disable=too-many-arguments
"""
Handle `include directive
"""
stream.skip_while(WHITESPACE)
try:
tok = stream.pop()
except EOFException:
raise LocationException.warning("EOF reached when parsing `include argument", token.location)
if tok.kind == PREPROCESSOR:
if tok.value in defines:
macro = defines[tok.value]
else:
raise LocationException.warning("Verilog `include argument not defined", tok.location)
expanded_tokens = self.expand_macro(tok, stream, defines, include_paths, included_files)
if len(expanded_tokens) == 0:
raise LocationException.warning(
"Verilog `include has bad argument, empty define `%s" % macro.name, tok.location
)
if expanded_tokens[0].kind != STRING:
raise LocationException.warning("Verilog `include has bad argument", expanded_tokens[0].location)
file_name_tok = expanded_tokens[0]
elif tok.kind == STRING:
file_name_tok = tok
else:
raise LocationException.warning("Verilog `include bad argument", tok.location)
included_file = find_included_file(include_paths, file_name_tok.value)
included_files.append((file_name_tok.value, included_file))
if included_file is None:
# Is debug message since there are so many builtin includes in tools
raise LocationException.debug(
"Could not find `include file %s" % file_name_tok.value, file_name_tok.location
)
include_point = (strip_previous(token.location), hash(frozenset(defines.keys())))
if include_point in self._include_trace:
raise LocationException.error(
"Circular `include of %s detected" % file_name_tok.value, file_name_tok.location
)
self._include_trace.add(include_point)
included_tokens = self._tokenizer.tokenize(
read_file(included_file), file_name=included_file, previous_location=token.location
)
included_tokens = self._preprocess(included_tokens, defines, include_paths, included_files)
self._include_trace.remove(include_point)
return included_tokens
def test_create_cds_lib_virtuoso(self, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = "cds_root_virtuoso"
IncisiveInterface(prefix="prefix", output_path=self.output_path)
self.assertEqual(read_file(join(self.output_path, "cds.lib")), """\
## cds.lib: Defines the locations of compiled libraries.
softinclude cds_root_irun/tools/inca/files/cds.lib
# needed for referencing the library 'basic' for cells 'cds_alias', 'cds_thru' etc. in analog models:
define basic "cds_root_virtuoso/tools/dfII/etc/cdslib/basic"
define work "%s/libraries/work"
""" % self.output_path)
def __init__(self, name, library, verilog_parser, include_dirs=None, defines=None):
SourceFile.__init__(self, name, library, 'verilog')
self.package_dependencies = []
self.module_dependencies = []
self.include_dirs = include_dirs if include_dirs is not None else []
self.defines = defines.copy() if defines is not None else {}
code = ostools.read_file(self.name, encoding=HDL_FILE_ENCODING)
self._content_hash = hash_string(code)
for key, value in self.defines.items():
self._content_hash = hash_string(self._content_hash + hash_string(key))
self._content_hash = hash_string(self._content_hash + hash_string(value))
self.parse(code, verilog_parser, include_dirs)
