def test_compile_project_vhdl_extra_flags(self, check_output,
find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd",
"lib",
file_type="vhdl")
source_file.set_compile_option("incisive.irun_vhdl_flags",
["custom", "flags"])
simif.compile_project(project)
args_file = str(
Path(self.output_path) / "irun_compile_vhdl_file_lib.args")
check_output.assert_called_once_with(
[str(Path("prefix") / "irun"), "-f", args_file],
env=simif.get_env())
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-v200x -extv200x",
"-work work",
'-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"),
'-log "%s"' %
str(Path(self.output_path) / "irun_compile_vhdl_file_lib.log"),
"-quiet",
"custom",
"flags",
'-nclibdirname "."',
"-makelib lib_path",
'"file.vhd"',
"-endlib",
],
)
def test_compile_project_vhdl(self, process, check_output):
simif = RivieraProInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
check_output.assert_called_once_with([
join('prefix', 'vcom'), '-quiet', '-j', self.output_path, '-2008',
'-work', 'lib', 'file.vhd'
],
env=simif.get_env())
def test_compile_source_files_minimal_subset(self):
simif = create_simulator_interface()
project = Project()
project.add_library("lib", "lib_path")
write_file("file1.vhd", "")
file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl")
with mock.patch(
"vunit.project.Project.get_minimal_file_set_in_compile_order",
autospec=True) as target_function:
target_function.return_value = []
printer = MockPrinter()
simif.compile_source_files(project,
printer=printer,
target_files=[file1])
simif.compile_source_files(project,
printer=printer,
target_files=[file1])
self.assertTrue(target_function.called)
def test_compile_project_verilog(self, process, check_output):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix", library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog")
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
check_output.assert_called_once_with([
join('prefix', 'vlog'), '-quiet', '-lc', library_cfg, '-work',
'lib', 'file.v', '-l', 'lib'
],
env=simif.get_env())
def test_compile_source_files_run_command_error(self):
simif = create_simulator_interface()
simif.compile_source_file_command.return_value = ["command"]
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd",
"lib",
file_type="vhdl")
with mock.patch("vunit.simulator_interface.run_command",
autospec=True) as run_command:
run_command.return_value = False
self.assertRaises(CompileError, simif.compile_source_files,
project)
run_command.assert_called_once_with(["command"],
env=simif.get_env())
self.assertEqual(project.get_files_in_compile_order(incremental=True),
[source_file])
def test_dependencies_on_separated_architecture(self):
"""
Create a projected containing an entity file separated from architecture file.
Dependency should involve also architecture.
"""
self.project = Project()
self.project.add_library("lib", "work_path")
self.add_source_file("lib", "file1.vhd", """\
library ieee;
use ieee.std_logic_1164.all;
entity buffer1 is
port (D : in std_logic;
Q : out std_logic);
end entity;
""")
file1_arch_vhd = self.add_source_file("lib", "file1_arch.vhd", """\
library ieee;
use ieee.std_logic_1164.all;
architecture arch of buffer1 is
begin
Q <= D;
end architecture;
""")
file3 = self.add_source_file("lib", "file3.vhd", """\
library ieee;
use ieee.std_logic_1164.all;
entity your_buffer is
port (D : in std_logic; Q : out std_logic);
end entity;
architecture arch of your_buffer is
begin
my_buffer_i : entity work.buffer1
port map (D => D,Q => Q);
end architecture;
""")
dep_files = self.project.get_dependencies_in_compile_order([file3], implementation_dependencies=True)
self.assertIn(file1_arch_vhd, dep_files)
def test_compile_project_verilog_hdlvar(self, check_output,
find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path,
hdlvar="custom_hdlvar")
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v",
"lib",
file_type="verilog",
defines=dict(defname="defval"))
simif.compile_project(project)
args_file = join(self.output_path,
"irun_compile_verilog_file_lib.args")
check_output.assert_called_once_with(
[join("prefix", "irun"), "-f", args_file], env=simif.get_env())
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn UEXPSC",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-work work",
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-hdlvar "custom_hdlvar"',
'-log "%s"' %
join(self.output_path, "irun_compile_verilog_file_lib.log"),
"-quiet",
'-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
"-define defname=defval",
'-nclibdirname ""',
"-makelib lib",
'"file.v"',
"-endlib",
],
)
def test_compile_project_vhdl_93(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard=VHDL.standard("93"))
simif.compile_project(project)
process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
check_args = [
str(Path(self.prefix_path) / "vcom"),
"-quiet",
"-modelsimini",
str(Path(self.output_path) / "modelsim.ini"),
"-93",
"-work",
"lib",
"file.vhd",
]
check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_vhdl(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
run_command.assert_called_once_with(
[join('prefix', 'vcom'),
'-quiet',
'-j',
self.output_path,
'-2008',
'-work',
'lib',
'file.vhd'])
def test_compile_project_verilog(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = RivieraProInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog")
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-sv2k12',
'-lc',
library_cfg,
'-work',
'lib',
'file.v',
'-l', 'lib'])
def test_compile_project_verilog_coverage(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
coverage="best",
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog")
simif.compile_project(project)
process.assert_called_once_with(
[join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([
join('prefix', 'vlog'), '-sv', '-quiet', '-modelsimini',
modelsim_ini, '+cover=best', '-work', 'lib', 'file.v', '-L', 'lib'
])
def test_compile_project_system_verilog(self, process, check_output):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.sv", "")
project.add_source_file("file.sv", "lib", file_type="systemverilog")
simif.compile_project(project)
process.assert_called_once_with(
[join("prefix", "vlib"), "-unix", "lib_path"], env=simif.get_env())
check_output.assert_called_once_with([
join('prefix', 'vlog'), '-quiet', '-modelsimini', modelsim_ini,
'-sv', '-work', 'lib', 'file.sv', '-L', 'lib'
],
env=simif.get_env())
def test_compile_project_vhdl_93(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard="93")
simif.compile_project(project)
process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
check_args = [
join(self.prefix_path, 'vcom'), '-quiet', '-modelsimini',
join(self.output_path, "modelsim.ini"), '-93', '-work', 'lib',
'file.vhd'
]
check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_verilog_extra_flags(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = RivieraProInterface(prefix="prefix", library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
source_file = project.add_source_file("file.v",
"lib",
file_type="verilog")
source_file.set_compile_option("rivierapro.vlog_flags",
["custom", "flags"])
simif.compile_project(project, vhdl_standard="2008")
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path)
run_command.assert_called_once_with([
join('prefix', 'vlog'), '-quiet', '-sv2k12', '-lc', library_cfg,
'custom', 'flags', '-work', 'lib', 'file.v', '-l', 'lib'
])
def test_finds_use_package_dependencies_case_insensitive(self):
for library_clause, use_clause in itertools.combinations(("lib", "Lib"), 2):
self.project = Project()
self.project.add_library("Lib", "lib_path")
package = self.add_source_file("Lib", "package.vhd", """
package pkg is
end package;
package body PKG is
begin
end package body;
""")
self.project.add_library("lib2", "lib2_path")
module = self.add_source_file("lib2", "module.vhd", """
library {library_clause};
use {use_clause}.PKG.all;
""".format(library_clause=library_clause, use_clause=use_clause))
self.assert_compiles(package, before=module)
def test_compile_project_93(self, check_output):
simif = GHDLInterface(prefix="prefix", output_path="")
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard=VHDL.standard("93"))
simif.compile_project(project)
check_output.assert_called_once_with(
[
str(Path("prefix") / "ghdl"),
"-a",
"--workdir=lib_path",
"--work=lib",
"--std=93",
"-Plib_path",
"file.vhd",
],
env=simif.get_env(),
)
def test_compile_project_verilog_define(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v",
"lib",
file_type="verilog",
defines={"defname": "defval"})
simif.compile_project(project)
process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
process_args = [
join(self.prefix_path, 'vlog'), '-quiet', '-modelsimini',
join(self.output_path, "modelsim.ini"), '-work', 'lib', 'file.v',
'-L', 'lib', '+define+defname=defval'
]
check_output.assert_called_once_with(process_args, env=simif.get_env())
def test_dependencies_on_verilog_component(self):
"""
Create a projected containing an verilog file separated.
Dependency should involve it.
"""
self.project = Project()
self.project.add_library("lib", "work_path")
file1_v = self.add_source_file("lib", "file1.v", """\
module buffer1 (input D,output Q);
assign Q = D;
endmodule
""")
file3 = self.add_source_file("lib", "file3.vhd", """\
library ieee;use ieee.std_logic_1164.all;
entity your_buffer is port (D : in std_logic;Q : out std_logic);end entity;
architecture arch of your_buffer is
component buffer1 port (D : in std_logic;Q : out std_logic);end component buffer1;
begin my_buffer_i : buffer1 port map (D => D,Q => Q);end architecture;
""")
dep_files = self.project.get_dependencies_in_compile_order([file3], implementation_dependencies=True)
self.assertIn(file1_v, dep_files)
def test_compile_project_verilog_define(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"})
simif.compile_project(project, vhdl_standard="2008")
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-sv2k12',
'-lc',
library_cfg,
'-work',
'lib',
'file.v',
'-l', 'lib',
'+define+defname=defval'])
def test_compile_project_verilog_extra_flags(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
source_file = project.add_source_file("file.v",
"lib",
file_type="verilog")
source_file.set_compile_option("modelsim.vlog_flags",
["custom", "flags"])
simif.compile_project(project)
process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
check_args = [
join(self.prefix_path, 'vlog'), '-quiet', '-modelsimini',
join(self.output_path, "modelsim.ini"), 'custom', 'flags', '-work',
'lib', 'file.v', '-L', 'lib'
]
check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_vhdl_coverage(self, process, check_output):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
coverage="best",
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project)
process.assert_called_once_with(
[join("prefix", "vlib"), "-unix", "lib_path"], env=simif.get_env())
check_output.assert_called_once_with([
join('prefix', 'vcom'), '-quiet', '-modelsimini', modelsim_ini,
'+cover=best', '-2008', '-work', 'lib', 'file.vhd'
],
env=simif.get_env())
def test_compile_source_files_create_command_error(self):
simif = create_simulator_interface()
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd",
"lib",
file_type="vhdl")
with mock.patch("vunit.simulator_interface.check_output",
autospec=True) as check_output:
check_output.return_value = ""
def raise_compile_error(source_file): # pylint: disable=unused-argument
raise CompileError
simif.compile_source_file_command.side_effect = raise_compile_error
self.assertRaises(CompileError, simif.compile_source_files,
project)
self.assertEqual(project.get_files_in_compile_order(incremental=True),
[source_file])
def test_compile_source_files_create_command_error(self):
simif = create_simulator_interface()
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd",
"lib",
file_type="vhdl")
with mock.patch("vunit.simulator_interface.run_command",
autospec=True) as run_command:
run_command.return_value = True
def raise_compile_error(*args, **kwargs):
raise CompileError
simif.compile_source_file_command.side_effect = raise_compile_error
self.assertRaises(CompileError, simif.compile_source_files,
project)
self.assertEqual(project.get_files_in_compile_order(incremental=True),
[source_file])
def test_compile_source_files_check_output_error(self):
simif = create_simulator_interface()
simif.compile_source_file_command.return_value = ["command"]
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd",
"lib",
file_type="vhdl")
with mock.patch("vunit.simulator_interface.check_output",
autospec=True) as check_output:
def check_output_side_effect(command, env=None): # pylint: disable=missing-docstring, unused-argument
raise subprocess.CalledProcessError(returncode=-1,
cmd=command,
output="bad stuff")
check_output.side_effect = check_output_side_effect
printer = MockPrinter()
self.assertRaises(CompileError,
simif.compile_source_files,
project,
printer=printer)
self.assertEqual(
printer.output,
"""\
Compiling into lib: file.vhd failed
=== Command used: ===
command
=== Command output: ===
bad stuff
Compile failed
""",
)
check_output.assert_called_once_with(["command"],
env=simif.get_env())
self.assertEqual(project.get_files_in_compile_order(incremental=True),
[source_file])
def test_compile_project_verilog_extra_flags(self, _find_prefix, process,
check_output):
library_cfg = str(Path(self.output_path) / "library.cfg")
simif = RivieraProInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
source_file = project.add_source_file("file.v",
"lib",
file_type="verilog")
source_file.set_compile_option("rivierapro.vlog_flags",
["custom", "flags"])
simif.compile_project(project)
process.assert_any_call(
[str(Path("prefix") / "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env(),
)
process.assert_called_with(
[str(Path("prefix") / "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env(),
)
check_output.assert_called_once_with(
[
str(Path("prefix") / "vlog"),
"-quiet",
"-lc",
library_cfg,
"custom",
"flags",
"-work",
"lib",
"file.v",
"-l",
"lib",
],
env=simif.get_env(),
)
def test_compile_project_verilog_include(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", include_dirs=["include"])
simif.compile_project(project)
process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
check_args = [
str(Path(self.prefix_path) / "vlog"),
"-quiet",
"-modelsimini",
str(Path(self.output_path) / "modelsim.ini"),
"-work",
"lib",
"file.v",
"-L",
"lib",
"+incdir+include",
]
check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_vhdl_93(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard="93")
simif.compile_project(project)
process.assert_called_once_with(
[join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([
join('prefix', 'vcom'), '-quiet', '-modelsimini', modelsim_ini,
'-93', '-work', 'lib', 'file.vhd'
])
def test_compile_project_system_verilog(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.sv", "")
project.add_source_file("file.sv", "lib", file_type="systemverilog")
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
check_output.assert_called_once_with(
[join('prefix', 'irun'), '-f', args_file],
env=simif.get_env())
self.assertEqual(read_file(args_file).splitlines(),
['-compile',
'-nocopyright',
'-licqueue',
'-nowarn UEXPSC',
'-nowarn DLCPTH',
'-nowarn DLCVAR',
'-work work',
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
'-quiet',
'-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
'-nclibdirname ""',
'-makelib lib',
'"file.sv"',
'-endlib'])
self.assertEqual(read_file(join(self.output_path, "cds.lib")), """\
## cds.lib: Defines the locations of compiled libraries.
softinclude cds_root_irun/tools/inca/files/cds.lib
# needed for referencing the library 'basic' for cells 'cds_alias', 'cds_thru' etc. in analog models:
# NOTE: 'virtuoso' executable not found!
# define basic ".../tools/dfII/etc/cdslib/basic"
define lib "lib_path"
define work "%s/libraries/work"
""" % self.output_path)
def test_compile_source_files(self):
simif = create_simulator_interface()
simif.compile_source_file_command.side_effect = iter([["command1"],
["command2"]])
project = Project()
project.add_library("lib", "lib_path")
write_file("file1.vhd", "")
file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl")
write_file("file2.vhd", "")
file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl")
project.add_manual_dependency(file2, depends_on=file1)
with mock.patch("vunit.simulator_interface.run_command",
autospec=True) as run_command:
run_command.side_effect = iter([True, True])
simif.compile_source_files(project)
run_command.assert_has_calls([
mock.call(["command1"], env=simif.get_env()),
mock.call(["command2"], env=simif.get_env())
])
self.assertEqual(project.get_files_in_compile_order(incremental=True),
[])
def test_compile_project_vhdl_extra_flags(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("activehdl.vcom_flags", ["custom", "flags"])
simif.compile_project(project, vhdl_standard="2008")
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
run_command.assert_called_once_with([join('prefix', 'vcom'),
'-quiet',
'-j',
self.output_path,
'custom',
'flags',
'-2008',
'-work',
'lib',
'file.vhd'])
