def test_compile_project_verilog_define(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"})
simif.compile_project(project, vhdl_standard="2008")
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-sv',
'-quiet',
'-modelsimini',
modelsim_ini,
'-work',
'lib',
'file.v',
'-L', 'lib',
'+define+defname=defval'],
simif._compile_output_consumer) # pylint: disable=protected-access
def test_compile_project_verilog_define(self, process, check_output):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"})
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
check_output.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-lc',
library_cfg,
'-work',
'lib',
'file.v',
'-l', 'lib',
'+define+defname=defval'],
env=simif.get_env())
def test_compile_project_verilog_coverage(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
coverage="best",
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog")
simif.compile_project(project)
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-sv',
'-quiet',
'-modelsimini',
modelsim_ini,
'+cover=best',
'-work',
'lib',
'file.v',
'-L', 'lib'])
def test_compile_project_verilog_hdlvar(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, hdlvar="custom_hdlvar")
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines=dict(defname="defval"))
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
check_output.assert_called_once_with(
[join('prefix', 'irun'), '-f', args_file],
env=simif.get_env())
self.assertEqual(read_file(args_file).splitlines(),
['-compile',
'-nocopyright',
'-licqueue',
'-nowarn UEXPSC',
'-nowarn DLCPTH',
'-nowarn DLCVAR',
'-work work',
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-hdlvar "custom_hdlvar"',
'-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
'-quiet',
'-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
'-define defname=defval',
'-nclibdirname ""',
'-makelib lib',
'"file.v"',
'-endlib'])
def test_compile_project_vhdl_coverage(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
coverage="best",
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project, vhdl_standard="2008")
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vcom'),
'-quiet',
'-modelsimini',
modelsim_ini,
'+cover=best',
'-2008',
'-work',
'lib',
'file.vhd'],
simif._compile_output_consumer) # pylint: disable=protected-access
def test_compile_project_verilog_hdlvar(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path, hdlvar="custom_hdlvar")
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines=dict(defname="defval"))
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn UEXPSC",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-work work",
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-hdlvar "custom_hdlvar"',
'-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
"-quiet",
'-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
"-define defname=defval",
'-nclibdirname ""',
"-makelib lib",
'"file.v"',
"-endlib",
],
)
def test_compile_project_vhdl_2002(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002")
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
check_output.assert_called_once_with(
[join('prefix', 'irun'), '-f', args_file],
env=simif.get_env())
self.assertEqual(read_file(args_file).splitlines(),
['-compile',
'-nocopyright',
'-licqueue',
'-nowarn DLCPTH',
'-nowarn DLCVAR',
'-v200x -extv200x',
'-work work',
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"),
'-quiet',
'-nclibdirname ""',
'-makelib lib_path',
'"file.vhd"',
'-endlib'])
def test_compile_project_vhdl_2002(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002")
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args")
run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-v200x -extv200x",
"-work work",
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"),
"-quiet",
'-nclibdirname ""',
"-makelib lib_path",
'"file.vhd"',
"-endlib",
],
)
def test_compile_project_verilog_error(self):
simif = GHDLInterface(prefix="prefix")
write_file("file.v", "")
project = Project()
project.add_library("lib", "lib_path")
project.add_source_file("file.v", "lib", file_type="verilog")
self.assertRaises(CompileError, simif.compile_project, project, vhdl_standard="2008")
def test_compile_source_files_continue_on_error(self):
simif = create_simulator_interface()
project = Project()
project.add_library("lib", "lib_path")
write_file("file1.vhd", "")
file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl")
write_file("file2.vhd", "")
file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl")
write_file("file3.vhd", "")
file3 = project.add_source_file("file3.vhd", "lib", file_type="vhdl")
project.add_manual_dependency(file2, depends_on=file1)
def compile_source_file_command(source_file):
"""
Dummy compile command
"""
if source_file == file1:
return ["command1"]
if source_file == file2:
return ["command2"]
if source_file == file3:
return ["command3"]
raise AssertionError
def check_output_side_effect(command, env=None): # pylint: disable=missing-docstring, unused-argument
if command == ["command1"]:
raise subprocess.CalledProcessError(returncode=-1, cmd=command, output="bad stuff")
return ""
simif.compile_source_file_command.side_effect = compile_source_file_command
with mock.patch("vunit.simulator_interface.check_output", autospec=True) as check_output:
check_output.side_effect = check_output_side_effect
printer = MockPrinter()
self.assertRaises(CompileError, simif.compile_source_files,
project, printer=printer, continue_on_error=True)
self.assertEqual(printer.output, """\
Compiling into lib: file3.vhd passed
Compiling into lib: file1.vhd failed
=== Command used: ===
command1
=== Command output: ===
bad stuff
Compiling into lib: file2.vhd skipped
Compile failed
""")
self.assertEqual(len(check_output.mock_calls), 2)
check_output.assert_has_calls([mock.call(["command1"], env=simif.get_env()),
mock.call(["command3"], env=simif.get_env())], any_order=True)
self.assertEqual(project.get_files_in_compile_order(incremental=True), [file1, file2])
def test_compile_project_2002(self, check_output): # pylint: disable=no-self-use
simif = GHDLInterface(prefix="prefix", output_path="")
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002")
simif.compile_project(project)
check_output.assert_called_once_with(
[join("prefix", 'ghdl'), '-a', '--workdir=lib_path', '--work=lib',
'--std=02', '-Plib_path', 'file.vhd'], env=simif.get_env())
def test_compile_project_93(self, run_command): # pylint: disable=no-self-use
simif = GHDLInterface(prefix="prefix")
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="93")
simif.compile_project(project)
run_command.assert_called_once_with(
[join("prefix", 'ghdl'), '-a', '--workdir=lib_path', '--work=lib',
'--std=93', '-Plib_path', 'file.vhd'])
def test_compile_project_2002(self, run_command): # pylint: disable=no-self-use
simif = GHDLInterface(prefix="prefix")
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project, vhdl_standard="2002")
run_command.assert_called_once_with(
[join("prefix", 'ghdl'), '-a', '--workdir=lib_path', '--work=lib',
'--std=02', '-Plib_path', 'file.vhd'],
simif._compile_output_consumer) # pylint: disable=protected-access
def test_compile_project_vhdl_93(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="93")
simif.compile_project(project)
process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
check_args = [join(self.prefix_path, 'vcom'), '-quiet', '-modelsimini',
join(self.output_path, "modelsim.ini"), '-93',
'-work', 'lib', 'file.vhd']
check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_verilog_define(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"})
simif.compile_project(project)
process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
process_args = [join(self.prefix_path, 'vlog'), '-quiet', '-modelsimini',
join(self.output_path, "modelsim.ini"), '-work', 'lib',
'file.v', '-L', 'lib', '+define+defname=defval']
check_output.assert_called_once_with(process_args, env=simif.get_env())
def test_compile_project_vhdl_extra_flags(self, process, check_output):
simif = ActiveHDLInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("activehdl.vcom_flags", ["custom", "flags"])
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
check_output.assert_called_once_with([join('prefix', 'vcom'),
'-quiet',
'-j',
self.output_path,
'custom',
'flags',
'-2008',
'-work',
'lib',
'file.vhd'],
env=simif.get_env())
def test_compile_project_vhdl_extra_flags(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("modelsim.vcom_flags", ["custom", "flags"])
simif.compile_project(project)
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vcom'),
'-quiet',
'-modelsimini',
modelsim_ini,
'custom',
'flags',
'-2008',
'-work',
'lib',
'file.vhd'])
def test_compile_source_files_check_output_error(self):
simif = create_simulator_interface()
simif.compile_source_file_command.return_value = ["command"]
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
with mock.patch("vunit.simulator_interface.check_output", autospec=True) as check_output:
def check_output_side_effect(command, env=None): # pylint: disable=missing-docstring, unused-argument
raise subprocess.CalledProcessError(returncode=-1, cmd=command, output="bad stuff")
check_output.side_effect = check_output_side_effect
printer = MockPrinter()
self.assertRaises(CompileError, simif.compile_source_files, project, printer=printer)
self.assertEqual(printer.output, """\
Compiling into lib: file.vhd failed
=== Command used: ===
command
=== Command output: ===
bad stuff
Compile failed
""")
check_output.assert_called_once_with(["command"], env=simif.get_env())
self.assertEqual(project.get_files_in_compile_order(incremental=True), [source_file])
def test_compile_source_files(self):
simif = create_simulator_interface()
simif.compile_source_file_command.side_effect = iter([["command1"], ["command2"]])
project = Project()
project.add_library("lib", "lib_path")
write_file("file1.vhd", "")
file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl")
write_file("file2.vhd", "")
file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl")
project.add_manual_dependency(file2, depends_on=file1)
with mock.patch("vunit.simulator_interface.run_command", autospec=True) as run_command:
run_command.side_effect = iter([True, True])
simif.compile_source_files(project)
run_command.assert_has_calls([mock.call(["command1"]),
mock.call(["command2"])])
self.assertEqual(project.get_files_in_compile_order(incremental=True), [])
def test_compile_project_verilog(self, run_command, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog")
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
run_command.assert_called_once_with([join("prefix", "irun"), "-f", args_file])
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn UEXPSC",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-work work",
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
"-quiet",
'-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
'-nclibdirname ""',
"-makelib lib",
'"file.v"',
"-endlib",
],
)
self.assertEqual(
read_file(join(self.output_path, "cds.lib")),
"""\
## cds.lib: Defines the locations of compiled libraries.
softinclude cds_root_irun/tools/inca/files/cds.lib
# needed for referencing the library 'basic' for cells 'cds_alias', 'cds_thru' etc. in analog models:
# NOTE: 'virtuoso' executable not found!
# define basic ".../tools/dfII/etc/cdslib/basic"
define lib "lib_path"
define work "%s/libraries/work"
"""
% self.output_path,
)
def test_add_source_file_has_vhdl_standard(self):
write_file("file.vhd", "")
for std in ('93', '2002', '2008'):
project = Project()
project.add_library("lib", "lib_path")
source_file = project.add_source_file("file.vhd",
library_name="lib", file_type='vhdl', vhdl_standard=std)
self.assertEqual(source_file.get_vhdl_standard(), std)
def test_compile_project_verilog(self, process, check_output):
library_cfg = join(self.output_path, "library.cfg")
simif = RivieraProInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog")
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
check_output.assert_called_once_with([
join('prefix', 'vlog'), '-quiet', '-lc', library_cfg, '-work',
'lib', 'file.v', '-l', 'lib'
],
env=simif.get_env())
def test_compile_project_verilog(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog")
simif.compile_project(project)
process.assert_called_once_with(
[join("prefix", "vlib"), "-unix", "lib_path"], env=simif.get_env())
run_command.assert_called_once_with([
join('prefix', 'vlog'), '-quiet', '-modelsimini', modelsim_ini,
'-work', 'lib', 'file.v', '-L', 'lib'
],
env=simif.get_env())
def test_compile_project_vhdl_93(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard="93")
simif.compile_project(project)
process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
check_args = [
join(self.prefix_path, 'vcom'), '-quiet', '-modelsimini',
join(self.output_path, "modelsim.ini"), '-93', '-work', 'lib',
'file.vhd'
]
check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_verilog_define(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v",
"lib",
file_type="verilog",
defines={"defname": "defval"})
simif.compile_project(project)
process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
process_args = [
join(self.prefix_path, 'vlog'), '-quiet', '-modelsimini',
join(self.output_path, "modelsim.ini"), '-work', 'lib', 'file.v',
'-L', 'lib', '+define+defname=defval'
]
check_output.assert_called_once_with(process_args, env=simif.get_env())
def test_compile_project_vhdl(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = RivieraProInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
run_command.assert_called_once_with(
[join('prefix', 'vcom'),
'-quiet',
'-j',
self.output_path,
'-2008',
'-work',
'lib',
'file.vhd'])
def test_compile_project_verilog(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog")
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-sv2k12',
'-lc',
library_cfg,
'-work',
'lib',
'file.v',
'-l', 'lib'])
def test_compile_project_verilog_define(self, check_output,
find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v",
"lib",
file_type="verilog",
defines=dict(defname="defval"))
simif.compile_project(project)
args_file = join(self.output_path,
"irun_compile_verilog_file_lib.args")
check_output.assert_called_once_with(
[join("prefix", "irun"), "-f", args_file], env=simif.get_env())
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn UEXPSC",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-work work",
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' %
join(self.output_path, "irun_compile_verilog_file_lib.log"),
"-quiet",
'-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
"-define defname=defval",
'-nclibdirname ""',
"-makelib lib",
'"file.v"',
"-endlib",
],
)
def test_compile_project_verilog(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog")
simif.compile_project(project)
process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
check_args = [
str(Path(self.prefix_path) / "vlog"),
"-quiet",
"-modelsimini",
str(Path(self.output_path) / "modelsim.ini"),
"-work",
"lib",
"file.v",
"-L",
"lib",
]
check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_vhdl(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project, vhdl_standard="2008")
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
run_command.assert_called_once_with(
[join('prefix', 'vcom'),
'-quiet',
'-j',
self.output_path,
'-2008',
'-work',
'lib',
'file.vhd'],
simif._compile_output_consumer) # pylint: disable=protected-access
def test_compile_project_verilog_define(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"})
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-sv2k12',
'-lc',
library_cfg,
'-work',
'lib',
'file.v',
'-l', 'lib',
'+define+defname=defval'])
def test_compile_project_vhdl(self, process, check_output):
simif = RivieraProInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path, env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path, env=simif.get_env())
check_output.assert_called_once_with(
[join('prefix', 'vcom'),
'-quiet',
'-j',
self.output_path,
'-2008',
'-work',
'lib',
'file.vhd'], env=simif.get_env())
def test_compile_project_extra_flags(self, check_output): # pylint: disable=no-self-use
simif = GHDLInterface(prefix="prefix", output_path="")
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("ghdl.flags", ["custom", "flags"])
simif.compile_project(project)
check_output.assert_called_once_with(
[join("prefix", 'ghdl'), '-a', '--workdir=lib_path', '--work=lib', '--std=08',
'-Plib_path', 'custom', 'flags', 'file.vhd'], env=simif.get_env())
def test_compile_project_vhdl_coverage(self, process, check_output):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
coverage="best",
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project)
process.assert_called_once_with(
[join("prefix", "vlib"), "-unix", "lib_path"], env=simif.get_env())
check_output.assert_called_once_with([
join('prefix', 'vcom'), '-quiet', '-modelsimini', modelsim_ini,
'+cover=best', '-2008', '-work', 'lib', 'file.vhd'
],
env=simif.get_env())
def test_compile_project_extra_flags(self, run_command): # pylint: disable=no-self-use
simif = GHDLInterface(prefix="prefix")
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("ghdl.flags", ["custom", "flags"])
simif.compile_project(project)
run_command.assert_called_once_with(
[join("prefix", 'ghdl'), '-a', '--workdir=lib_path', '--work=lib', '--std=08',
'-Plib_path', 'custom', 'flags', 'file.vhd'])
def test_compile_project_vhdl(self, process, check_output):
simif = RivieraProInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path, env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path, env=simif.get_env())
check_output.assert_called_once_with(
[join('prefix', 'vcom'),
'-quiet',
'-j',
self.output_path,
'-2008',
'-work',
'lib',
'file.vhd'], env=simif.get_env())
def test_compile_project_verilog_define(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = RivieraProInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"})
simif.compile_project(project, vhdl_standard="2008")
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-sv2k12',
'-lc',
library_cfg,
'-work',
'lib',
'file.v',
'-l', 'lib',
'+define+defname=defval'])
def test_compile_project_verilog_include(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = RivieraProInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", include_dirs=["include"])
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-sv2k12',
'-lc',
library_cfg,
'-work',
'lib',
'file.v',
'-l', 'lib',
'+incdir+include'])
def test_compile_project_coverage(self, process, check_output):
library_cfg = join(self.output_path, "library.cfg")
for file_type, coverage_off in product(["vhdl", "verilog"],
[False, True]):
check_output.reset_mock()
simif = RivieraProInterface(prefix="prefix",
output_path=self.output_path,
coverage="bes")
project = Project()
project.add_library("lib", "lib_path")
if file_type == "vhdl":
file_name = "file.vhd"
else:
file_name = "file.v"
write_file(file_name, "")
source_file = project.add_source_file(file_name,
"lib",
file_type=file_type)
if coverage_off:
covargs = []
source_file.set_compile_option("disable_coverage", True)
else:
covargs = ['-coverage', 'bes']
simif.compile_project(project)
process.assert_any_call(
[join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with(
[join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
if file_type == "vhdl":
check_output.assert_called_once_with(
[join('prefix', 'vcom'), '-quiet', '-j', self.output_path
] + covargs + ['-2008', '-work', 'lib', 'file.vhd'],
env=simif.get_env())
elif file_type == "verilog":
check_output.assert_called_once_with(
[join('prefix', 'vlog'), '-quiet', '-lc', library_cfg] +
covargs + ['-work', 'lib', 'file.v', '-l', 'lib'],
env=simif.get_env())
else:
assert False
def test_compile_project_vhdl_93(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard="93")
simif.compile_project(project)
process.assert_called_once_with(
[join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([
join('prefix', 'vcom'), '-quiet', '-modelsimini', modelsim_ini,
'-93', '-work', 'lib', 'file.vhd'
])
def test_compile_project_verilog_include(self, process, check_output):
library_cfg = join(self.output_path, "library.cfg")
simif = RivieraProInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", include_dirs=["include"])
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path, env=None)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path, env=simif.get_env())
check_output.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-lc',
library_cfg,
'-work',
'lib',
'file.v',
'-l', 'lib',
'+incdir+include'], env=simif.get_env())
def test_compile_project_system_verilog(self, check_output, find_cds_root_irun, find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix", output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.sv", "")
project.add_source_file("file.sv", "lib", file_type="systemverilog")
simif.compile_project(project)
args_file = join(self.output_path, "irun_compile_verilog_file_lib.args")
check_output.assert_called_once_with(
[join('prefix', 'irun'), '-f', args_file],
env=simif.get_env())
self.assertEqual(read_file(args_file).splitlines(),
['-compile',
'-nocopyright',
'-licqueue',
'-nowarn UEXPSC',
'-nowarn DLCPTH',
'-nowarn DLCVAR',
'-work work',
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' % join(self.output_path, "irun_compile_verilog_file_lib.log"),
'-quiet',
'-incdir "cds_root_irun/tools/spectre/etc/ahdl/"',
'-nclibdirname ""',
'-makelib lib',
'"file.sv"',
'-endlib'])
self.assertEqual(read_file(join(self.output_path, "cds.lib")), """\
## cds.lib: Defines the locations of compiled libraries.
softinclude cds_root_irun/tools/inca/files/cds.lib
# needed for referencing the library 'basic' for cells 'cds_alias', 'cds_thru' etc. in analog models:
# NOTE: 'virtuoso' executable not found!
# define basic ".../tools/dfII/etc/cdslib/basic"
define lib "lib_path"
define work "%s/libraries/work"
""" % self.output_path)
def test_compile_project_vhdl_2002(self, check_output, find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard=VHDL.standard("2002"))
simif.compile_project(project)
args_file = str(
Path(self.output_path) / "irun_compile_vhdl_file_lib.args")
check_output.assert_called_once_with(
[str(Path("prefix") / "irun"), "-f", args_file],
env=simif.get_env())
self.assertEqual(
read_file(args_file).splitlines(),
[
"-compile",
"-nocopyright",
"-licqueue",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-v200x -extv200x",
"-work work",
'-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"),
'-log "%s"' %
str(Path(self.output_path) / "irun_compile_vhdl_file_lib.log"),
"-quiet",
'-nclibdirname "."',
"-makelib lib_path",
'"file.vhd"',
"-endlib",
],
)
def test_compile_source_files_run_command_error(self):
simif = create_simulator_interface()
simif.compile_source_file_command.return_value = ["command"]
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
with mock.patch("vunit.simulator_interface.run_command", autospec=True) as run_command:
run_command.return_value = False
self.assertRaises(CompileError, simif.compile_source_files, project)
run_command.assert_called_once_with(["command"])
self.assertEqual(project.get_files_in_compile_order(incremental=True), [source_file])
def test_compile_source_files(self):
simif = create_simulator_interface()
simif.compile_source_file_command.side_effect = iter([["command1"],
["command2"]])
project = Project()
project.add_library("lib", "lib_path")
write_file("file1.vhd", "")
file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl")
write_file("file2.vhd", "")
file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl")
project.add_manual_dependency(file2, depends_on=file1)
with mock.patch("vunit.simulator_interface.run_command",
autospec=True) as run_command:
run_command.side_effect = iter([True, True])
simif.compile_source_files(project)
run_command.assert_has_calls([
mock.call(["command1"], env=simif.get_env()),
mock.call(["command2"], env=simif.get_env())
])
self.assertEqual(project.get_files_in_compile_order(incremental=True),
[])
def test_compile_project_verilog_include(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", include_dirs=["include"])
simif.compile_project(project, vhdl_standard="2008")
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-sv2k12',
'-lc',
library_cfg,
'-work',
'lib',
'file.v',
'-l', 'lib',
'+incdir+include'],
simif._compile_output_consumer) # pylint: disable=protected-access
def test_compile_project_verilog_define(self, _find_prefix, process,
check_output):
library_cfg = str(Path(self.output_path) / "library.cfg")
simif = RivieraProInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v",
"lib",
file_type="verilog",
defines={"defname": "defval"})
simif.compile_project(project)
process.assert_any_call(
[str(Path("prefix") / "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env(),
)
process.assert_called_with(
[str(Path("prefix") / "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env(),
)
check_output.assert_called_once_with(
[
str(Path("prefix") / "vlog"),
"-quiet",
"-lc",
library_cfg,
"-work",
"lib",
"file.v",
"-l",
"lib",
"+define+defname=defval",
],
env=simif.get_env(),
)
def test_compile_source_files(self):
simif = create_simulator_interface()
simif.compile_source_file_command.side_effect = iter([["command1"], ["command2"]])
project = Project()
project.add_library("lib", "lib_path")
write_file("file1.vhd", "")
file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl")
write_file("file2.vhd", "")
file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl")
project.add_manual_dependency(file2, depends_on=file1)
with mock.patch("vunit.simulator_interface.check_output", autospec=True) as check_output:
check_output.side_effect = iter(["", ""])
printer = MockPrinter()
simif.compile_source_files(project, printer=printer)
check_output.assert_has_calls([mock.call(["command1"], env=simif.get_env()),
mock.call(["command2"], env=simif.get_env())])
self.assertEqual(printer.output, """\
Compiling into lib: file1.vhd passed
Compiling into lib: file2.vhd passed
Compile passed
""")
self.assertEqual(project.get_files_in_compile_order(incremental=True), [])
def test_compile_project_93(self, check_output):
simif = GHDLInterface(prefix="prefix", output_path="")
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard=VHDL.standard("93"))
simif.compile_project(project)
check_output.assert_called_once_with(
[
str(Path("prefix") / "ghdl"),
"-a",
"--workdir=lib_path",
"--work=lib",
"--std=93",
"-Plib_path",
"file.vhd",
],
env=simif.get_env(),
)
def test_compile_project_verilog_include(self, process, check_output):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v",
"lib",
file_type="verilog",
include_dirs=["include"])
simif.compile_project(project)
process.assert_any_call(
[join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env(),
)
process.assert_called_with(
[join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env(),
)
check_output.assert_called_once_with(
[
join("prefix", "vlog"),
"-quiet",
"-lc",
library_cfg,
"-work",
"lib",
"file.v",
"-l",
"lib",
"+incdir+include",
],
env=simif.get_env(),
)
def test_compile_project_vhdl_2002(self, process, check_output):
simif = ModelSimInterface(
prefix=self.prefix_path, output_path=self.output_path, persistent=False
)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file(
"file.vhd", "lib", file_type="vhdl", vhdl_standard=VHDL.standard("2002")
)
simif.compile_project(project)
process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
check_args = [
join(self.prefix_path, "vcom"),
"-quiet",
"-modelsimini",
join(self.output_path, "modelsim.ini"),
"-2002",
"-work",
"lib",
"file.vhd",
]
check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_system_verilog(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.sv", "")
project.add_source_file("file.sv", "lib", file_type="systemverilog")
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-lc',
library_cfg,
'-work',
'lib',
'file.sv',
'-l', 'lib'],
env=simif.get_env())
def test_compile_project_extra_flags(self, run_command): # pylint: disable=no-self-use
simif = GHDLInterface(prefix="prefix")
write_file("file.vhd", "")
project = Project()
project.add_library("lib", "lib_path")
source_file = project.add_source_file("file.vhd",
"lib",
file_type="vhdl")
source_file.set_compile_option("ghdl.flags", ["custom", "flags"])
simif.compile_project(project, vhdl_standard="2008")
run_command.assert_called_once_with([
join("prefix", 'ghdl'), '-a', '--workdir=lib_path', '--work=lib',
'--std=08', '-Plib_path', 'custom', 'flags', 'file.vhd'
])
def test_compile_project_verilog_define(self, process, run_command):
write_file("modelsim.ini", """
[Library]
""")
modelsim_ini = join(self.output_path, "modelsim.ini")
simif = ModelSimInterface(prefix="prefix",
modelsim_ini=modelsim_ini,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"})
simif.compile_project(project, vhdl_standard="2008")
process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"])
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-sv',
'-quiet',
'-modelsimini',
modelsim_ini,
'-work',
'lib',
'file.v',
'-L', 'lib',
'+define+defname=defval'])
def test_compile_source_files_minimal_subset(self):
simif = create_simulator_interface()
project = Project()
project.add_library("lib", "lib_path")
write_file("file1.vhd", "")
file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl")
with mock.patch(
"vunit.project.Project.get_minimal_file_set_in_compile_order", autospec=True
) as target_function:
target_function.return_value = []
printer = MockPrinter()
simif.compile_source_files(project, printer=printer, target_files=[file1])
simif.compile_source_files(project, printer=printer, target_files=[file1])
self.assertTrue(target_function.called)
def test_compile_source_files_continue_on_error(self):
simif = create_simulator_interface()
project = Project()
project.add_library("lib", "lib_path")
write_file("file1.vhd", "")
file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl")
write_file("file2.vhd", "")
file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl")
write_file("file3.vhd", "")
file3 = project.add_source_file("file3.vhd", "lib", file_type="vhdl")
project.add_manual_dependency(file2, depends_on=file1)
def compile_source_file_command(source_file):
if source_file == file1:
return ["command1"]
elif source_file == file2:
return ["command2"]
elif source_file == file3:
return ["command3"]
def run_command_side_effect(command):
if command == ["command1"]:
return False
else:
return True
simif.compile_source_file_command.side_effect = compile_source_file_command
with mock.patch("vunit.simulator_interface.run_command", autospec=True) as run_command:
run_command.side_effect = run_command_side_effect
self.assertRaises(CompileError, simif.compile_source_files, project, continue_on_error=True)
self.assertEqual(len(run_command.mock_calls), 2)
run_command.assert_has_calls([mock.call(["command1"]),
mock.call(["command3"])], any_order=True)
self.assertEqual(project.get_files_in_compile_order(incremental=True), [file1, file2])
def test_add_source_file_has_no_parse_verilog(self):
for no_parse in (True, False):
project = Project()
file_name = "file.v"
write_file(file_name, """
module mod;
endmodule
""")
project.add_library("lib", "work_path")
source_file = project.add_source_file(file_name,
"lib",
file_type=file_type_of(file_name),
no_parse=no_parse)
self.assertEqual(len(source_file.design_units), int(not no_parse))
def test_compile_source_files_create_command_error(self):
simif = create_simulator_interface()
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
with mock.patch("vunit.sim_if.check_output", autospec=True) as check_output:
check_output.return_value = ""
def raise_compile_error(source_file): # pylint: disable=unused-argument
raise CompileError
simif.compile_source_file_command.side_effect = raise_compile_error
self.assertRaises(CompileError, simif.compile_source_files, project)
self.assertEqual(project.get_files_in_compile_order(incremental=True), [source_file])
def test_compile_source_files_create_command_error(self):
simif = create_simulator_interface()
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
with mock.patch("vunit.simulator_interface.run_command", autospec=True) as run_command:
run_command.return_value = True
def raise_compile_error(*args, **kwargs):
raise CompileError
simif.compile_source_file_command.side_effect = raise_compile_error
self.assertRaises(CompileError, simif.compile_source_files, project)
self.assertEqual(project.get_files_in_compile_order(incremental=True), [source_file])
