def getStateSequence(self, sgl):
print 'IOs : ', self.inputs, self.outputs
signalVectorList = self.inputs + self.outputs
start = 0
dictState = dict([])
stgList = []
for line in sgl:
if ('.SG' in line):
start = 1
elif ('.end' in line):
start = 0
elif (start == 1 and line != '' and line != ' '):
stgList = func.trimList(line.split(' '))
print stgList
if (len(stgList) != 0):
if (stgList[0] not in dictState):
dictState[stgList[0]] = []
dictState[stgList[0]].append([stgList[1], stgList[2]])
return dictState
def getStateSequence(self, sgl):
print 'IOs : ', self.inputs, self.outputs
signalVectorList = self.inputs+self.outputs
start = 0
dictState = dict([])
stgList = []
for line in sgl:
if('.SG' in line):
start = 1
elif('.end' in line):
start = 0
elif(start == 1 and line!='' and line!=' '):
stgList = func.trimList(line.split(' '))
print stgList
if(len(stgList)!=0):
if(stgList[0] not in dictState):
dictState[stgList[0]] = []
dictState[stgList[0]].append([stgList[1], stgList[2]])
return dictState
def reverifyCge_and_stabeStates(self, inputs, outputs, internals,
init_state, sgList, sgl):
fsg = open(sys.argv[1].split('.')[0] + '.sg', 'r+')
start = 0
specState = dict([])
sgfile = []
specStateDict = dict([])
specSignals = inputs + outputs + internals
self.signalSpec = inputs + outputs + internals
outSignals = outputs + internals
intoutSignals = outputs + self.internals
onlyInternals = []
for i in self.internals:
if (i not in internals):
onlyInternals.append(i)
#onlyInternals = self.internals - internals
print 'Only Internals:', onlyInternals
cgeVerifyTag = dict([])
for line in fsg:
if ('.SG' in line):
start = 1
elif ('.end' in line):
start = 0
elif (start == 1 and len(func.trimList(line.split(' '))) != 0):
sgfile.append(func.trimList(line.split(' ')))
for i in sgfile:
print 'hey', i[0]
if (i[0] not in specState):
specState[tuple(i[0])] = [i[1], tuple(i[2])]
else:
specState[tuple(i[0])].append([i[1], tuple(i[2])])
tempState = dict([])
for j in range(0, len(specSignals)):
print 'Here: ', specSignals[j], j
tempState[specSignals[j]] = i[0][j]
specStateDict[tuple(i[0])] = tempState
for i, v in specStateDict.iteritems():
print i, v, '\n'
ExcSignals = self.getStateEval(specSignals, v, 1)
print 'ExcSignals: ', ExcSignals
for out in outSignals:
excited = 0
##---- output not enabled in impl, output should not be enabled in spec as well
if (ExcSignals[out] == v[out]):
if ((out + '+' not in specState[i][0])
and (out + '-' not in specState[i])
and (out not in specState[i][0])):
cgeVerifyTag[i] = 'PASS STATE1'
else:
cgeVerifyTag[i] = 'FAIL STATE1'
elif (ExcSignals[out] != v[out]):
if (ExcSignals[out] == '1'
and (out + '+' not in specState[i][0])):
cgeVerifyTag[i] = 'FAIL STATE2'
elif (ExcSignals[out] == '0'
and (out + '-' not in specState[i][0])):
cgeVerifyTag[i] = 'FAIL STATE3' + str(
specState[i][0]) + out
else:
cgeVerifyTag[i] = 'PASS STATE2'
for i, v in specState.iteritems():
print 'SpecstateItems: ', i, v
for i, v in cgeVerifyTag.iteritems():
print specStateDict[i], i, v
""" if( v == 'FAIL STATE ):
setReturn = 1
if(setReturn==1):
return 'CGE Verification Failed"""
################## Stable States ####################
##---- Get FanIn of each output and internal nodes -------------
'''FanInDict = dict([])
def reverifyCge_and_stabeStates( self, inputs, outputs, internals, init_state, sgList, sgl ):
fsg = open(sys.argv[1].split('.')[0]+'.sg', 'r+')
start = 0
specState = dict([])
sgfile = []
specStateDict = dict([])
specSignals = inputs+outputs+internals
self.signalSpec = inputs+outputs+internals
outSignals = outputs+internals
intoutSignals = outputs+self.internals
onlyInternals = []
for i in self.internals:
if(i not in internals):
onlyInternals.append(i)
#onlyInternals = self.internals - internals
print 'Only Internals:', onlyInternals
cgeVerifyTag = dict([])
for line in fsg:
if('.SG' in line):
start = 1
elif('.end' in line):
start = 0
elif(start==1 and len(func.trimList(line.split(' ')))!=0):
sgfile.append(func.trimList(line.split(' ')))
for i in sgfile:
print 'hey',i[0]
if(i[0] not in specState):
specState[tuple(i[0])] = [i[1],tuple(i[2])]
else:
specState[tuple(i[0])].append([i[1],tuple(i[2])])
tempState = dict([])
for j in range(0,len(specSignals)):
print 'Here: ', specSignals[j], j
tempState[specSignals[j]] = i[0][j]
specStateDict[tuple(i[0])] = tempState
for i, v in specStateDict.iteritems():
print i, v,'\n'
ExcSignals = self.getStateEval(specSignals, v,1)
print 'ExcSignals: ', ExcSignals
for out in outSignals:
excited = 0
##---- output not enabled in impl, output should not be enabled in spec as well
if(ExcSignals[out] == v[out]):
if((out+'+' not in specState[i][0]) and (out+'-' not in specState[i]) and (out not in specState[i][0])):
cgeVerifyTag[i] = 'PASS STATE1'
else:
cgeVerifyTag[i] = 'FAIL STATE1'
elif(ExcSignals[out] != v[out]):
if( ExcSignals[out]=='1' and (out+'+' not in specState[i][0])):
cgeVerifyTag[i] = 'FAIL STATE2'
elif( ExcSignals[out]=='0' and (out+'-' not in specState[i][0])):
cgeVerifyTag[i] = 'FAIL STATE3'+str(specState[i][0])+out
else:
cgeVerifyTag[i] = 'PASS STATE2'
for i,v in specState.iteritems():
print 'SpecstateItems: ', i, v
for i, v in cgeVerifyTag.iteritems():
print specStateDict[i], i, v
""" if( v == 'FAIL STATE ):
setReturn = 1
if(setReturn==1):
return 'CGE Verification Failed"""
################## Stable States ####################
##---- Get FanIn of each output and internal nodes -------------
'''FanInDict = dict([])
