def _entPort2CompPort(e, p):
port = Port()
port.name = p.name
port.direction = p.direction.name.lower()
port.type = WireTypeDef()
t = port.type
dt = p._dtype
def createTmpVar(suggestedName, dtype):
pass
t.typeName = VhdlSerializer.HdlType(dt, createTmpVar)
try:
t.typeName = t.typeName[:t.typeName.index('(')]
except ValueError:
pass
if dt == BIT:
port.vector = False
elif isinstance(dt, Bits):
port.vector = dt.constrain.staticEval().val
t.viewNameRefs = [
"xilinx_vhdlsynthesis", "xilinx_vhdlbehavioralsimulation"
]
return port
def serializeType(self, hdlType: HdlType) -> str:
"""
:see: doc of method on parent class
"""
def createTmpVar(suggestedName, dtype):
raise NotImplementedError(
"Can not seraialize hdl type %r into"
"ipcore format" % (hdlType))
return VhdlSerializer.HdlType(hdlType, VhdlSerializer.getBaseContext())
def _entPort2CompPort(e, p):
port = Port()
port.name = p.name
port.direction = p.direction.name.lower()
port.type = WireTypeDef()
t = port.type
dt = p._dtype
t.typeName = VhdlSerializer.HdlType(dt,
VhdlSerializer.getBaseContext())
try:
t.typeName = t.typeName[:t.typeName.index('(')]
except ValueError:
pass
if dt == BIT:
port.vector = False
elif isinstance(dt, Bits):
port.vector = [evalParam(dt.width) - 1, hInt(0)]
t.viewNameRefs = [
"xilinx_vhdlsynthesis", "xilinx_vhdlbehavioralsimulation"
]
return port