def quartus_add_interface_port(self, buff: List[str], intfName: str,
signal, logicName: str):
"""
Add subinterface to Quartus interface
:param buff: line buffer for output
:param intfName: name of top interface
:param signal: subinterface to create port for
:param logicName: name of port in Quartus
"""
d = signal._direction
if d == INTF_DIRECTION.MASTER:
dir_ = "Output"
elif d == INTF_DIRECTION.SLAVE:
dir_ = "Input"
else:
raise ValueError(d)
width = signal._dtype.width
if isinstance(width, int):
width = str(width)
else:
ctx = VhdlSerializer.getBaseContext()
def createTmpVar(suggestedName, dtype):
raise NotImplementedError(
"Width value can not be converted do ipcore format (%r)",
width)
ctx.createTmpVarFn = createTmpVar
width = VivadoTclExpressionSerializer.asHdl(
width.staticEval(), ctx)
buff.append("add_interface_port %s %s %s %s %s" %
(intfName, signal._sigInside.name, logicName, dir_, width))
def strStructureCmp(self, cont, tmpl):
if not isinstance(cont, str):
cont = VhdlSerializer.asHdl(cont, VhdlSerializer.getBaseContext())
_tmpl = rmWhitespaces.sub(" ", tmpl).strip()
_cont = rmWhitespaces.sub(" ", cont).strip()
self.assertEqual(_tmpl, _cont)
def test_indexOps(self):
c, interf = IndexOps()
_, arch = list(c.synthesize("indexOps", interf, DummyPlatform()))
s = VhdlSerializer.Architecture(arch, VhdlSerializer.getBaseContext())
self.assertNotIn("sig_", s)
def strStructureCmp(self, cont, tmpl):
if not isinstance(cont, str):
cont = VhdlSerializer.asHdl(cont, VhdlSerializer.getBaseContext())
_tmpl = rmWhitespaces.sub(" ", tmpl).strip()
_cont = rmWhitespaces.sub(" ", cont).strip()
self.assertEqual(_tmpl, _cont)
def netlistToVhdlStr(name, netlist, interfaces):
for s in interfaces:
s._interface = True
ctx = VhdlSerializer.getBaseContext()
return "\n".join([VhdlSerializer.asHdl(o, ctx)
for o in netlist.synthesize(name, interfaces, DummyPlatform())
])
def netlistToVhdlStr(name, netlist, interfaces):
for s in interfaces:
s._interface = True
ctx = VhdlSerializer.getBaseContext()
return "\n".join([
VhdlSerializer.asHdl(o, ctx)
for o in netlist.synthesize(name, interfaces, DummyPlatform())
])
def serializeType(self, hdlType: HdlType) -> str:
"""
:see: doc of method on parent class
"""
def createTmpVar(suggestedName, dtype):
raise NotImplementedError(
"Can not seraialize hdl type %r into"
"ipcore format" % (hdlType))
return VhdlSerializer.HdlType(hdlType, VhdlSerializer.getBaseContext())
def addWidthParam(self, thisIntf, name, value):
ctx = VhdlSerializer.getBaseContext()
def createTmpVar(suggestedName, dtype):
raise NotImplementedError(
"Value of generic %s can not be converted do ipcore format (%r)",
name, value)
ctx.createTmpVarFn = createTmpVar
v = VivadoTclExpressionSerializer.asHdl(value.staticEval(), ctx)
p = self.addSimpleParam(thisIntf, "ADDR_WIDTH", v)
if isinstance(value, RtlSignalBase):
p.value.resolve = "user"
def getExprVal(self, val, do_eval=False):
"""
:see: doc of method on parent class
"""
ctx = VhdlSerializer.getBaseContext()
def createTmpVar(suggestedName, dtype):
raise NotImplementedError(
"Width value can not be converted do ipcore format (%r)",
val)
ctx.createTmpVarFn = createTmpVar
if do_eval:
val = val.staticEval()
val = VivadoTclExpressionSerializer.asHdl(val, ctx)
return val
def dump(self, dumpFile=sys.stdout):
for proc in self.tbArch.processes:
proc.statements.append(WaitStm(None))
hasToBeOpened = isinstance(dumpFile, str)
if hasToBeOpened:
_dumpFile = open(dumpFile, 'w')
else:
_dumpFile = dumpFile
ctx = VhdlSerializer.getBaseContext()
ctx.scope.setLevel(2)
VhdlSerializer.Entity_prepare(self.tbArch.components[0], ctx)
ctx.scope.setLevel(1)
_dumpFile.write(VhdlSerializer.formatter(
VhdlSerializer.Entity(self.tbEnt, ctx)))
_dumpFile.write(VhdlSerializer.formatter(
VhdlSerializer.Architecture(self.tbArch, ctx)))
def _entPort2CompPort(e, p):
port = Port()
port.name = p.name
port.direction = p.direction.name.lower()
port.type = WireTypeDef()
t = port.type
dt = p._dtype
t.typeName = VhdlSerializer.HdlType(dt,
VhdlSerializer.getBaseContext())
try:
t.typeName = t.typeName[:t.typeName.index('(')]
except ValueError:
pass
if dt == BIT:
port.vector = False
elif isinstance(dt, Bits):
port.vector = [evalParam(dt.width) - 1, hInt(0)]
t.viewNameRefs = [
"xilinx_vhdlsynthesis", "xilinx_vhdlbehavioralsimulation"
]
return port
def __repr__(self, indent=0, withAddr=None, expandStructs=False):
"""
:param indent: number of indentation
:param withAddr: if is not None is used as a additional
information about on which address this type is stored
(used only by HStruct)
:param expandStructs: expand HStructTypes (used by HStruct and HArray)
"""
c = self.width
if isinstance(c, int):
constr = "%dbits" % c
else:
from hwt.serializer.vhdl.serializer import VhdlSerializer
ctx = VhdlSerializer.getBaseContext()
constr = VhdlSerializer.asHdl(self.width, ctx)
constr = "%s, %dbits" % (constr, self.bit_length())
if self.signed:
constr += ", signed"
elif self.signed is False:
constr += ", unsigned"
return "%s<%s, %s>" % (getIndent(indent), self.__class__.__name__,
constr)
def assertStrEq(self, first, second, msg=None):
ctx = VhdlSerializer.getBaseContext()
first = VhdlSerializer.asHdl(first, ctx).replace(" ", "")
unittest.TestCase.assertEqual(self, first, second, msg=msg)
def assertStrEq(self, first, second, msg=None):
ctx = VhdlSerializer.getBaseContext()
first = VhdlSerializer.asHdl(first, ctx).replace(" ", "")
unittest.TestCase.assertEqual(self, first, second, msg=msg)