def scriptCheckpoints(options, maxtick, cptdir): if options.at_instruction or options.simpoint: checkpoint_inst = options.take_checkpoints # maintain correct offset if we restored from some instruction if options.checkpoint_restore != None: checkpoint_inst += options.checkpoint_restore print "Creating checkpoint at inst:%d" % (checkpoint_inst) exit_event = m5.simulate() exit_cause = exit_event.getCause() print "exit cause = %s" % exit_cause # skip checkpoint instructions should they exist while exit_cause == "checkpoint": exit_event = m5.simulate() exit_cause = exit_event.getCause() if exit_cause == "a thread reached checkpoint inst number" or \ exit_cause == "sp simulation reached the interval size": m5.checkpoint(joinpath(cptdir, "cpt.%s.%d" % \ (options.bench, checkpoint_inst))) print "Checkpoint written." else: when, period = options.take_checkpoints.split(",", 1) when = int(when) period = int(period) num_checkpoints = 0 exit_event = m5.simulate(when - m5.curTick()) exit_cause = exit_event.getCause() while exit_cause == "checkpoint": exit_event = m5.simulate(when - m5.curTick()) exit_cause = exit_event.getCause() if exit_cause == "simulate() limit reached": m5.checkpoint(joinpath(cptdir, "cpt.%d")) num_checkpoints += 1 sim_ticks = when max_checkpoints = options.max_checkpoints while num_checkpoints < max_checkpoints and \ exit_cause == "simulate() limit reached": if (sim_ticks + period) > maxtick: exit_event = m5.simulate(maxtick - sim_ticks) exit_cause = exit_event.getCause() break else: exit_event = m5.simulate(period) exit_cause = exit_event.getCause() sim_ticks += period while exit_event.getCause() == "checkpoint": exit_event = m5.simulate(sim_ticks - m5.curTick()) if exit_event.getCause() == "simulate() limit reached": m5.checkpoint(joinpath(cptdir, "cpt.%d")) num_checkpoints += 1 return exit_event
def benchCheckpoints_sync(options, maxreltick, cptdir): import socket quantum,port,host = options.sync.split(',') sync_quantum = long(quantum) TCP_IP = host TCP_PORT = int(port) BUFFER_SIZE = 1 pre_tick = m5.curTick() try: s = socket.socket(socket.AF_INET, socket.SOCK_STREAM) s.connect((TCP_IP, TCP_PORT)) exit_event = m5.simulate(sync_quantum) exit_cause = exit_event.getCause() total_tick_simulated = sync_quantum num_checkpoints = 0 max_checkpoints = options.max_checkpoints s.send("R") data = s.recv(BUFFER_SIZE) while total_tick_simulated <= maxreltick and\ (exit_cause == "simulate() limit reached" or\ exit_cause == "checkpoint"): if exit_cause == "checkpoint": m5.simulate(pre_tick + sync_quantum - m5.curTick()) # send "C" to barrier to notify that we should take a # checkpoint at the begining of next quantum s.send("C") else: s.send("R") data = s.recv(BUFFER_SIZE) pre_tick = m5.curTick() exit_event = m5.simulate(sync_quantum) total_tick_simulated += sync_quantum # if we receive a "C" from barrier, start to dump a checkpoint if data == "C" : m5.checkpoint(joinpath(cptdir, "cpt.%d")) num_checkpoints += 1 if num_checkpoints == max_checkpoints: exit_cause = "maximum %d checkpoints dropped"\ % max_checkpoints break exit_cause = exit_event.getCause() except KeyboardInterrupt: sys.exit() except Exception as ex: print "exception %s occured." %(ex.args[1]) sys.exit() return exit_event
def run(checkpoint_dir=m5.options.outdir): # start simulation (and drop checkpoints when requested) while True: event = m5.simulate() exit_msg = event.getCause() if exit_msg == "checkpoint": print("Dropping checkpoint at tick %d" % m5.curTick()) cpt_dir = os.path.join(checkpoint_dir, "cpt.%d" % m5.curTick()) m5.checkpoint(cpt_dir) print("Checkpoint done.") else: print(exit_msg, " @ ", m5.curTick()) break sys.exit(event.getCode())
def run_test(root): """Default run_test implementations. Scripts can override it.""" # instantiate configuration m5.instantiate() # simulate until program terminates exit_event = m5.simulate(maxtick) print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause())
def run(args): cptdir = m5.options.outdir if args.checkpoint: print "Checkpoint directory: %s" % cptdir while True: event = m5.simulate() exit_msg = event.getCause() if exit_msg == "checkpoint": print "Dropping checkpoint at tick %d" % m5.curTick() cpt_dir = os.path.join(m5.options.outdir, "cpt.%d" % m5.curTick()) m5.checkpoint(os.path.join(cpt_dir)) print "Checkpoint done." else: print exit_msg, " @ ", m5.curTick() break sys.exit(event.getCode())
def benchCheckpoints(options, maxtick, cptdir): exit_event = m5.simulate(maxtick - m5.curTick()) exit_cause = exit_event.getCause() num_checkpoints = 0 max_checkpoints = options.max_checkpoints while exit_cause == "checkpoint": m5.checkpoint(joinpath(cptdir, "cpt.%d")) num_checkpoints += 1 if num_checkpoints == max_checkpoints: exit_cause = "maximum %d checkpoints dropped" % max_checkpoints break exit_event = m5.simulate(maxtick - m5.curTick()) exit_cause = exit_event.getCause() return exit_event
def repeatSwitch(testsys, repeat_switch_cpu_list, maxtick, switch_freq): print "starting switch loop" while True: exit_event = m5.simulate(switch_freq) exit_cause = exit_event.getCause() if exit_cause != "simulate() limit reached": return exit_event m5.switchCpus(testsys, repeat_switch_cpu_list) tmp_cpu_list = [] for old_cpu, new_cpu in repeat_switch_cpu_list: tmp_cpu_list.append((new_cpu, old_cpu)) repeat_switch_cpu_list = tmp_cpu_list if (maxtick - m5.curTick()) <= switch_freq: exit_event = m5.simulate(maxtick - m5.curTick()) return exit_event
def run_test(root): """gpu test requires a specialized run_test implementation to set up the mmio space.""" # instantiate configuration m5.instantiate() # Now that the system has been constructed, setup the mmio space root.system.cpu[0].workload[0].map(0x10000000, 0x200000000, 4096) # simulate until program terminates exit_event = m5.simulate(maxtick) print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
def handleEventPlayback(controller, options): if not options.playback_file: return from controller import playback # Use all non-empty colon-separated words as event names. events = filter(len, options.playback.split(':')) offset = options.playback_offset or m5.curTick() # The scheduleRecordedEvents() function uses m5.ticks.fromSeconds() which # needs a fixed simulator frequency. Because this function is called early # during M5 initialization the frequency is not yet fixed by M5 itself. m5.ticks.fixGlobalFrequency() playback.scheduleRecordedEvents(m5.event.mainq, controller, options.playback_file, events, 1.0/options.playback_speed, offset)
def main(): parser = argparse.ArgumentParser(epilog=__doc__) parser.add_argument("commands_to_run", metavar="command(s)", nargs='*', help="Command(s) to run") parser.add_argument("--cpu", type=str, choices=cpu_types.keys(), default="atomic", help="CPU model to use") parser.add_argument("--cpu-freq", type=str, default="4GHz") parser.add_argument("--num-cores", type=int, default=1, help="Number of CPU cores") parser.add_argument("--mem-type", default="DDR3_1600_8x8", choices=MemConfig.mem_names(), help = "type of memory to use") parser.add_argument("--mem-channels", type=int, default=2, help = "number of memory channels") parser.add_argument("--mem-ranks", type=int, default=None, help = "number of memory ranks per channel") parser.add_argument("--mem-size", action="store", type=str, default="2GB", help="Specify the physical memory size") args = parser.parse_args() # Create a single root node for gem5's object hierarchy. There can # only exist one root node in the simulator at any given # time. Tell gem5 that we want to use syscall emulation mode # instead of full system mode. root = Root(full_system=False) # Populate the root node with a system. A system corresponds to a # single node with shared memory. root.system = create(args) # Instantiate the C++ object hierarchy. After this point, # SimObjects can't be instantiated anymore. m5.instantiate() # Start the simulator. This gives control to the C++ world and # starts the simulator. The returned event tells the simulation # script why the simulator exited. event = m5.simulate() # Print the reason for the simulation exit. Some exit codes are # requests for service (e.g., checkpoints) from the simulation # script. We'll just ignore them here and exit. print(event.getCause(), " @ ", m5.curTick()) sys.exit(event.getCode())
def main(): parser = argparse.ArgumentParser(description="Simple system using HMC as\ main memory") HMC.add_options(parser) add_options(parser) options = parser.parse_args() # build the system root = build_system(options) # instantiate all of the objects we've created so far m5.instantiate() print("Beginning simulation!") event = m5.simulate(10000000000) m5.stats.dump() print('Exiting @ tick %i because %s (exit code is %i)' % (m5.curTick(), event.getCause(), event.getCode())) print("Done")
def dump(): '''Dump all statistics data to the registered outputs''' from m5 import options curTick = m5.curTick() global lastDump assert lastDump <= curTick if lastDump == curTick: return lastDump = curTick internal.stats.processDumpQueue() prepare() # Prodromou: Based on a M5 flag, filter stats or not if options.use_stat_flags: stat_print_flags = [ "committedInsts", "readReqs", "writeReqs", "system.mem_ctrls.avgQLat", "microThreads", "thinkingTime", "readRowHitRate" ] for output in outputList: if output.valid(): output.begin() for stat in stats_list: for flag in stat_print_flags: if flag in stat.name: output.visit(stat) output.end() else: for output in outputList: if output.valid(): output.begin() for stat in stats_list: output.visit(stat) output.end()
def restoreSimpointCheckpoint(): exit_event = m5.simulate() exit_cause = exit_event.getCause() if exit_cause == "simpoint starting point found": print "Warmed up! Dumping and resetting stats!" m5.stats.dump() m5.stats.reset() exit_event = m5.simulate() exit_cause = exit_event.getCause() if exit_cause == "simpoint starting point found": print "Done running SimPoint!" sys.exit(exit_event.getCode()) print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_cause) sys.exit(exit_event.getCode())
def dump(): '''Dump all statistics data to the registered outputs''' curTick = m5.curTick() global lastDump assert lastDump <= curTick if lastDump == curTick: return lastDump = curTick prepare() for output in outputList: if output.valid(): output.begin() for stat in stats_list: output.visit(stat) output.end()
def takeSimpointCheckpoints(simpoints, interval_length, cptdir): num_checkpoints = 0 index = 0 last_chkpnt_inst_count = -1 for simpoint in simpoints: interval, weight, starting_inst_count, actual_warmup_length = simpoint if starting_inst_count == last_chkpnt_inst_count: # checkpoint starting point same as last time # (when warmup period longer than starting point) exit_cause = "simpoint starting point found" code = 0 else: exit_event = m5.simulate() # skip checkpoint instructions should they exist while exit_event.getCause() == "checkpoint": print "Found 'checkpoint' exit event...ignoring..." exit_event = m5.simulate() exit_cause = exit_event.getCause() code = exit_event.getCode() if exit_cause == "simpoint starting point found": m5.checkpoint(joinpath(cptdir, "cpt.simpoint_%02d_inst_%d_weight_%f_interval_%d_warmup_%d" % (index, starting_inst_count, weight, interval_length, actual_warmup_length))) print "Checkpoint #%d written. start inst:%d weight:%f" % \ (num_checkpoints, starting_inst_count, weight) num_checkpoints += 1 last_chkpnt_inst_count = starting_inst_count else: break index += 1 print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_cause) print "%d checkpoints taken" % num_checkpoints sys.exit(code)
def dump(): '''Dump all statistics data to the registered outputs''' curTick = m5.curTick() global lastDump assert lastDump <= curTick if lastDump == curTick: return lastDump = curTick internal.stats.processDumpQueue() prepare() for output in outputList: if output.valid(): output.begin() for stat in stats_list: output.visit(stat) output.end() for listener in dumpListeners: listener()
def __init__(self, eventq, period): super(ProgressEvent, self).__init__() self.period = int(period) self.eventq = eventq self.eventq.schedule(self, m5.curTick() + self.period)
tmp_cpu_list = [] for old_cpu, new_cpu in switch_cpu_list: tmp_cpu_list.append((new_cpu, old_cpu)) switch_cpu_list = tmp_cpu_list m5.stats.reset() exit_event = m5.simulate() exit_cause = exit_event.getCause() if switch_cpu_list[0][0].type == 'DerivO3CPU': m5.stats.dump() elif options.simpoint_mode == "checkpoint_gen": exit_event = m5.simulate() exit_cause = exit_event.getCause() checkpoint_points = simple_end_points[:] checkpoint_points.reverse() while exit_cause == "simpoint starting point found": point_inst = checkpoint_points.pop() m5.checkpoint(os.path.join(options.checkpoint_dir, "simpoint.ckpt.inst.%d" % point_inst)) if not checkpoint_points: exit_cause = "final simpoint checkpoint created" break; exit_event = m5.simulate() exit_cause = exit_event.getCause() print "Exiting @ tick %i because %s" % (m5.curTick(), exit_cause)
import m5 from m5.objects import * root = Root(full_system=False) root.hello = HelloObject(time_to_wait='2us', number_of_fires=10) root.hello.goodbye_object = GoodbyeObject(buffer_size='100B') m5.instantiate() print("begin") exit_event = m5.simulate() print('exit @ tick {} because {}'.format(m5.curTick(), exit_event.getCause()))
def run(options, root, testsys, cpu_class): if options.maxtick: maxtick = options.maxtick elif options.maxtime: simtime = m5.ticks.seconds(simtime) print "simulating for: ", simtime maxtick = simtime else: maxtick = m5.MaxTick if options.checkpoint_dir: cptdir = options.checkpoint_dir elif m5.options.outdir: cptdir = m5.options.outdir else: cptdir = getcwd() if options.fast_forward and options.checkpoint_restore != None: fatal("Can't specify both --fast-forward and --checkpoint-restore") if options.standard_switch and not options.caches: fatal("Must specify --caches when using --standard-switch") np = options.num_cpus max_checkpoints = options.max_checkpoints new = None if options.prog_interval: for i in xrange(np): testsys.cpu[i].progress_interval = options.prog_interval if options.maxinsts: for i in xrange(np): testsys.cpu[i].max_insts_any_thread = options.maxinsts if cpu_class: new = [cpu_class(defer_registration=True, cpu_id=(np + i)) for i in xrange(np)] for i in xrange(np): if options.fast_forward: testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) new[i].system = testsys if not buildEnv["FULL_SYSTEM"]: new[i].workload = testsys.cpu[i].workload new[i].clock = testsys.cpu[0].clock # simulation period if options.maxinsts: new[i].max_insts_any_thread = options.maxinsts testsys.new = new switch_cpu_list = [(testsys.cpu[i], new[i]) for i in xrange(np)] if options.standard_switch: if not options.caches: # O3 CPU must have a cache to work. print "O3 CPU must be used with caches" sys.exit(1) new = [TimingSimpleCPU(defer_registration=True, cpu_id=(np + i)) for i in xrange(np)] new_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2 * np + i)) for i in xrange(np)] for i in xrange(np): new[i].system = testsys new_1[i].system = testsys if not buildEnv["FULL_SYSTEM"]: new[i].workload = testsys.cpu[i].workload new_1[i].workload = testsys.cpu[i].workload new[i].clock = testsys.cpu[0].clock new_1[i].clock = testsys.cpu[0].clock # if restoring, make atomic cpu simulate only a few instructions if options.checkpoint_restore != None: testsys.cpu[i].max_insts_any_thread = 1 # Fast forward to specified location if we are not restoring elif options.fast_forward: testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) # Fast forward to a simpoint (warning: time consuming) elif options.simpoint: if testsys.cpu[i].workload[0].simpoint == 0: fatal("simpoint not found") testsys.cpu[i].max_insts_any_thread = testsys.cpu[i].workload[0].simpoint # No distance specified, just switch else: testsys.cpu[i].max_insts_any_thread = 1 # warmup period if options.warmup_insts: new[i].max_insts_any_thread = options.warmup_insts # simulation period if options.maxinsts: new_1[i].max_insts_any_thread = options.maxinsts testsys.new = new testsys.new_1 = new_1 switch_cpu_list = [(testsys.cpu[i], new[i]) for i in xrange(np)] switch_cpu_list1 = [(new[i], new_1[i]) for i in xrange(np)] # set the checkpoint in the cpu before m5.instantiate is called if options.take_checkpoints != None and (options.simpoint or options.at_instruction): offset = int(options.take_checkpoints) # Set an instruction break point if options.simpoint: for i in xrange(np): if testsys.cpu[i].workload[0].simpoint == 0: fatal("no simpoint for testsys.cpu[%d].workload[0]", i) checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset testsys.cpu[i].max_insts_any_thread = checkpoint_inst # used for output below options.take_checkpoints = checkpoint_inst else: options.take_checkpoints = offset # Set all test cpus with the right number of instructions # for the upcoming simulation for i in xrange(np): testsys.cpu[i].max_insts_any_thread = offset checkpoint_dir = None if options.checkpoint_restore != None: from os.path import isdir, exists from os import listdir import re if not isdir(cptdir): fatal("checkpoint dir %s does not exist!", cptdir) if options.at_instruction or options.simpoint: inst = options.checkpoint_restore if options.simpoint: # assume workload 0 has the simpoint if testsys.cpu[0].workload[0].simpoint == 0: fatal("Unable to find simpoint") inst += int(testsys.cpu[0].workload[0].simpoint) checkpoint_dir = joinpath(cptdir, "cpt.%s.%s" % (options.bench, inst)) if not exists(checkpoint_dir): fatal("Unable to find checkpoint directory %s", checkpoint_dir) else: dirs = listdir(cptdir) expr = re.compile("cpt\.([0-9]*)") cpts = [] for dir in dirs: match = expr.match(dir) if match: cpts.append(match.group(1)) cpts.sort(lambda a, b: cmp(long(a), long(b))) cpt_num = options.checkpoint_restore if cpt_num > len(cpts): fatal("Checkpoint %d not found", cpt_num) ## Adjust max tick based on our starting tick maxtick = maxtick - int(cpts[cpt_num - 1]) checkpoint_dir = joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]) m5.instantiate(checkpoint_dir) if options.standard_switch or cpu_class: if options.standard_switch: print "Switch at instruction count:%s" % str(testsys.cpu[0].max_insts_any_thread) exit_event = m5.simulate() elif cpu_class and options.fast_forward: print "Switch at instruction count:%s" % str(testsys.cpu[0].max_insts_any_thread) exit_event = m5.simulate() else: print "Switch at curTick count:%s" % str(10000) exit_event = m5.simulate(10000) print "Switched CPUS @ tick %s" % (m5.curTick()) # when you change to Timing (or Atomic), you halt the system # given as argument. When you are finished with the system # changes (including switchCpus), you must resume the system # manually. You DON'T need to resume after just switching # CPUs if you haven't changed anything on the system level. m5.changeToTiming(testsys) m5.switchCpus(switch_cpu_list) m5.resume(testsys) if options.standard_switch: print "Switch at instruction count:%d" % (testsys.new[0].max_insts_any_thread) # warmup instruction count may have already been set if options.warmup_insts: exit_event = m5.simulate() else: exit_event = m5.simulate(options.warmup) print "Switching CPUS @ tick %s" % (m5.curTick()) print "Simulation ends instruction count:%d" % (testsys.new_1[0].max_insts_any_thread) m5.drain(testsys) m5.switchCpus(switch_cpu_list1) m5.resume(testsys) num_checkpoints = 0 exit_cause = "" # If we're taking and restoring checkpoints, use checkpoint_dir # option only for finding the checkpoints to restore from. This # lets us test checkpointing by restoring from one set of # checkpoints, generating a second set, and then comparing them. if options.take_checkpoints and options.checkpoint_restore: if m5.options.outdir: cptdir = m5.options.outdir else: cptdir = getcwd() # Checkpoints being taken via the command line at <when> and at # subsequent periods of <period>. Checkpoint instructions # received from the benchmark running are ignored and skipped in # favor of command line checkpoint instructions. if options.take_checkpoints != None: if options.at_instruction or options.simpoint: checkpoint_inst = int(options.take_checkpoints) # maintain correct offset if we restored from some instruction if options.checkpoint_restore != None: checkpoint_inst += options.checkpoint_restore print "Creating checkpoint at inst:%d" % (checkpoint_inst) exit_event = m5.simulate() print "exit cause = %s" % (exit_event.getCause()) # skip checkpoint instructions should they exist while exit_event.getCause() == "checkpoint": exit_event = m5.simulate() if exit_event.getCause() == "a thread reached the max instruction count": m5.checkpoint(joinpath(cptdir, "cpt.%s.%d" % (options.bench, checkpoint_inst))) print "Checkpoint written." num_checkpoints += 1 if exit_event.getCause() == "user interrupt received": exit_cause = exit_event.getCause() else: when, period = options.take_checkpoints.split(",", 1) when = int(when) period = int(period) exit_event = m5.simulate(when) while exit_event.getCause() == "checkpoint": exit_event = m5.simulate(when - m5.curTick()) if exit_event.getCause() == "simulate() limit reached": m5.checkpoint(joinpath(cptdir, "cpt.%d")) num_checkpoints += 1 sim_ticks = when exit_cause = "maximum %d checkpoints dropped" % max_checkpoints while num_checkpoints < max_checkpoints and exit_event.getCause() == "simulate() limit reached": if (sim_ticks + period) > maxtick: exit_event = m5.simulate(maxtick - sim_ticks) exit_cause = exit_event.getCause() break else: exit_event = m5.simulate(period) sim_ticks += period while exit_event.getCause() == "checkpoint": exit_event = m5.simulate(sim_ticks - m5.curTick()) if exit_event.getCause() == "simulate() limit reached": m5.checkpoint(joinpath(cptdir, "cpt.%d")) num_checkpoints += 1 if exit_event.getCause() != "simulate() limit reached": exit_cause = exit_event.getCause() else: # no checkpoints being taken via this script if options.fast_forward: m5.stats.reset() print "**** REAL SIMULATION ****" exit_event = m5.simulate(maxtick) while exit_event.getCause() == "checkpoint": m5.checkpoint(joinpath(cptdir, "cpt.%d")) num_checkpoints += 1 if num_checkpoints == max_checkpoints: exit_cause = "maximum %d checkpoints dropped" % max_checkpoints break exit_event = m5.simulate(maxtick - m5.curTick()) exit_cause = exit_event.getCause() if exit_cause == "": exit_cause = exit_event.getCause() print "Exiting @ tick %i because %s" % (m5.curTick(), exit_cause) if options.checkpoint_at_end: m5.checkpoint(joinpath(cptdir, "cpt.%d"))
def main(): parser = argparse.ArgumentParser( description="Generic ARM big.LITTLE configuration") parser.add_argument("--restore-from", type=str, default=None, help="Restore from checkpoint") parser.add_argument("--dtb", type=str, default=default_dtb, help="DTB file to load") parser.add_argument("--kernel", type=str, default=default_kernel, help="Linux kernel") parser.add_argument("--disk", action="append", type=str, default=[], help="Disks to instantiate") parser.add_argument("--bootscript", type=str, default=default_rcs, help="Linux bootscript") parser.add_argument("--atomic", action="store_true", default=False, help="Use atomic CPUs") parser.add_argument("--kernel-init", type=str, default="/sbin/init", help="Override init") parser.add_argument("--big-cpus", type=int, default=1, help="Number of big CPUs to instantiate") parser.add_argument("--little-cpus", type=int, default=1, help="Number of little CPUs to instantiate") parser.add_argument("--caches", action="store_true", default=False, help="Instantiate caches") parser.add_argument("--last-cache-level", type=int, default=2, help="Last level of caches (e.g. 3 for L3)") parser.add_argument("--big-cpu-clock", type=str, default="2GHz", help="Big CPU clock frequency") parser.add_argument("--little-cpu-clock", type=str, default="1GHz", help="Little CPU clock frequency") m5.ticks.fixGlobalFrequency() options = parser.parse_args() if options.atomic: cpu_config = { 'cpu' : AtomicSimpleCPU } big_cpu_config, little_cpu_config = cpu_config, cpu_config else: big_cpu_config = { 'cpu' : CpuConfig.get("arm_detailed"), 'l1i' : devices.L1I, 'l1d' : devices.L1D, 'wcache' : devices.WalkCache, 'l2' : devices.L2 } little_cpu_config = { 'cpu' : MinorCPU, 'l1i' : devices.L1I, 'l1d' : devices.L1D, 'wcache' : devices.WalkCache, 'l2' : devices.L2 } big_cpu_class = big_cpu_config['cpu'] little_cpu_class = little_cpu_config['cpu'] kernel_cmd = [ "earlyprintk=pl011,0x1c090000", "console=ttyAMA0", "lpj=19988480", "norandmaps", "loglevel=8", "mem=%s" % default_mem_size, "root=/dev/vda1", "rw", "init=%s" % options.kernel_init, "vmalloc=768MB", ] root = Root(full_system=True) assert big_cpu_class.memory_mode() == little_cpu_class.memory_mode() disks = default_disk if len(options.disk) == 0 else options.disk system = createSystem(options.kernel, big_cpu_class.memory_mode(), options.bootscript, disks=disks) root.system = system system.boot_osflags = " ".join(kernel_cmd) # big cluster if options.big_cpus > 0: system.bigCluster = CpuCluster() system.bigCluster.addCPUs(big_cpu_config, options.big_cpus, options.big_cpu_clock) # LITTLE cluster if options.little_cpus > 0: system.littleCluster = CpuCluster() system.littleCluster.addCPUs(little_cpu_config, options.little_cpus, options.little_cpu_clock) # add caches if options.caches: cluster_mem_bus = addCaches(system, options.last_cache_level) else: if big_cpu_class.require_caches(): m5.util.panic("CPU model %s requires caches" % str(big_cpu_class)) if little_cpu_class.require_caches(): m5.util.panic("CPU model %s requires caches" % str(little_cpu_class)) cluster_mem_bus = system.membus # connect each cluster to the memory hierarchy for cluster in system._clusters: cluster.connectMemSide(cluster_mem_bus) # Linux device tree system.dtb_filename = SysPaths.binary(options.dtb) # Get and load from the chkpt or simpoint checkpoint if options.restore_from is not None: m5.instantiate(options.restore_from) else: m5.instantiate() # start simulation (and drop checkpoints when requested) while True: event = m5.simulate() exit_msg = event.getCause() if exit_msg == "checkpoint": print "Dropping checkpoint at tick %d" % m5.curTick() cpt_dir = os.path.join(m5.options.outdir, "cpt.%d" % m5.curTick()) m5.checkpoint(os.path.join(cpt_dir)) print "Checkpoint done." else: print exit_msg, " @ ", m5.curTick() break sys.exit(event.getCode())
def run(options, root, testsys, cpu_class): if options.maxtick: maxtick = options.maxtick elif options.maxtime: simtime = m5.ticks.seconds(simtime) print "simulating for: ", simtime maxtick = simtime else: maxtick = m5.MaxTick if options.checkpoint_dir: cptdir = options.checkpoint_dir elif m5.options.outdir: cptdir = m5.options.outdir else: cptdir = getcwd() if options.fast_forward and options.checkpoint_restore != None: fatal("Can't specify both --fast-forward and --checkpoint-restore") if options.standard_switch and not options.caches: fatal("Must specify --caches when using --standard-switch") if options.standard_switch and options.repeat_switch: fatal("Can't specify both --standard-switch and --repeat-switch") if options.repeat_switch and options.take_checkpoints: fatal("Can't specify both --repeat-switch and --take-checkpoints") np = options.num_cpus switch_cpus = None if options.prog_interval: for i in xrange(np): testsys.cpu[i].progress_interval = options.prog_interval if options.maxinsts: for i in xrange(np): testsys.cpu[i].max_insts_any_thread = options.maxinsts if cpu_class: switch_cpus = [cpu_class(switched_out=True, cpu_id=(i)) for i in xrange(np)] for i in xrange(np): if options.fast_forward: testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) switch_cpus[i].system = testsys switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus[i].clock = testsys.cpu[i].clock # simulation period if options.maxinsts: switch_cpus[i].max_insts_any_thread = options.maxinsts # Add checker cpu if selected if options.checker: switch_cpus[i].addCheckerCpu() testsys.switch_cpus = switch_cpus switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] if options.repeat_switch: switch_class = getCPUClass(options.cpu_type)[0] if switch_class.require_caches() and \ not options.caches: print "%s: Must be used with caches" % str(switch_class) sys.exit(1) if not switch_class.support_take_over(): print "%s: CPU switching not supported" % str(switch_class) sys.exit(1) repeat_switch_cpus = [switch_class(switched_out=True, \ cpu_id=(i)) for i in xrange(np)] for i in xrange(np): repeat_switch_cpus[i].system = testsys repeat_switch_cpus[i].workload = testsys.cpu[i].workload repeat_switch_cpus[i].clock = testsys.cpu[i].clock if options.maxinsts: repeat_switch_cpus[i].max_insts_any_thread = options.maxinsts if options.checker: repeat_switch_cpus[i].addCheckerCpu() testsys.repeat_switch_cpus = repeat_switch_cpus if cpu_class: repeat_switch_cpu_list = [(switch_cpus[i], repeat_switch_cpus[i]) for i in xrange(np)] else: repeat_switch_cpu_list = [(testsys.cpu[i], repeat_switch_cpus[i]) for i in xrange(np)] if options.standard_switch: switch_cpus = [TimingSimpleCPU(switched_out=True, cpu_id=(i)) for i in xrange(np)] switch_cpus_1 = [DerivO3CPU(switched_out=True, cpu_id=(i)) for i in xrange(np)] for i in xrange(np): switch_cpus[i].system = testsys switch_cpus_1[i].system = testsys switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus_1[i].workload = testsys.cpu[i].workload switch_cpus[i].clock = testsys.cpu[i].clock switch_cpus_1[i].clock = testsys.cpu[i].clock # if restoring, make atomic cpu simulate only a few instructions if options.checkpoint_restore != None: testsys.cpu[i].max_insts_any_thread = 1 # Fast forward to specified location if we are not restoring elif options.fast_forward: testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) # Fast forward to a simpoint (warning: time consuming) elif options.simpoint: if testsys.cpu[i].workload[0].simpoint == 0: fatal('simpoint not found') testsys.cpu[i].max_insts_any_thread = \ testsys.cpu[i].workload[0].simpoint # No distance specified, just switch else: testsys.cpu[i].max_insts_any_thread = 1 # warmup period if options.warmup_insts: switch_cpus[i].max_insts_any_thread = options.warmup_insts # simulation period if options.maxinsts: switch_cpus_1[i].max_insts_any_thread = options.maxinsts # attach the checker cpu if selected if options.checker: switch_cpus[i].addCheckerCpu() switch_cpus_1[i].addCheckerCpu() testsys.switch_cpus = switch_cpus testsys.switch_cpus_1 = switch_cpus_1 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] # set the checkpoint in the cpu before m5.instantiate is called if options.take_checkpoints != None and \ (options.simpoint or options.at_instruction): offset = int(options.take_checkpoints) # Set an instruction break point if options.simpoint: for i in xrange(np): if testsys.cpu[i].workload[0].simpoint == 0: fatal('no simpoint for testsys.cpu[%d].workload[0]', i) checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset testsys.cpu[i].max_insts_any_thread = checkpoint_inst # used for output below options.take_checkpoints = checkpoint_inst else: options.take_checkpoints = offset # Set all test cpus with the right number of instructions # for the upcoming simulation for i in xrange(np): testsys.cpu[i].max_insts_any_thread = offset checkpoint_dir = None if options.checkpoint_restore != None: maxtick, checkpoint_dir = findCptDir(options, maxtick, cptdir, testsys) m5.instantiate(checkpoint_dir) if options.standard_switch or cpu_class: if options.standard_switch: print "Switch at instruction count:%s" % \ str(testsys.cpu[0].max_insts_any_thread) exit_event = m5.simulate() elif cpu_class and options.fast_forward: print "Switch at instruction count:%s" % \ str(testsys.cpu[0].max_insts_any_thread) exit_event = m5.simulate() else: print "Switch at curTick count:%s" % str(10000) exit_event = m5.simulate(10000) print "Switched CPUS @ tick %s" % (m5.curTick()) m5.switchCpus(testsys, switch_cpu_list) if options.standard_switch: print "Switch at instruction count:%d" % \ (testsys.switch_cpus[0].max_insts_any_thread) #warmup instruction count may have already been set if options.warmup_insts: exit_event = m5.simulate() else: exit_event = m5.simulate(options.standard_switch) print "Switching CPUS @ tick %s" % (m5.curTick()) print "Simulation ends instruction count:%d" % \ (testsys.switch_cpus_1[0].max_insts_any_thread) m5.switchCpus(testsys, switch_cpu_list1) # If we're taking and restoring checkpoints, use checkpoint_dir # option only for finding the checkpoints to restore from. This # lets us test checkpointing by restoring from one set of # checkpoints, generating a second set, and then comparing them. if options.take_checkpoints and options.checkpoint_restore: if m5.options.outdir: cptdir = m5.options.outdir else: cptdir = getcwd() if options.take_checkpoints != None : # Checkpoints being taken via the command line at <when> and at # subsequent periods of <period>. Checkpoint instructions # received from the benchmark running are ignored and skipped in # favor of command line checkpoint instructions. exit_event = scriptCheckpoints(options, maxtick, cptdir) else: if options.fast_forward: m5.stats.reset() print "**** REAL SIMULATION ****" # If checkpoints are being taken, then the checkpoint instruction # will occur in the benchmark code it self. if options.repeat_switch and maxtick > options.repeat_switch: exit_event = repeatSwitch(testsys, repeat_switch_cpu_list, maxtick, options.repeat_switch) else: exit_event = benchCheckpoints(options, maxtick, cptdir) print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()) if options.checkpoint_at_end: m5.checkpoint(joinpath(cptdir, "cpt.%d")) if not m5.options.interactive: sys.exit(exit_event.getCode())
def run(options, root, testsys, cpu_class): if options.checkpoint_dir: cptdir = options.checkpoint_dir elif m5.options.outdir: cptdir = m5.options.outdir else: cptdir = getcwd() if options.fast_forward and options.checkpoint_restore != None: fatal("Can't specify both --fast-forward and --checkpoint-restore") if options.standard_switch and not options.caches: fatal("Must specify --caches when using --standard-switch") if options.standard_switch and options.repeat_switch: fatal("Can't specify both --standard-switch and --repeat-switch") if options.repeat_switch and options.take_checkpoints: fatal("Can't specify both --repeat-switch and --take-checkpoints") np = options.num_cpus switch_cpus = None if options.prog_interval: for i in range(np): testsys.cpu[i].progress_interval = options.prog_interval if options.maxinsts: for i in range(np): testsys.cpu[i].max_insts_any_thread = options.maxinsts if cpu_class: switch_cpus = [ cpu_class(switched_out=True, cpu_id=(i)) for i in range(np) ] for i in range(np): if options.fast_forward: testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) switch_cpus[i].system = testsys switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain switch_cpus[i].progress_interval = \ testsys.cpu[i].progress_interval switch_cpus[i].isa = testsys.cpu[i].isa # simulation period if options.maxinsts: switch_cpus[i].max_insts_any_thread = options.maxinsts # Add checker cpu if selected if options.checker: switch_cpus[i].addCheckerCpu() if options.bp_type: bpClass = ObjectList.bp_list.get(options.bp_type) switch_cpus[i].branchPred = bpClass() if options.indirect_bp_type: IndirectBPClass = ObjectList.indirect_bp_list.get( options.indirect_bp_type) switch_cpus[i].branchPred.indirectBranchPred = \ IndirectBPClass() # If elastic tracing is enabled attach the elastic trace probe # to the switch CPUs if options.elastic_trace_en: CpuConfig.config_etrace(cpu_class, switch_cpus, options) testsys.switch_cpus = switch_cpus switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in range(np)] if options.repeat_switch: switch_class = getCPUClass(options.cpu_type)[0] if switch_class.require_caches() and \ not options.caches: print("%s: Must be used with caches" % str(switch_class)) sys.exit(1) if not switch_class.support_take_over(): print("%s: CPU switching not supported" % str(switch_class)) sys.exit(1) repeat_switch_cpus = [switch_class(switched_out=True, \ cpu_id=(i)) for i in range(np)] for i in range(np): repeat_switch_cpus[i].system = testsys repeat_switch_cpus[i].workload = testsys.cpu[i].workload repeat_switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain repeat_switch_cpus[i].isa = testsys.cpu[i].isa if options.maxinsts: repeat_switch_cpus[i].max_insts_any_thread = options.maxinsts if options.checker: repeat_switch_cpus[i].addCheckerCpu() testsys.repeat_switch_cpus = repeat_switch_cpus if cpu_class: repeat_switch_cpu_list = [(switch_cpus[i], repeat_switch_cpus[i]) for i in range(np)] else: repeat_switch_cpu_list = [(testsys.cpu[i], repeat_switch_cpus[i]) for i in range(np)] if options.standard_switch: switch_cpus = [ TimingSimpleCPU(switched_out=True, cpu_id=(i)) for i in range(np) ] switch_cpus_1 = [ DerivO3CPU(switched_out=True, cpu_id=(i)) for i in range(np) ] for i in range(np): switch_cpus[i].system = testsys switch_cpus_1[i].system = testsys switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus_1[i].workload = testsys.cpu[i].workload switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain switch_cpus_1[i].clk_domain = testsys.cpu[i].clk_domain switch_cpus[i].isa = testsys.cpu[i].isa switch_cpus_1[i].isa = testsys.cpu[i].isa # if restoring, make atomic cpu simulate only a few instructions if options.checkpoint_restore != None: testsys.cpu[i].max_insts_any_thread = 1 # Fast forward to specified location if we are not restoring elif options.fast_forward: testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) # Fast forward to a simpoint (warning: time consuming) elif options.simpoint: if testsys.cpu[i].workload[0].simpoint == 0: fatal('simpoint not found') testsys.cpu[i].max_insts_any_thread = \ testsys.cpu[i].workload[0].simpoint # No distance specified, just switch else: testsys.cpu[i].max_insts_any_thread = 1 # warmup period if options.warmup_insts: switch_cpus[i].max_insts_any_thread = options.warmup_insts # simulation period if options.maxinsts: switch_cpus_1[i].max_insts_any_thread = options.maxinsts # attach the checker cpu if selected if options.checker: switch_cpus[i].addCheckerCpu() switch_cpus_1[i].addCheckerCpu() testsys.switch_cpus = switch_cpus testsys.switch_cpus_1 = switch_cpus_1 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in range(np)] switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in range(np)] # set the checkpoint in the cpu before m5.instantiate is called if options.take_checkpoints != None and \ (options.simpoint or options.at_instruction): offset = int(options.take_checkpoints) # Set an instruction break point if options.simpoint: for i in range(np): if testsys.cpu[i].workload[0].simpoint == 0: fatal('no simpoint for testsys.cpu[%d].workload[0]', i) checkpoint_inst = int( testsys.cpu[i].workload[0].simpoint) + offset testsys.cpu[i].max_insts_any_thread = checkpoint_inst # used for output below options.take_checkpoints = checkpoint_inst else: options.take_checkpoints = offset # Set all test cpus with the right number of instructions # for the upcoming simulation for i in range(np): testsys.cpu[i].max_insts_any_thread = offset if options.take_simpoint_checkpoints != None: simpoints, interval_length = parseSimpointAnalysisFile( options, testsys) checkpoint_dir = None if options.checkpoint_restore: cpt_starttick, checkpoint_dir = findCptDir(options, cptdir, testsys) root.apply_config(options.param) m5.instantiate(checkpoint_dir) # Initialization is complete. If we're not in control of simulation # (that is, if we're a slave simulator acting as a component in another # 'master' simulator) then we're done here. The other simulator will # call simulate() directly. --initialize-only is used to indicate this. if options.initialize_only: return # Handle the max tick settings now that tick frequency was resolved # during system instantiation # NOTE: the maxtick variable here is in absolute ticks, so it must # include any simulated ticks before a checkpoint explicit_maxticks = 0 maxtick_from_abs = m5.MaxTick maxtick_from_rel = m5.MaxTick maxtick_from_maxtime = m5.MaxTick if options.abs_max_tick: maxtick_from_abs = options.abs_max_tick explicit_maxticks += 1 if options.rel_max_tick: maxtick_from_rel = options.rel_max_tick if options.checkpoint_restore: # NOTE: this may need to be updated if checkpoints ever store # the ticks per simulated second maxtick_from_rel += cpt_starttick if options.at_instruction or options.simpoint: warn("Relative max tick specified with --at-instruction or" \ " --simpoint\n These options don't specify the " \ "checkpoint start tick, so assuming\n you mean " \ "absolute max tick") explicit_maxticks += 1 if options.maxtime: maxtick_from_maxtime = m5.ticks.fromSeconds(options.maxtime) explicit_maxticks += 1 if explicit_maxticks > 1: warn("Specified multiple of --abs-max-tick, --rel-max-tick, --maxtime."\ " Using least") maxtick = min([maxtick_from_abs, maxtick_from_rel, maxtick_from_maxtime]) if options.checkpoint_restore != None and maxtick < cpt_starttick: fatal("Bad maxtick (%d) specified: " \ "Checkpoint starts starts from tick: %d", maxtick, cpt_starttick) if options.standard_switch or cpu_class: if options.standard_switch: print("Switch at instruction count:%s" % str(testsys.cpu[0].max_insts_any_thread)) exit_event = m5.simulate() elif cpu_class and options.fast_forward: print("Switch at instruction count:%s" % str(testsys.cpu[0].max_insts_any_thread)) exit_event = m5.simulate() else: print("Switch at curTick count:%s" % str(10000)) exit_event = m5.simulate(10000) print("Switched CPUS @ tick %s" % (m5.curTick())) m5.switchCpus(testsys, switch_cpu_list) if options.standard_switch: print("Switch at instruction count:%d" % (testsys.switch_cpus[0].max_insts_any_thread)) #warmup instruction count may have already been set if options.warmup_insts: exit_event = m5.simulate() else: exit_event = m5.simulate(options.standard_switch) print("Switching CPUS @ tick %s" % (m5.curTick())) print("Simulation ends instruction count:%d" % (testsys.switch_cpus_1[0].max_insts_any_thread)) m5.switchCpus(testsys, switch_cpu_list1) # If we're taking and restoring checkpoints, use checkpoint_dir # option only for finding the checkpoints to restore from. This # lets us test checkpointing by restoring from one set of # checkpoints, generating a second set, and then comparing them. if (options.take_checkpoints or options.take_simpoint_checkpoints) \ and options.checkpoint_restore: if m5.options.outdir: cptdir = m5.options.outdir else: cptdir = getcwd() if options.take_checkpoints != None: # Checkpoints being taken via the command line at <when> and at # subsequent periods of <period>. Checkpoint instructions # received from the benchmark running are ignored and skipped in # favor of command line checkpoint instructions. exit_event = scriptCheckpoints(options, maxtick, cptdir) # Take SimPoint checkpoints elif options.take_simpoint_checkpoints != None: takeSimpointCheckpoints(simpoints, interval_length, cptdir) # Restore from SimPoint checkpoints elif options.restore_simpoint_checkpoint != None: restoreSimpointCheckpoint() else: if options.fast_forward: m5.stats.reset() print("**** REAL SIMULATION ****") # If checkpoints are being taken, then the checkpoint instruction # will occur in the benchmark code it self. if options.repeat_switch and maxtick > options.repeat_switch: exit_event = repeatSwitch(testsys, repeat_switch_cpu_list, maxtick, options.repeat_switch) elif options.advancedstats: while 1: exit_event = m5.simulate( options.dumpinterval ) # The time scale is nano second (one tick) m5.stats.dump() # m5.stats.reset() # print('MESSAGE', exit_event.getCause()) if (exit_event.getCause() == 'exiting with last active thread context'): break print("all sample completed") else: exit_event = benchCheckpoints(options, maxtick, cptdir) print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()))
system.cpu.createInterruptController() if isa == 'x86': system.cpu.interrupts[0].pio = system.membus.master system.cpu.interrupts[0].int_master = system.membus.slave system.cpu.interrupts[0].int_slave = system.membus.master system.system_port = system.membus.slave system.mem_ctrl = DDR3_1600_8x8() system.mem_ctrl.range = system.mem_ranges[0] system.mem_ctrl.port = system.membus.master process = Process() apps_path = "/project/linuxlab/gem5/test_progs/" if program == "daxpy" and isa == "x86": process.cmd = [apps_path + '/daxpy/daxpy_x86'] elif program == "daxpy" and isa == "arm": process.cmd = [apps_path + '/daxpy/daxpy_arm'] elif program == "queens" and isa == "x86": process.cmd = [apps_path + '/queens/queens_x86'] process.cmd += ["10 -c"] elif program == "queens" and isa == "arm": process.cmd = [apps_path + 'queens/queens_arm'] process.cmd += ["10 -c"] system.cpu.workload = process system.cpu.createThreads() root = Root(full_system=False, system=system) m5.instantiate() print("Beginning simulation!") exit_event = m5.simulate() print('Exiting @ tick because '.format(m5.curTick(), exit_event.getCause()))
# int controllers system.cpu.createInterruptController() system.cpu.interrupts[0].pio = system.membus.master system.cpu.interrupts[0].int_master = system.membus.slave system.cpu.interrupts[0].int_slave = system.membus.master system.system_port = system.membus.slave system.mem_ctrl = DDR3_1600_8x8() system.mem_ctrl.range = system.mem_ranges[0] system.mem_ctrl.port = system.membus.master process = Process() process.cmd = ['tests/test-progs/hello/bin/x86/linux/hello'] system.cpu.workload = process system.cpu.createThreads() # all the simulations have to have a root object, absolutely required, # all others are optionsl root = Root(full_system=False, system=system) # walk through all the above python objects and create all C++ objects m5.instantiate() print "beginning simulation" exit_event = m5.simulate() print "done simulating at tick %d because %s!!" % (m5.curTick(), exit_event.getCause())
checkpoint_dir = None m5.instantiate(checkpoint_dir) # Map workload to this address space host_cpu.workload[0].map(0x10000000, 0x200000000, 4096) if options.fast_forward: print("Switch at instruction count: %d" % cpu_list[0].max_insts_any_thread) exit_event = m5.simulate(maxtick) if options.fast_forward: if exit_event.getCause() == "a thread reached the max instruction count": m5.switchCpus(system, switch_cpu_list) print("Switched CPUS @ tick %s" % (m5.curTick())) m5.stats.reset() exit_event = m5.simulate(maxtick - m5.curTick()) elif options.fast_forward_pseudo_op: while exit_event.getCause() == "switchcpu": # If we are switching *to* kvm, then the current stats are meaningful # Note that we don't do any warmup by default if type(switch_cpu_list[0][0]) == FutureCpuClass: print("Dumping stats...") m5.stats.dump() m5.switchCpus(system, switch_cpu_list) print("Switched CPUS @ tick %s" % (m5.curTick())) m5.stats.reset() # This lets us switch back and forth without keeping a counter switch_cpu_list = [(x[1], x[0]) for x in switch_cpu_list] exit_event = m5.simulate(maxtick - m5.curTick())
def main(): parser = argparse.ArgumentParser(epilog=__doc__) parser.add_argument("commands_to_run", metavar="command(s)", nargs='*', help="Command(s) to run") parser.add_argument("--cpu", type=str, choices=cpu_types.keys(), default="atomic", help="CPU model to use") parser.add_argument("--cpu-freq", type=str, default="4GHz") parser.add_argument("--num-cores", type=int, default=1, help="Number of CPU cores") parser.add_argument("--mem-type", default="DDR3_1600_8x8", choices=ObjectList.mem_list.get_names(), help="type of memory to use") parser.add_argument("--mem-channels", type=int, default=2, help="number of memory channels") parser.add_argument("--mem-ranks", type=int, default=None, help="number of memory ranks per channel") parser.add_argument("--mem-size", action="store", type=str, default="2GB", help="Specify the physical memory size") args = parser.parse_args() # Create a single root node for gem5's object hierarchy. There can # only exist one root node in the simulator at any given # time. Tell gem5 that we want to use syscall emulation mode # instead of full system mode. root = Root(full_system=False) # Populate the root node with a system. A system corresponds to a # single node with shared memory. root.system = create(args) # Instantiate the C++ object hierarchy. After this point, # SimObjects can't be instantiated anymore. m5.instantiate() # Start the simulator. This gives control to the C++ world and # starts the simulator. The returned event tells the simulation # script why the simulator exited. event = m5.simulate() # Print the reason for the simulation exit. Some exit codes are # requests for service (e.g., checkpoints) from the simulation # script. We'll just ignore them here and exit. print(event.getCause(), " @ ", m5.curTick()) sys.exit(event.getCode())
def __call__(self): print "Progress! Time now %fs" % (m5.curTick() / 1e12) self.eventq.schedule(self, m5.curTick() + self.period)
def get_current_tick(self) -> int: """ Returns the current tick. """ return m5.curTick()
def scriptCheckpoints(options, maxtick, cptdir): if options.at_instruction or options.simpoint: checkpoint_inst = int(options.take_checkpoints) # maintain correct offset if we restored from some instruction if options.checkpoint_restore != None: checkpoint_inst += options.checkpoint_restore print "Creating checkpoint at inst:%d" % (checkpoint_inst) exit_event = m5.simulate() exit_cause = exit_event.getCause() print "exit cause = %s" % exit_cause # skip checkpoint instructions should they exist while exit_cause == "checkpoint": exit_event = m5.simulate() exit_cause = exit_event.getCause() if exit_cause == "a thread reached the max instruction count": m5.checkpoint(joinpath(cptdir, "cpt.%s.%d" % \ (options.bench, checkpoint_inst))) print "Checkpoint written." else: when, period = options.take_checkpoints.split(",", 1) when = int(when) period = int(period) num_checkpoints = 0 exit_event = m5.simulate(when - m5.curTick()) exit_cause = exit_event.getCause() while exit_cause == "checkpoint": exit_event = m5.simulate(when - m5.curTick()) exit_cause = exit_event.getCause() if exit_cause == "simulate() limit reached": # cuiwl: dump and reset stats. print "Checkpoint %d." % (num_checkpoints) m5.checkpoint(joinpath(cptdir, "cpt.%d")) num_checkpoints += 1 sim_ticks = when max_checkpoints = options.max_checkpoints while num_checkpoints < max_checkpoints and \ exit_cause == "simulate() limit reached": if (sim_ticks + period) > maxtick: exit_event = m5.simulate(maxtick - sim_ticks) exit_cause = exit_event.getCause() break else: exit_event = m5.simulate(period) exit_cause = exit_event.getCause() sim_ticks += period while exit_event.getCause() == "checkpoint": exit_event = m5.simulate(sim_ticks - m5.curTick()) if exit_event.getCause() == "simulate() limit reached": # dump and reset stats. print "Checkpoint %d." % (num_checkpoints) m5.stats.dump() m5.stats.reset() m5.checkpoint(joinpath(cptdir, "cpt.%d")) num_checkpoints += 1 if options.stat_prefix: shutil.copyfile("/usr/local/google/home/cuiwl/gem5/m5out/stats.txt", "/usr/local/google/home/cuiwl/gem5/m5out/stats/" + options.stat_prefix + "_" + time.strftime("%Y%m%d") + "_" + time.strftime("%H:%M:%S") + ".txt") else: shutil.copyfile("/usr/local/google/home/cuiwl/gem5/m5out/stats.txt", "/usr/local/google/home/cuiwl/gem5/m5out/stats/none" + "_" + time.strftime("%Y%m%d") + "_" + time.strftime("%H:%M:%S") + ".txt") return exit_event
numa_cache_upward.append(domain.numa_cache_upward) system.mem_ranges.append(domain.mem_ranges) mem_ctrl.append(domain.mem_ctrl) membus.append(domain.membus) l2bus.append(domain.l2bus) l2cache.append(domain.l2cache) cpu += domain.cpu system.numa_cache_downward = numa_cache_downward system.numa_cache_upward = numa_cache_upward system.mem_ctrl = mem_ctrl system.membus = membus system.l2bus = l2bus system.l2cache = l2cache system.cpu = cpu system.system_port = system.systembus.slave root = Root(full_system = False, system = system) m5.instantiate() exit_event = m5.simulate() print 'Exiting @ tick ' + str(m5.curTick()) + ' because ' + exit_event.getCause()
make_level(spec[1:], prototypes[1:], cache, "cpu_side") else: # we just built the MemTest objects parent.cpu = objs for t in objs: t.test = getattr(attach_obj, attach_port) t.functional = system.funcmem.port make_level(treespec, prototypes, system.physmem, "port") # ----------------------- # run simulation # ----------------------- root = Root( system = system ) if options.atomic: root.system.mem_mode = 'atomic' else: root.system.mem_mode = 'timing' # Not much point in this being higher than the L1 latency m5.ticks.setGlobalFrequency('1ns') # instantiate configuration m5.instantiate(root) # simulate until program terminates exit_event = m5.simulate(options.maxtick) print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
system.cpu.createInterruptController() system.cpu.interrupts[0].pio = system.membus.master system.cpu.interrupts[0].int_master = system.membus.slave system.cpu.interrupts[0].int_slave = system.membus.master system.system_port = system.membus.slave system.mem_ctrl = DDR3_1600_8x8() system.mem_ctrl.range = system.mem_ranges[0] system.mem_ctrl.port = system.membus.master process = Process() process.cmd = ['tests/test-progs/hello/bin/x86/linux/hello'] system.cpu.workload = process system.cpu.createThreads() root = Root(full_system = False, system = system) m5.instantiate() print("Beginning simulation!") exit_event = m5.simulate() print('Exiting @ tick {} because {}' .format(m5.curTick(), exit_event.getCause()))
process = Process() system.cpu.process = process system.cpu.max_insts_any_thread = opts.maxinsts or default_max_insts # Set the command # cmd is a list which begins with the executable (like argv) process.cmd = binary + input_file process.output = output_file # Set the cpu to use the process as its workload and create thread contexts system.cpu.workload = process system.cpu.createThreads() # set up the root SimObject and start the simulation root = Root(full_system = False, system = system) # instantiate all of the objects we've created above m5.instantiate() # this code allows us to dump stats in intermediate states, every n instructions dump_n_instructions = 100000 i = 0 while True: i += dump_n_instructions system.cpu.scheduleInstStop(0, dump_n_instructions, 'dump statistics') event = m5.simulate() if event.getCause() == 'dump statistics': m5.stats.dump() print(str(datetime.datetime.now()), 'Instruction Count: {}, Dumping stats'.format(i)) else: print('Exiting @ tick %i because %s', m5.curTick(), event.getCause()) break
def main(): parser = argparse.ArgumentParser( description="Generic ARM big.LITTLE configuration") parser.add_argument("--restore-from", type=str, default=None, help="Restore from checkpoint") parser.add_argument("--dtb", type=str, default=default_dtb, help="DTB file to load") parser.add_argument("--kernel", type=str, default=default_kernel, help="Linux kernel") parser.add_argument("--disk", action="append", type=str, default=[], help="Disks to instantiate") parser.add_argument("--bootscript", type=str, default=default_rcs, help="Linux bootscript") parser.add_argument("--atomic", action="store_true", default=False, help="Use atomic CPUs") parser.add_argument("--kernel-init", type=str, default="/sbin/init", help="Override init") parser.add_argument("--big-cpus", type=int, default=1, help="Number of big CPUs to instantiate") parser.add_argument("--little-cpus", type=int, default=1, help="Number of little CPUs to instantiate") parser.add_argument("--caches", action="store_true", default=False, help="Instantiate caches") parser.add_argument("--last-cache-level", type=int, default=2, help="Last level of caches (e.g. 3 for L3)") parser.add_argument("--big-cpu-clock", type=str, default="2GHz", help="Big CPU clock frequency") parser.add_argument("--little-cpu-clock", type=str, default="1GHz", help="Little CPU clock frequency") m5.ticks.fixGlobalFrequency() options = parser.parse_args() kernel_cmd = [ "earlyprintk=pl011,0x1c090000", "console=ttyAMA0", "lpj=19988480", "norandmaps", "loglevel=8", "mem=%s" % default_mem_size, "root=/dev/vda1", "rw", "init=%s" % options.kernel_init, "vmalloc=768MB", ] root = Root(full_system=True) disks = default_disk if len(options.disk) == 0 else options.disk system = createSystem(options.kernel, options.bootscript, disks=disks) root.system = system system.boot_osflags = " ".join(kernel_cmd) AtomicCluster = devices.AtomicCluster if options.big_cpus + options.little_cpus == 0: m5.util.panic("Empty CPU clusters") # big cluster if options.big_cpus > 0: if options.atomic: system.bigCluster = AtomicCluster(system, options.big_cpus, options.big_cpu_clock) else: system.bigCluster = BigCluster(system, options.big_cpus, options.big_cpu_clock) mem_mode = system.bigCluster.memoryMode() # little cluster if options.little_cpus > 0: if options.atomic: system.littleCluster = AtomicCluster(system, options.little_cpus, options.little_cpu_clock) else: system.littleCluster = LittleCluster(system, options.little_cpus, options.little_cpu_clock) mem_mode = system.littleCluster.memoryMode() if options.big_cpus > 0 and options.little_cpus > 0: if system.bigCluster.memoryMode() != system.littleCluster.memoryMode(): m5.util.panic("Memory mode missmatch among CPU clusters") system.mem_mode = mem_mode # create caches system.addCaches(options.caches, options.last_cache_level) if not options.caches: if options.big_cpus > 0 and system.bigCluster.requireCaches(): m5.util.panic("Big CPU model requires caches") if options.little_cpus > 0 and system.littleCluster.requireCaches(): m5.util.panic("Little CPU model requires caches") # Linux device tree system.dtb_filename = SysPaths.binary(options.dtb) # Get and load from the chkpt or simpoint checkpoint if options.restore_from is not None: m5.instantiate(options.restore_from) else: m5.instantiate() # start simulation (and drop checkpoints when requested) while True: event = m5.simulate() exit_msg = event.getCause() if exit_msg == "checkpoint": print "Dropping checkpoint at tick %d" % m5.curTick() cpt_dir = os.path.join(m5.options.outdir, "cpt.%d" % m5.curTick()) m5.checkpoint(os.path.join(cpt_dir)) print "Checkpoint done." else: print exit_msg, " @ ", m5.curTick() break sys.exit(event.getCode())
def main(): parser = argparse.ArgumentParser( description="Generic ARM big.LITTLE configuration") parser.add_argument("--restore-from", type=str, default=None, help="Restore from checkpoint") parser.add_argument("--dtb", type=str, default=default_dtb, help="DTB file to load") parser.add_argument("--kernel", type=str, default=default_kernel, help="Linux kernel") parser.add_argument("--disk", action="append", type=str, default=[], help="Disks to instantiate") parser.add_argument("--bootscript", type=str, default=default_rcs, help="Linux bootscript") parser.add_argument("--atomic", action="store_true", default=False, help="Use atomic CPUs") parser.add_argument("--kernel-init", type=str, default="/sbin/init", help="Override init") parser.add_argument("--big-cpus", type=int, default=1, help="Number of big CPUs to instantiate") parser.add_argument("--little-cpus", type=int, default=1, help="Number of little CPUs to instantiate") parser.add_argument("--caches", action="store_true", default=False, help="Instantiate caches") parser.add_argument("--last-cache-level", type=int, default=2, help="Last level of caches (e.g. 3 for L3)") parser.add_argument("--big-cpu-clock", type=str, default="2GHz", help="Big CPU clock frequency") parser.add_argument("--little-cpu-clock", type=str, default="1GHz", help="Little CPU clock frequency") m5.ticks.fixGlobalFrequency() options = parser.parse_args() kernel_cmd = [ "earlyprintk=pl011,0x1c090000", "console=ttyAMA0", "lpj=19988480", "norandmaps", "loglevel=8", "mem=%s" % default_mem_size, "root=/dev/vda1", "rw", "init=%s" % options.kernel_init, "vmalloc=768MB", ] root = Root(full_system=True) disks = [default_disk] if len(options.disk) == 0 else options.disk system = createSystem(options.caches, options.kernel, options.bootscript, disks=disks) root.system = system system.boot_osflags = " ".join(kernel_cmd) AtomicCluster = devices.AtomicCluster if options.big_cpus + options.little_cpus == 0: m5.util.panic("Empty CPU clusters") # big cluster if options.big_cpus > 0: if options.atomic: system.bigCluster = AtomicCluster(system, options.big_cpus, options.big_cpu_clock) else: system.bigCluster = BigCluster(system, options.big_cpus, options.big_cpu_clock) mem_mode = system.bigCluster.memoryMode() # little cluster if options.little_cpus > 0: if options.atomic: system.littleCluster = AtomicCluster(system, options.little_cpus, options.little_cpu_clock) else: system.littleCluster = LittleCluster(system, options.little_cpus, options.little_cpu_clock) mem_mode = system.littleCluster.memoryMode() if options.big_cpus > 0 and options.little_cpus > 0: if system.bigCluster.memoryMode() != system.littleCluster.memoryMode(): m5.util.panic("Memory mode missmatch among CPU clusters") system.mem_mode = mem_mode # create caches system.addCaches(options.caches, options.last_cache_level) if not options.caches: if options.big_cpus > 0 and system.bigCluster.requireCaches(): m5.util.panic("Big CPU model requires caches") if options.little_cpus > 0 and system.littleCluster.requireCaches(): m5.util.panic("Little CPU model requires caches") # Linux device tree system.dtb_filename = SysPaths.binary(options.dtb) # Get and load from the chkpt or simpoint checkpoint if options.restore_from is not None: m5.instantiate(options.restore_from) else: m5.instantiate() # start simulation (and drop checkpoints when requested) while True: event = m5.simulate() exit_msg = event.getCause() if exit_msg == "checkpoint": print "Dropping checkpoint at tick %d" % m5.curTick() cpt_dir = os.path.join(m5.options.outdir, "cpt.%d" % m5.curTick()) m5.checkpoint(os.path.join(cpt_dir)) print "Checkpoint done." else: print exit_msg, " @ ", m5.curTick() break sys.exit(event.getCode())
def run(options, root, testsys, cpu_class): if options.maxtick: maxtick = options.maxtick elif options.maxtime: simtime = m5.ticks.seconds(simtime) print "simulating for: ", simtime maxtick = simtime else: maxtick = m5.MaxTick if options.checkpoint_dir: cptdir = options.checkpoint_dir elif m5.options.outdir: cptdir = m5.options.outdir else: cptdir = getcwd() if options.fast_forward and options.checkpoint_restore != None: fatal("Can't specify both --fast-forward and --checkpoint-restore") if options.standard_switch and not options.caches: fatal("Must specify --caches when using --standard-switch") np = options.num_cpus max_checkpoints = options.max_checkpoints switch_cpus = None if options.prog_interval: for i in xrange(np): testsys.cpu[i].progress_interval = options.prog_interval if options.maxinsts: for i in xrange(np): testsys.cpu[i].max_insts_any_thread = options.maxinsts if cpu_class: switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i)) for i in xrange(np)] for i in xrange(np): if options.fast_forward: testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) switch_cpus[i].system = testsys switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus[i].clock = testsys.cpu[0].clock # simulation period if options.maxinsts: switch_cpus[i].max_insts_any_thread = options.maxinsts # Add checker cpu if selected if options.checker: switch_cpus[i].addCheckerCpu() testsys.switch_cpus = switch_cpus switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] if options.standard_switch: if not options.caches: # O3 CPU must have a cache to work. print "O3 CPU must be used with caches" sys.exit(1) switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) for i in xrange(np)] switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) for i in xrange(np)] for i in xrange(np): switch_cpus[i].system = testsys switch_cpus_1[i].system = testsys switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus_1[i].workload = testsys.cpu[i].workload switch_cpus[i].clock = testsys.cpu[0].clock switch_cpus_1[i].clock = testsys.cpu[0].clock # if restoring, make atomic cpu simulate only a few instructions if options.checkpoint_restore != None: testsys.cpu[i].max_insts_any_thread = 1 # Fast forward to specified location if we are not restoring elif options.fast_forward: testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) # Fast forward to a simpoint (warning: time consuming) elif options.simpoint: if testsys.cpu[i].workload[0].simpoint == 0: fatal('simpoint not found') testsys.cpu[i].max_insts_any_thread = \ testsys.cpu[i].workload[0].simpoint # No distance specified, just switch else: testsys.cpu[i].max_insts_any_thread = 1 # warmup period if options.warmup_insts: switch_cpus[i].max_insts_any_thread = options.warmup_insts # simulation period if options.maxinsts: switch_cpus_1[i].max_insts_any_thread = options.maxinsts # attach the checker cpu if selected if options.checker: switch_cpus[i].addCheckerCpu() switch_cpus_1[i].addCheckerCpu() testsys.switch_cpus = switch_cpus testsys.switch_cpus_1 = switch_cpus_1 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] # set the checkpoint in the cpu before m5.instantiate is called if options.take_checkpoints != None and \ (options.simpoint or options.at_instruction): offset = int(options.take_checkpoints) # Set an instruction break point if options.simpoint: for i in xrange(np): if testsys.cpu[i].workload[0].simpoint == 0: fatal('no simpoint for testsys.cpu[%d].workload[0]', i) checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset testsys.cpu[i].max_insts_any_thread = checkpoint_inst # used for output below options.take_checkpoints = checkpoint_inst else: options.take_checkpoints = offset # Set all test cpus with the right number of instructions # for the upcoming simulation for i in xrange(np): testsys.cpu[i].max_insts_any_thread = offset checkpoint_dir = None if options.checkpoint_restore != None: from os.path import isdir, exists from os import listdir import re if not isdir(cptdir): fatal("checkpoint dir %s does not exist!", cptdir) if options.at_instruction or options.simpoint: inst = options.checkpoint_restore if options.simpoint: # assume workload 0 has the simpoint if testsys.cpu[0].workload[0].simpoint == 0: fatal('Unable to find simpoint') inst += int(testsys.cpu[0].workload[0].simpoint) checkpoint_dir = joinpath(cptdir, "cpt.%s.%s" % (options.bench, inst)) if not exists(checkpoint_dir): fatal("Unable to find checkpoint directory %s", checkpoint_dir) else: dirs = listdir(cptdir) expr = re.compile('cpt\.([0-9]*)') cpts = [] for dir in dirs: match = expr.match(dir) if match: cpts.append(match.group(1)) cpts.sort(lambda a,b: cmp(long(a), long(b))) cpt_num = options.checkpoint_restore if cpt_num > len(cpts): fatal('Checkpoint %d not found', cpt_num) ## Adjust max tick based on our starting tick maxtick = maxtick - int(cpts[cpt_num - 1]) checkpoint_dir = joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]) m5.instantiate(checkpoint_dir) if options.standard_switch or cpu_class: if options.standard_switch: print "Switch at instruction count:%s" % \ str(testsys.cpu[0].max_insts_any_thread) exit_event = m5.simulate() elif cpu_class and options.fast_forward: print "Switch at instruction count:%s" % \ str(testsys.cpu[0].max_insts_any_thread) exit_event = m5.simulate() else: print "Switch at curTick count:%s" % str(10000) exit_event = m5.simulate(10000) print "Switched CPUS @ tick %s" % (m5.curTick()) # when you change to Timing (or Atomic), you halt the system # given as argument. When you are finished with the system # changes (including switchCpus), you must resume the system # manually. You DON'T need to resume after just switching # CPUs if you haven't changed anything on the system level. m5.changeToTiming(testsys) m5.switchCpus(switch_cpu_list) m5.resume(testsys) if options.standard_switch: print "Switch at instruction count:%d" % \ (testsys.switch_cpus[0].max_insts_any_thread) #warmup instruction count may have already been set if options.warmup_insts: exit_event = m5.simulate() else: exit_event = m5.simulate(options.warmup) print "Switching CPUS @ tick %s" % (m5.curTick()) print "Simulation ends instruction count:%d" % \ (testsys.switch_cpus_1[0].max_insts_any_thread) m5.drain(testsys) m5.switchCpus(switch_cpu_list1) m5.resume(testsys) num_checkpoints = 0 exit_cause = '' # If we're taking and restoring checkpoints, use checkpoint_dir # option only for finding the checkpoints to restore from. This # lets us test checkpointing by restoring from one set of # checkpoints, generating a second set, and then comparing them. if options.take_checkpoints and options.checkpoint_restore: if m5.options.outdir: cptdir = m5.options.outdir else: cptdir = getcwd() # Checkpoints being taken via the command line at <when> and at # subsequent periods of <period>. Checkpoint instructions # received from the benchmark running are ignored and skipped in # favor of command line checkpoint instructions. if options.take_checkpoints != None : if options.at_instruction or options.simpoint: checkpoint_inst = int(options.take_checkpoints) # maintain correct offset if we restored from some instruction if options.checkpoint_restore != None: checkpoint_inst += options.checkpoint_restore print "Creating checkpoint at inst:%d" % (checkpoint_inst) exit_event = m5.simulate() print "exit cause = %s" % (exit_event.getCause()) # skip checkpoint instructions should they exist while exit_event.getCause() == "checkpoint": exit_event = m5.simulate() if exit_event.getCause() == \ "a thread reached the max instruction count": m5.checkpoint(joinpath(cptdir, "cpt.%s.%d" % \ (options.bench, checkpoint_inst))) print "Checkpoint written." num_checkpoints += 1 if exit_event.getCause() == "user interrupt received": exit_cause = exit_event.getCause(); else: when, period = options.take_checkpoints.split(",", 1) when = int(when) period = int(period) exit_event = m5.simulate(when) while exit_event.getCause() == "checkpoint": exit_event = m5.simulate(when - m5.curTick()) if exit_event.getCause() == "simulate() limit reached": m5.checkpoint(joinpath(cptdir, "cpt.%d")) num_checkpoints += 1 sim_ticks = when exit_cause = "maximum %d checkpoints dropped" % max_checkpoints while num_checkpoints < max_checkpoints and \ exit_event.getCause() == "simulate() limit reached": if (sim_ticks + period) > maxtick: exit_event = m5.simulate(maxtick - sim_ticks) exit_cause = exit_event.getCause() break else: exit_event = m5.simulate(period) sim_ticks += period while exit_event.getCause() == "checkpoint": exit_event = m5.simulate(sim_ticks - m5.curTick()) if exit_event.getCause() == "simulate() limit reached": m5.checkpoint(joinpath(cptdir, "cpt.%d")) num_checkpoints += 1 if exit_event.getCause() != "simulate() limit reached": exit_cause = exit_event.getCause(); else: # no checkpoints being taken via this script if options.fast_forward: m5.stats.reset() print "**** REAL SIMULATION ****" exit_event = m5.simulate(maxtick) while exit_event.getCause() == "checkpoint": m5.checkpoint(joinpath(cptdir, "cpt.%d")) num_checkpoints += 1 if num_checkpoints == max_checkpoints: exit_cause = "maximum %d checkpoints dropped" % max_checkpoints break exit_event = m5.simulate(maxtick - m5.curTick()) exit_cause = exit_event.getCause() if exit_cause == '': exit_cause = exit_event.getCause() print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_cause) if options.checkpoint_at_end: m5.checkpoint(joinpath(cptdir, "cpt.%d"))
dispatcher.cpu = host_cpu dispatcher.shader_pointer = shader dispatcher.cl_driver = driver ########################## Start simulation ######################## root = Root(system=system, full_system=False) m5.ticks.setGlobalFrequency('1THz') if options.abs_max_tick: maxtick = options.abs_max_tick else: maxtick = m5.MaxTick # Benchmarks support work item annotations Simulation.setWorkCountOptions(system, options) # Checkpointing is not supported by APU model if (options.checkpoint_dir != None or options.checkpoint_restore != None): fatal("Checkpointing not supported by apu model") checkpoint_dir = None m5.instantiate(checkpoint_dir) # Map workload to this address space host_cpu.workload[0].map(0x10000000, 0x200000000, 4096) exit_event = m5.simulate(maxtick) print "Ticks:", m5.curTick() print 'Exiting because ', exit_event.getCause() sys.exit(exit_event.getCode())
# obj1.master = obj2.slave <==> obj2.slave = obj1.master # But the direction of data stream between cache and the membus should be double direction ? system.cpu.createInterruptController() print type(system.cpu.interrupts.pio) system.cpu.interrupts.pio = system.membus.master system.cpu.interrupts.int_master = system.membus.slave system.cpu.interrupts.int_slave = system.membus.master system.system_port = system.membus.slave # x86 specific, allow system to r/w memory system.mem_ctrl = DDR3_1600_x64() # memory controller system.mem_ctrl.range = system.mem_ranges[0] system.mem_ctrl.port = system.membus.master process = LiveProcess() process.cmd = ['tests/test-progs/hello/bin/x86/linux/hello'] system.cpu.workload = process system.cpu.createThreads() root = Root(full_system=False, system=system) m5.instantiate() print 'Beginning simulation!' exit_event = m5.simulate() print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())
root.sim_quantum = int(1e9) # 1 ms # instantiate all of the objects we've created above m5.instantiate() # Keep running until we are done. print("Running the simulation") curCpus = 'system.cpu' exit_event = m5.simulate() while exit_event.getCause() != "m5_exit instruction encountered": if exit_event.getCause() == "user interrupt received": print("User interrupt. Exiting") break print('Pause @ tick %i because %s' % (m5.curTick(), exit_event.getCause())) if exit_event.getCause() == "switchcpu": if 'system.cpu' == curCpus: system.switchCpus(system.cpu, system.timingCpu) curCpus = 'system.timingCpu' else: system.switchCpus(system.timingCpu, system.cpu) curCpus = 'system.cpu' m5.stats.reset() exit_event = m5.simulate(100000000) elif exit_event.getCause() == "simulate() limit reached": if 'system.timingCpu' == curCpus: m5.stats.dump() m5.stats.reset() print("Continuing...")
system.mem_ctrl.range = system.mem_ranges[0] system.mem_ctrl.port = system.membus.master ''' Process setup ''' # Process process = Process() process.cmd = [binary] # Set CPU to execute process system.cpu.workload = process # Create the execution threads system.cpu.createThreads() ''' Simulation environment setup ''' # Root of the simulation root = Root(full_system=False, system=system) ''' Run the setup ''' # Instantiating the simulator m5.instantiate() # Run the simulator, kick off discrete event simulation exit_event = m5.simulate() m5.stats.dump() print("{} at tick {}.".format(exit_event.getCause(), m5.curTick()))
def run(options, root, testsys, cpu_class): # NOTE: this function is called from example from configs/example/ruby_fs.py # like this: "Simulation.run(options, root, system, FutureClass)" # so, "system" is "testsys" here; if options.maxtick: maxtick = options.maxtick elif options.maxtime: simtime = m5.ticks.seconds(simtime) print "simulating for: ", simtime maxtick = simtime else: maxtick = m5.MaxTick if options.checkpoint_dir: cptdir = options.checkpoint_dir elif m5.options.outdir: cptdir = m5.options.outdir else: cptdir = getcwd() if options.fast_forward and options.checkpoint_restore != None: fatal("Can't specify both --fast-forward and --checkpoint-restore") if options.standard_switch and not options.caches: fatal("Must specify --caches when using --standard-switch") np = options.num_cpus max_checkpoints = options.max_checkpoints switch_cpus = None if options.prog_interval: for i in xrange(np): testsys.cpu[i].progress_interval = options.prog_interval if options.maxinsts: for i in xrange(np): testsys.cpu[i].max_insts_any_thread = options.maxinsts if cpu_class: switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i)) for i in xrange(np)] for i in xrange(np): if options.fast_forward: testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) switch_cpus[i].system = testsys if not buildEnv['FULL_SYSTEM']: switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus[i].clock = testsys.cpu[0].clock # simulation period if options.maxinsts: switch_cpus[i].max_insts_any_thread = options.maxinsts testsys.switch_cpus = switch_cpus switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] if options.standard_switch: if not options.caches: # O3 CPU must have a cache to work. print "O3 CPU must be used with caches" sys.exit(1) switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) for i in xrange(np)] switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) for i in xrange(np)] for i in xrange(np): switch_cpus[i].system = testsys switch_cpus_1[i].system = testsys if not buildEnv['FULL_SYSTEM']: switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus_1[i].workload = testsys.cpu[i].workload switch_cpus[i].clock = testsys.cpu[0].clock switch_cpus_1[i].clock = testsys.cpu[0].clock # if restoring, make atomic cpu simulate only a few instructions if options.checkpoint_restore != None: testsys.cpu[i].max_insts_any_thread = 1 # Fast forward to specified location if we are not restoring elif options.fast_forward: testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) # Fast forward to a simpoint (warning: time consuming) elif options.simpoint: if testsys.cpu[i].workload[0].simpoint == 0: fatal('simpoint not found') testsys.cpu[i].max_insts_any_thread = \ testsys.cpu[i].workload[0].simpoint # No distance specified, just switch else: testsys.cpu[i].max_insts_any_thread = 1 # warmup period if options.warmup_insts: switch_cpus[i].max_insts_any_thread = options.warmup_insts # simulation period if options.maxinsts: switch_cpus_1[i].max_insts_any_thread = options.maxinsts testsys.switch_cpus = switch_cpus testsys.switch_cpus_1 = switch_cpus_1 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] # set the checkpoint in the cpu before m5.instantiate is called if options.take_checkpoints != None and \ (options.simpoint or options.at_instruction): offset = int(options.take_checkpoints) # Set an instruction break point if options.simpoint: for i in xrange(np): if testsys.cpu[i].workload[0].simpoint == 0: fatal('no simpoint for testsys.cpu[%d].workload[0]', i) checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset testsys.cpu[i].max_insts_any_thread = checkpoint_inst # used for output below options.take_checkpoints = checkpoint_inst else: options.take_checkpoints = offset # Set all test cpus with the right number of instructions # for the upcoming simulation for i in xrange(np): testsys.cpu[i].max_insts_any_thread = offset checkpoint_dir = None if options.checkpoint_restore != None: from os.path import isdir, exists from os import listdir import re if not isdir(cptdir): fatal("checkpoint dir %s does not exist!", cptdir) if options.at_instruction or options.simpoint: inst = options.checkpoint_restore if options.simpoint: # assume workload 0 has the simpoint if testsys.cpu[0].workload[0].simpoint == 0: fatal('Unable to find simpoint') inst += int(testsys.cpu[0].workload[0].simpoint) checkpoint_dir = joinpath(cptdir, "cpt.%s.%s" % (options.bench, inst)) if not exists(checkpoint_dir): fatal("Unable to find checkpoint directory %s", checkpoint_dir) else: dirs = listdir(cptdir) expr = re.compile('cpt\.([0-9]*)') cpts = [] for dir in dirs: match = expr.match(dir) if match: cpts.append(match.group(1)) cpts.sort(lambda a,b: cmp(long(a), long(b))) cpt_num = options.checkpoint_restore if cpt_num > len(cpts): fatal('Checkpoint %d not found', cpt_num) ## Adjust max tick based on our starting tick maxtick = maxtick - int(cpts[cpt_num - 1]) checkpoint_dir = joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]) m5.instantiate(checkpoint_dir) if options.standard_switch or cpu_class: if options.standard_switch: print "Switch at instruction count:%s" % \ str(testsys.cpu[0].max_insts_any_thread) exit_event = m5.simulate() elif cpu_class and options.fast_forward: print "Switch at instruction count:%s" % \ str(testsys.cpu[0].max_insts_any_thread) exit_event = m5.simulate() else: print "Switch at curTick count:%s" % str(10000) exit_event = m5.simulate(10000) print "Switched CPUS @ tick %s" % (m5.curTick()) # when you change to Timing (or Atomic), you halt the system # given as argument. When you are finished with the system # changes (including switchCpus), you must resume the system # manually. You DON'T need to resume after just switching # CPUs if you haven't changed anything on the system level. m5.changeToTiming(testsys) m5.switchCpus(switch_cpu_list) m5.resume(testsys) if options.standard_switch: print "Switch at instruction count:%d" % \ (testsys.switch_cpus[0].max_insts_any_thread) #warmup instruction count may have already been set if options.warmup_insts: exit_event = m5.simulate() else: exit_event = m5.simulate(options.warmup) print "Switching CPUS @ tick %s" % (m5.curTick()) print "Simulation ends instruction count:%d" % \ (testsys.switch_cpus_1[0].max_insts_any_thread) m5.drain(testsys) m5.switchCpus(switch_cpu_list1) m5.resume(testsys) num_checkpoints = 0 exit_cause = '' # If we're taking and restoring checkpoints, use checkpoint_dir # option only for finding the checkpoints to restore from. This # lets us test checkpointing by restoring from one set of # checkpoints, generating a second set, and then comparing them. if options.take_checkpoints and options.checkpoint_restore: if m5.options.outdir: cptdir = m5.options.outdir else: cptdir = getcwd() # Checkpoints being taken via the command line at <when> and at # subsequent periods of <period>. Checkpoint instructions # received from the benchmark running are ignored and skipped in # favor of command line checkpoint instructions. if options.take_checkpoints != None : if options.at_instruction or options.simpoint: checkpoint_inst = int(options.take_checkpoints) # maintain correct offset if we restored from some instruction if options.checkpoint_restore != None: checkpoint_inst += options.checkpoint_restore print "Creating checkpoint at inst:%d" % (checkpoint_inst) exit_event = m5.simulate() print "exit cause = %s" % (exit_event.getCause()) # skip checkpoint instructions should they exist while exit_event.getCause() == "checkpoint": exit_event = m5.simulate() if exit_event.getCause() == \ "a thread reached the max instruction count": m5.checkpoint(joinpath(cptdir, "cpt.%s.%d" % \ (options.bench, checkpoint_inst))) print "Checkpoint written." num_checkpoints += 1 if exit_event.getCause() == "user interrupt received": exit_cause = exit_event.getCause(); else: when, period = options.take_checkpoints.split(",", 1) when = int(when) period = int(period) exit_event = m5.simulate(when) while exit_event.getCause() == "checkpoint": exit_event = m5.simulate(when - m5.curTick()) if exit_event.getCause() == "simulate() limit reached": m5.checkpoint(joinpath(cptdir, "cpt.%d")) num_checkpoints += 1 sim_ticks = when exit_cause = "maximum %d checkpoints dropped" % max_checkpoints while num_checkpoints < max_checkpoints and \ exit_event.getCause() == "simulate() limit reached": if (sim_ticks + period) > maxtick: exit_event = m5.simulate(maxtick - sim_ticks) exit_cause = exit_event.getCause() break else: exit_event = m5.simulate(period) sim_ticks += period while exit_event.getCause() == "checkpoint": exit_event = m5.simulate(sim_ticks - m5.curTick()) if exit_event.getCause() == "simulate() limit reached": m5.checkpoint(joinpath(cptdir, "cpt.%d")) num_checkpoints += 1 if exit_event.getCause() != "simulate() limit reached": exit_cause = exit_event.getCause(); else: # no checkpoints being taken via this script if options.fast_forward: m5.stats.reset() print "**** REAL SIMULATION ****" #exit_event = m5.simulate(maxtick) # --Note1: Ruby is created in ruby_fs.py by # "Ruby.create_system(options, system, system.piobus, system._dma_devices)" # which assigned: "stats_filename = options.ruby_stats"; # definition of "create_system" is in configs/ruby/Ruby.py, which # instantiate the ctor of RubySystem: "system.ruby = RubySystem(...)"; #print testsys.ruby._cpu_ruby_ports #print testsys.ruby.network.ni_flit_size #print testsys.ruby.profiler.ruby_system # the ctor of RubySystem is defined in src/mem/ruby/system/RubySystem.py; # which sets some defaults: #print testsys.ruby.stats_filename # i.e., ruby.stats #print testsys.ruby.type #print testsys.ruby.random_seed #print testsys.ruby.clock #print testsys.ruby.block_size_bytes #print testsys.ruby.mem_size #print testsys.ruby.no_mem_vec # () cris: description of changes # --Note2: initially writing into ruby.stats was done with overwriting; # so, for each dump point the file was re-written; to fix that I # changed function "OutputDirectory::create(...)" from src/base/output.cc # which is called by "RubyExitCallback::process()" from src/mem/ruby/system/System.cc # function that is the one called at the end of the gem5 run # as a calback to dump all ruby stats (callback is "registered" in the # ctor of RubySystem::RubySystem() inside the same file...); # --Note3: using doExitCleanup inspired from src/python/m5/simulate.py # (inside which ini and json files are created; you need to rebuild each # time you change that Python file): #m5.internal.core.doExitCleanup( False) #clear callback queue? # --Note4: python/m5/internal/core.py describes "m5.internal.core"; # cris: here I want to dump stats every other delta ticks; # I need these to be able to generate reliability traces; NUM_OF_DUMPS = 100 num_i = 0 delta = maxtick/NUM_OF_DUMPS sim_ticks = m5.curTick() while (m5.curTick() < maxtick): sim_ticks += delta exit_event = m5.simulate(sim_ticks - m5.curTick()) if exit_event.getCause() == "simulate() limit reached": #--Note5: "doExitCleanup()" is described in src/sim/core.cc; # I changed it to be able to call it multiple times; #--Note6: do not dump stats in ruby.stats for last iteration # because it will be repeated once more via the exit callbacks # in src/python/m5/simulate.py... # Note6: next call of doExitCleanup does actually also reset/clear # the stats of ruby system via the RubyExitCallback::process() in # src/mem/ruby/system/System.cc if num_i < (NUM_OF_DUMPS-1): print "Dumping also ruby stats at inst %d to file: ruby.stats" %(num_i) m5.internal.core.doExitCleanup( False) #clear callback queue? print "Dumping gem5 stats at inst %d to file: stats.txt" %(num_i) # --Note7: dump() wites into stats.txt; dump() is defined in # src/python/m5/stats/__init__.py and does its # thing via the functions described in base/stats/text.cc #atexit.register(stats.dump) <--- does not work (from simulate.py) m5.stats.dump() m5.stats.reset() # <--- what does it actually do? num_i += 1 # alex's changes: #while exit_event.getCause() != "m5_exit instruction encountered": # m5.stats.dump() # m5.stats.reset() # exit_event = m5.simulate(maxtick) #while exit_event.getCause() == "checkpoint": # m5.checkpoint(joinpath(cptdir, "cpt.%d")) # num_checkpoints += 1 # if num_checkpoints == max_checkpoints: # exit_cause = "maximum %d checkpoints dropped" % max_checkpoints # break # exit_event = m5.simulate(maxtick - m5.curTick()) # exit_cause = exit_event.getCause() if exit_cause == '': exit_cause = exit_event.getCause() print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_cause) if options.checkpoint_at_end: m5.checkpoint(joinpath(cptdir, "cpt.%d"))
system.cpu = TimingSimpleCPU() system.membus = SystemXBar() system.cpu.icache_port = system.membus.slave system.cpu.dcache_port = system.membus.slave system.cpu.createInterruptController() system.cpu.interrupts[0].pio = system.membus.master system.cpu.interrupts[0].int_master = system.membus.slave system.cpu.interrupts[0].int_slave = system.membus.master system.system_port = system.membus.slave system.mem_ctrl = DDR3_1600_8x8() system.mem_ctrl.range = system.mem_ranges[0] system.mem_ctrl.port = system.membus.master process = Process() #process.cmd = ['tests/test-progs/hello/bin/x86/linux/hello'] process.cmd = ['tests/test-progs/hello/bin/x86/linux/loop'] system.cpu.workload = process system.cpu.createThreads() root = Root(full_system=False, system=system) m5.instantiate() print "Beginning Simulation" exit_event = m5.simulate() print 'Exiting @ tick %i' % (m5.curTick())
system.system_port = system.membus.slave #Caches if options.caches or options.l2cache: system.iocache = IOCache(addr_ranges=[system.physmem.range]) system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave else: system.iobridge = Bridge(delay='50ns', ranges = [system.physmem.range]) system.iobridge.slave = system.iobus.master system.iobridge.master = system.membus.slave CacheConfig.config_cache(options, system) ####################################################################### # # Start simulation root = Root(full_system=True, system=system) m5.instantiate() print '..... STARTING SIMULATION' exit_event = m5.simulate() exit_cause = exit_event.getCause() print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_cause)
# instantiate all of the objects we've created above m5.instantiate() globalStart = time.time() print("Running the simulation") print("Using cpu: {}".format(cpu)) exit_event = m5.simulate() if exit_event.getCause() == "workbegin": # Reached the start of ROI # start of ROI is marked by an # m5_work_begin() call print("Resetting stats at the start of ROI!") m5.stats.reset() start_tick = m5.curTick() start_insts = system.totalInsts() # switching cpu if argument cpu == atomic or timing if cpu == 'atomic': system.switchCpus(system.cpu, system.atomicCpu) if cpu == 'timing': system.switchCpus(system.cpu, system.timingCpu) else: print("Unexpected termination of simulation !") exit() # Simulate the ROI exit_event = m5.simulate() # Reached the end of ROI # Finish executing the benchmark
def __call__(self): print("Progress! Time now %fs" % (m5.curTick()/1e12)) self.eventq.schedule(self, m5.curTick() + self.period)
isa = str(m5.defines.buildEnv['TARGET_ISA']).lower() # Run application and use the compiled ISA to find the binary # grab the specific path to the binary thispath = os.path.dirname(os.path.realpath(__file__)) binary = os.path.join(thispath, '../../../', 'tests/test-progs/threads/bin/', isa, 'linux/threads') # Create a process for a simple "multi-threaded" application process = Process() # Set the command # cmd is a list which begins with the executable (like argv) process.cmd = [binary] # Set the cpu to use the process as its workload and create thread contexts for cpu in system.cpu: cpu.workload = process cpu.createThreads() # Set up the pseudo file system for the threads function above config_filesystem(system) # set up the root SimObject and start the simulation root = Root(full_system=False, system=system) # instantiate all of the objects we've created above m5.instantiate() print("Beginning simulation!") exit_event = m5.simulate() print('Exiting @ tick {} because {}'.format(m5.curTick(), exit_event.getCause()))
ctrl.port = system.membus.master if args.dump_period: m5.internal.stats.periodicStatDump(int(args.dump_period * 1e9)) root = m5.objects.Root(full_system=False, system=system) if args.fast_forward: cpu_types[args.cpu_type].numThreads = args.num_threads system.switch_cpus = [ cpu_types[args.cpu_type](switched_out=True, cpu_id=i) for i in xrange(args.num_cpus) ] for i in xrange(args.num_cpus): system.cpu[i].max_insts_any_thread = args.fast_forward system.switch_cpus[i].system = system system.switch_cpus[i].workload = system.cpu[i].workload system.switch_cpus[i].clk_domain = system.cpu[i].clk_domain system.switch_cpus[i].progress_interval = system.cpu[ i].progress_interval system.switch_cpus[i].createThreads() if args.max_instructions: system.switch_cpus[i].max_insts_all_threads = args.max_instructions m5.instantiate(None) if args.fast_forward: exit_event = m5.simulate(args.stop_at_tick) m5.switchCpus(system, [(system.cpu[i], system.switch_cpus[i]) for i in xrange(args.num_cpus)]) exit_event = m5.simulate(args.stop_at_tick - m5.curTick()) print("Exiting at tick %i because %s" % (m5.curTick(), exit_event.getCause()))
for (i, cpu) in enumerate(cpus): # # Tie the cpu memtester ports to the correct system ports # cpu.port = system.ruby._cpu_ports[i].slave # # Since the memtester is incredibly bursty, increase the deadlock # threshold to 5 million cycles # system.ruby._cpu_ports[i].deadlock_threshold = 5000000 # ----------------------- # run simulation # ----------------------- root = Root(full_system=False, system=system) root.system.mem_mode = 'timing' # Not much point in this being higher than the L1 latency m5.ticks.setGlobalFrequency('1ns') # instantiate configuration m5.instantiate() # simulate until program terminates exit_event = m5.simulate(options.abs_max_tick) print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause())
for core in system.cpu: core.workload = process core.createThreads() print(bcol.OK("Done")) print("") print(bcol.I("Instantiating system ...")) root = Root(full_system=False, system=system) m5.instantiate() print(bcol.OK("Done")) print("") print(bcol.H( \ "*********************** Beginning gem5 simulation ************************")) simulation = m5.simulate() if simulation.getCause() == "exiting with last active thread context": print(bcol.H( \ "**************************************************************************")) print(bcol.OK("Done.")) print(bcol.OK("Finished at tick %i." % (m5.curTick()))) print(bcol.OK("Status: %s." % (simulation.getCause()))) print(bcol.H( \ "**************************************************************************")) else: print(bcol.H( \ "**************************************************************************")) print(bcol.E("Status: %s." % (simulation.getCause()))) print(bcol.H( \ "**************************************************************************"))
def run_system_with_cpu( process, options, output_dir, warmup_cpu_class=None, warmup_instructions=0, real_cpu_create_function=lambda cpu_id: DerivO3CPU(cpu_id=cpu_id), ): # Override the -d outdir --outdir option to gem5 m5.options.outdir = output_dir m5.core.setOutputDir(m5.options.outdir) m5.stats.reset() max_tick = options.abs_max_tick if options.rel_max_tick: max_tick = options.rel_max_tick elif options.maxtime: max_tick = int(options.maxtime * 1000 * 1000 * 1000 * 1000) eprint("Simulating until tick=%s" % (max_tick)) real_cpus = [real_cpu_create_function(0)] mem_mode = real_cpus[0].memory_mode() if warmup_cpu_class: warmup_cpus = [warmup_cpu_class(cpu_id=0)] warmup_cpus[0].max_insts_any_thread = warmup_instructions else: warmup_cpus = real_cpus system = System(cpu = warmup_cpus, mem_mode = mem_mode, mem_ranges = [AddrRange(options.mem_size)], cache_line_size = options.cacheline_size) system.multi_thread = False system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) system.clk_domain = SrcClockDomain(clock = options.sys_clock, voltage_domain = system.voltage_domain) system.cpu_voltage_domain = VoltageDomain() system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, voltage_domain = system.cpu_voltage_domain) system.cache_line_size = options.cacheline_size if warmup_cpu_class: for cpu in real_cpus: cpu.clk_domain = system.cpu_clk_domain cpu.workload = process cpu.system = system cpu.switched_out = True cpu.createThreads() system.switch_cpus = real_cpus for cpu in system.cpu: cpu.clk_domain = system.cpu_clk_domain cpu.workload = process if options.prog_interval: cpu.progress_interval = options.prog_interval cpu.createThreads(); MemClass = Simulation.setMemClass(options) system.membus = SystemXBar() system.system_port = system.membus.slave system.cpu[0].connectAllPorts(system.membus) MemConfig.config_mem(options, system) root = Root(full_system = False, system = system) m5.options.outdir = output_dir m5.instantiate(None) # None == no checkpoint if warmup_cpu_class: eprint("Running warmup with warmup CPU class (%d instrs.)" % (warmup_instructions)) eprint("Starting simulation") exit_event = m5.simulate(max_tick) if warmup_cpu_class: max_tick -= m5.curTick() m5.stats.reset() debug_print("Finished warmup; running real simulation") m5.switchCpus(system, real_cpus) exit_event = m5.simulate(max_tick) eprint("Done simulation @ tick = %s: %s" % (m5.curTick(), exit_event.getCause())) m5.stats.dump()
system.readfile = writeBenchScript(m5.options.outdir, benchmark_name, benchmark_size, synthetic) m5.disableAllListeners() # set up the root SimObject and start the simulation root = Root(full_system = True, system = system) root.sim_quantum = int(1e9) # 1 ms # instantiate all of the objects we've created above m5.instantiate() print("Running the simulation with: ", system.cpu) exit_event = m5.simulate() print('Exiting @ tick {} because {}' .format(m5.curTick(), exit_event.getCause())) if exit_event.getCause() == "work started count reach": m5.stats.reset() start_tick = m5.curTick() start_insts = system.totalInsts() if cpu_type != 'kvm': system.switchToTiming() print("Switch to detailed cpu model") else: print("ROI is not annotated!") print('Exiting @ tick {} because {}' .format(m5.curTick(), exit_event.getCause())) exit() exit_event = m5.simulate()
if m5.defines.buildEnv['TARGET_ISA'] == "x86": system.cpu.interrupts[0].pio = system.membus.master system.cpu.interrupts[0].int_master = system.membus.slave system.cpu.interrupts[0].int_slave = system.membus.master # Connect the system up to the membus system.system_port = system.membus.slave # Create a DDR3 memory controller system.mem_ctrl = DDR3_1600_x64() system.mem_ctrl.range = system.mem_ranges[0] system.mem_ctrl.port = system.membus.master # Create a process for a simple "Hello World" application process = LiveProcess() # Set the command # cmd is a list which begins with the executable (like argv) process.cmd = [binary] # Set the cpu to use the process as its workload and create thread contexts system.cpu.workload = process system.cpu.createThreads() # set up the root SimObject and start the simulation root = Root(full_system=False, system=system) # instantiate all of the objects we've created above m5.instantiate() print "Beginning simulation!" exit_event = m5.simulate() print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())
def run(options, root, testsys, cpu_class): if options.maxtick: maxtick = options.maxtick elif options.maxtime: simtime = m5.ticks.seconds(simtime) print "simulating for: ", simtime maxtick = simtime else: maxtick = m5.MaxTick if options.checkpoint_dir: cptdir = options.checkpoint_dir elif m5.options.outdir: cptdir = m5.options.outdir else: cptdir = getcwd() if options.fast_forward and options.checkpoint_restore != None: fatal("Can't specify both --fast-forward and --checkpoint-restore") if options.standard_switch and not options.caches: fatal("Must specify --caches when using --standard-switch") if options.standard_switch and options.repeat_switch: fatal("Can't specify both --standard-switch and --repeat-switch") if options.repeat_switch and options.take_checkpoints: fatal("Can't specify both --repeat-switch and --take-checkpoints") np = options.num_cpus switch_cpus = None if options.prog_interval: for i in xrange(np): testsys.cpu[i].progress_interval = options.prog_interval if options.maxinsts: for i in xrange(np): testsys.cpu[i].max_insts_any_thread = options.maxinsts if cpu_class: switch_cpus = [ cpu_class(defer_registration=True, cpu_id=(i)) for i in xrange(np) ] for i in xrange(np): if options.fast_forward: testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) switch_cpus[i].system = testsys switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus[i].clock = testsys.cpu[i].clock # simulation period if options.maxinsts: switch_cpus[i].max_insts_any_thread = options.maxinsts # Add checker cpu if selected if options.checker: switch_cpus[i].addCheckerCpu() testsys.switch_cpus = switch_cpus switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] if options.repeat_switch: if options.cpu_type == "arm_detailed": if not options.caches: print "O3 CPU must be used with caches" sys.exit(1) repeat_switch_cpus = [O3_ARM_v7a_3(defer_registration=True, \ cpu_id=(i)) for i in xrange(np)] elif options.cpu_type == "detailed": if not options.caches: print "O3 CPU must be used with caches" sys.exit(1) repeat_switch_cpus = [DerivO3CPU(defer_registration=True, \ cpu_id=(i)) for i in xrange(np)] elif options.cpu_type == "inorder": print "inorder CPU switching not supported" sys.exit(1) elif options.cpu_type == "timing": repeat_switch_cpus = [TimingSimpleCPU(defer_registration=True, \ cpu_id=(i)) for i in xrange(np)] else: repeat_switch_cpus = [AtomicSimpleCPU(defer_registration=True, \ cpu_id=(i)) for i in xrange(np)] for i in xrange(np): repeat_switch_cpus[i].system = testsys repeat_switch_cpus[i].workload = testsys.cpu[i].workload repeat_switch_cpus[i].clock = testsys.cpu[i].clock if options.maxinsts: repeat_switch_cpus[i].max_insts_any_thread = options.maxinsts if options.checker: repeat_switch_cpus[i].addCheckerCpu() testsys.repeat_switch_cpus = repeat_switch_cpus if cpu_class: repeat_switch_cpu_list = [(switch_cpus[i], repeat_switch_cpus[i]) for i in xrange(np)] else: repeat_switch_cpu_list = [(testsys.cpu[i], repeat_switch_cpus[i]) for i in xrange(np)] if options.standard_switch: switch_cpus = [ TimingSimpleCPU(defer_registration=True, cpu_id=(i)) for i in xrange(np) ] switch_cpus_1 = [ DerivO3CPU(defer_registration=True, cpu_id=(i)) for i in xrange(np) ] for i in xrange(np): switch_cpus[i].system = testsys switch_cpus_1[i].system = testsys switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus_1[i].workload = testsys.cpu[i].workload switch_cpus[i].clock = testsys.cpu[i].clock switch_cpus_1[i].clock = testsys.cpu[i].clock # if restoring, make atomic cpu simulate only a few instructions if options.checkpoint_restore != None: testsys.cpu[i].max_insts_any_thread = 1 # Fast forward to specified location if we are not restoring elif options.fast_forward: testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) # Fast forward to a simpoint (warning: time consuming) elif options.simpoint: if testsys.cpu[i].workload[0].simpoint == 0: fatal('simpoint not found') testsys.cpu[i].max_insts_any_thread = \ testsys.cpu[i].workload[0].simpoint # No distance specified, just switch else: testsys.cpu[i].max_insts_any_thread = 1 # warmup period if options.warmup_insts: switch_cpus[i].max_insts_any_thread = options.warmup_insts # simulation period if options.maxinsts: switch_cpus_1[i].max_insts_any_thread = options.maxinsts # attach the checker cpu if selected if options.checker: switch_cpus[i].addCheckerCpu() switch_cpus_1[i].addCheckerCpu() testsys.switch_cpus = switch_cpus testsys.switch_cpus_1 = switch_cpus_1 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] # set the checkpoint in the cpu before m5.instantiate is called if options.take_checkpoints != None and \ (options.simpoint or options.at_instruction): offset = int(options.take_checkpoints) # Set an instruction break point if options.simpoint: for i in xrange(np): if testsys.cpu[i].workload[0].simpoint == 0: fatal('no simpoint for testsys.cpu[%d].workload[0]', i) checkpoint_inst = int( testsys.cpu[i].workload[0].simpoint) + offset testsys.cpu[i].max_insts_any_thread = checkpoint_inst # used for output below options.take_checkpoints = checkpoint_inst else: options.take_checkpoints = offset # Set all test cpus with the right number of instructions # for the upcoming simulation for i in xrange(np): testsys.cpu[i].max_insts_any_thread = offset checkpoint_dir = None if options.checkpoint_restore != None: maxtick, checkpoint_dir = findCptDir(options, maxtick, cptdir, testsys) m5.instantiate(checkpoint_dir) if options.standard_switch or cpu_class: if options.standard_switch: print "Switch at instruction count:%s" % \ str(testsys.cpu[0].max_insts_any_thread) exit_event = m5.simulate() elif cpu_class and options.fast_forward: print "Switch at instruction count:%s" % \ str(testsys.cpu[0].max_insts_any_thread) exit_event = m5.simulate() else: print "Switch at curTick count:%s" % str(10000) exit_event = m5.simulate(10000) print "Switched CPUS @ tick %s" % (m5.curTick()) # when you change to Timing (or Atomic), you halt the system # given as argument. When you are finished with the system # changes (including switchCpus), you must resume the system # manually. You DON'T need to resume after just switching # CPUs if you haven't changed anything on the system level. m5.changeToTiming(testsys) m5.switchCpus(switch_cpu_list) m5.resume(testsys) if options.standard_switch: print "Switch at instruction count:%d" % \ (testsys.switch_cpus[0].max_insts_any_thread) #warmup instruction count may have already been set if options.warmup_insts: exit_event = m5.simulate() else: exit_event = m5.simulate(options.standard_switch) print "Switching CPUS @ tick %s" % (m5.curTick()) print "Simulation ends instruction count:%d" % \ (testsys.switch_cpus_1[0].max_insts_any_thread) m5.drain(testsys) m5.switchCpus(switch_cpu_list1) m5.resume(testsys) # If we're taking and restoring checkpoints, use checkpoint_dir # option only for finding the checkpoints to restore from. This # lets us test checkpointing by restoring from one set of # checkpoints, generating a second set, and then comparing them. if options.take_checkpoints and options.checkpoint_restore: if m5.options.outdir: cptdir = m5.options.outdir else: cptdir = getcwd() if options.take_checkpoints != None: # Checkpoints being taken via the command line at <when> and at # subsequent periods of <period>. Checkpoint instructions # received from the benchmark running are ignored and skipped in # favor of command line checkpoint instructions. exit_cause = scriptCheckpoints(options, maxtick, cptdir) else: if options.fast_forward: m5.stats.reset() print "**** REAL SIMULATION ****" # If checkpoints are being taken, then the checkpoint instruction # will occur in the benchmark code it self. if options.repeat_switch and maxtick > options.repeat_switch: exit_cause = repeatSwitch(testsys, repeat_switch_cpu_list, maxtick, options.repeat_switch) else: exit_cause = benchCheckpoints(options, maxtick, cptdir) print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_cause) if options.checkpoint_at_end: m5.checkpoint(joinpath(cptdir, "cpt.%d"))
root = Root(full_system=True, system=board) # sim_quantum must be set if KVM cores are used. root.sim_quantum = int(1e9) m5.instantiate() # We maintain the wall clock time. globalStart = time.time() print("Running the simulation") print("Using KVM cpu") start_tick = m5.curTick() end_tick = m5.curTick() m5.stats.reset() # We start the simulation exit_event = m5.simulate() # The first exit_event ends with a `workbegin` cause. This means that the # system booted successfully and the execution on the program started. if exit_event.getCause() == "workbegin": print("Done booting Linux") print("Resetting stats at the start of ROI!")
def run(options, root, testsys, cpu_class): if options.checkpoint_dir: cptdir = options.checkpoint_dir elif m5.options.outdir: cptdir = m5.options.outdir else: cptdir = getcwd() if options.fast_forward and options.checkpoint_restore != None: fatal("Can't specify both --fast-forward and --checkpoint-restore") if options.standard_switch and not options.caches: fatal("Must specify --caches when using --standard-switch") if options.standard_switch and options.repeat_switch: fatal("Can't specify both --standard-switch and --repeat-switch") if options.repeat_switch and options.take_checkpoints: fatal("Can't specify both --repeat-switch and --take-checkpoints") np = options.num_cpus switch_cpus = None if options.prog_interval: for i in xrange(np): testsys.cpu[i].progress_interval = options.prog_interval if options.maxinsts: for i in xrange(np): testsys.cpu[i].max_insts_any_thread = options.maxinsts if cpu_class: switch_cpus = [cpu_class(switched_out=True, cpu_id=(i)) for i in xrange(np)] for i in xrange(np): if options.fast_forward: testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) switch_cpus[i].system = testsys switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain switch_cpus[i].progress_interval = testsys.cpu[i].progress_interval # simulation period if options.maxinsts: switch_cpus[i].max_insts_any_thread = options.maxinsts # Add checker cpu if selected if options.checker: switch_cpus[i].addCheckerCpu() testsys.switch_cpus = switch_cpus switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] if options.repeat_switch: switch_class = getCPUClass(options.cpu_type)[0] if switch_class.require_caches() and \ not options.caches: print "%s: Must be used with caches" % str(switch_class) sys.exit(1) if not switch_class.support_take_over(): print "%s: CPU switching not supported" % str(switch_class) sys.exit(1) repeat_switch_cpus = [switch_class(switched_out=True, \ cpu_id=(i)) for i in xrange(np)] for i in xrange(np): repeat_switch_cpus[i].system = testsys repeat_switch_cpus[i].workload = testsys.cpu[i].workload repeat_switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain if options.maxinsts: repeat_switch_cpus[i].max_insts_any_thread = options.maxinsts if options.checker: repeat_switch_cpus[i].addCheckerCpu() testsys.repeat_switch_cpus = repeat_switch_cpus if cpu_class: repeat_switch_cpu_list = [(switch_cpus[i], repeat_switch_cpus[i]) for i in xrange(np)] else: repeat_switch_cpu_list = [(testsys.cpu[i], repeat_switch_cpus[i]) for i in xrange(np)] if options.standard_switch: switch_cpus = [TimingSimpleCPU(switched_out=True, cpu_id=(i)) for i in xrange(np)] switch_cpus_1 = [DerivO3CPU(switched_out=True, cpu_id=(i)) for i in xrange(np)] for i in xrange(np): switch_cpus[i].system = testsys switch_cpus_1[i].system = testsys switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus_1[i].workload = testsys.cpu[i].workload switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain switch_cpus_1[i].clk_domain = testsys.cpu[i].clk_domain # if restoring, make atomic cpu simulate only a few instructions if options.checkpoint_restore != None: testsys.cpu[i].max_insts_any_thread = 1 # Fast forward to specified location if we are not restoring elif options.fast_forward: testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) # Fast forward to a simpoint (warning: time consuming) elif options.simpoint: if testsys.cpu[i].workload[0].simpoint == 0: fatal('simpoint not found') testsys.cpu[i].max_insts_any_thread = \ testsys.cpu[i].workload[0].simpoint # No distance specified, just switch else: testsys.cpu[i].max_insts_any_thread = 1 # warmup period if options.warmup_insts: switch_cpus[i].max_insts_any_thread = options.warmup_insts # simulation period if options.maxinsts: switch_cpus_1[i].max_insts_any_thread = options.maxinsts # attach the checker cpu if selected if options.checker: switch_cpus[i].addCheckerCpu() switch_cpus_1[i].addCheckerCpu() testsys.switch_cpus = switch_cpus testsys.switch_cpus_1 = switch_cpus_1 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] # set the checkpoint in the cpu before m5.instantiate is called if options.take_checkpoints != None and \ (options.simpoint or options.at_instruction): offset = int(options.take_checkpoints) # Set an instruction break point if options.simpoint: for i in xrange(np): if testsys.cpu[i].workload[0].simpoint == 0: fatal('no simpoint for testsys.cpu[%d].workload[0]', i) checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset testsys.cpu[i].max_insts_any_thread = checkpoint_inst # used for output below options.take_checkpoints = checkpoint_inst else: options.take_checkpoints = offset # Set all test cpus with the right number of instructions # for the upcoming simulation for i in xrange(np): testsys.cpu[i].max_insts_any_thread = offset if options.take_simpoint_checkpoints != None: simpoints, interval_length = parseSimpointAnalysisFile(options, testsys) checkpoint_dir = None if options.checkpoint_restore: cpt_starttick, checkpoint_dir = findCptDir(options, cptdir, testsys) m5.instantiate(checkpoint_dir) # Initialization is complete. If we're not in control of simulation # (that is, if we're a slave simulator acting as a component in another # 'master' simulator) then we're done here. The other simulator will # call simulate() directly. --initialize-only is used to indicate this. if options.initialize_only: return # Handle the max tick settings now that tick frequency was resolved # during system instantiation # NOTE: the maxtick variable here is in absolute ticks, so it must # include any simulated ticks before a checkpoint explicit_maxticks = 0 maxtick_from_abs = m5.MaxTick maxtick_from_rel = m5.MaxTick maxtick_from_maxtime = m5.MaxTick if options.abs_max_tick: maxtick_from_abs = options.abs_max_tick explicit_maxticks += 1 if options.rel_max_tick: maxtick_from_rel = options.rel_max_tick if options.checkpoint_restore: # NOTE: this may need to be updated if checkpoints ever store # the ticks per simulated second maxtick_from_rel += cpt_starttick if options.at_instruction or options.simpoint: warn("Relative max tick specified with --at-instruction or" \ " --simpoint\n These options don't specify the " \ "checkpoint start tick, so assuming\n you mean " \ "absolute max tick") explicit_maxticks += 1 if options.maxtime: maxtick_from_maxtime = m5.ticks.fromSeconds(options.maxtime) explicit_maxticks += 1 if explicit_maxticks > 1: warn("Specified multiple of --abs-max-tick, --rel-max-tick, --maxtime."\ " Using least") maxtick = min([maxtick_from_abs, maxtick_from_rel, maxtick_from_maxtime]) if options.checkpoint_restore != None and maxtick < cpt_starttick: fatal("Bad maxtick (%d) specified: " \ "Checkpoint starts starts from tick: %d", maxtick, cpt_starttick) if options.standard_switch or cpu_class: if options.standard_switch: print "Switch at instruction count:%s" % \ str(testsys.cpu[0].max_insts_any_thread) exit_event = m5.simulate() elif cpu_class and options.fast_forward: print "Switch at instruction count:%s" % \ str(testsys.cpu[0].max_insts_any_thread) exit_event = m5.simulate() else: print "Switch at curTick count:%s" % str(10000) exit_event = m5.simulate(10000) print "Switched CPUS @ tick %s" % (m5.curTick()) m5.switchCpus(testsys, switch_cpu_list) if options.standard_switch: print "Switch at instruction count:%d" % \ (testsys.switch_cpus[0].max_insts_any_thread) #warmup instruction count may have already been set if options.warmup_insts: exit_event = m5.simulate() else: exit_event = m5.simulate(options.standard_switch) print "Switching CPUS @ tick %s" % (m5.curTick()) print "Simulation ends instruction count:%d" % \ (testsys.switch_cpus_1[0].max_insts_any_thread) m5.switchCpus(testsys, switch_cpu_list1) # If we're taking and restoring checkpoints, use checkpoint_dir # option only for finding the checkpoints to restore from. This # lets us test checkpointing by restoring from one set of # checkpoints, generating a second set, and then comparing them. if (options.take_checkpoints or options.take_simpoint_checkpoints) \ and options.checkpoint_restore: if m5.options.outdir: cptdir = m5.options.outdir else: cptdir = getcwd() if options.take_checkpoints != None : # Checkpoints being taken via the command line at <when> and at # subsequent periods of <period>. Checkpoint instructions # received from the benchmark running are ignored and skipped in # favor of command line checkpoint instructions. exit_event = scriptCheckpoints(options, maxtick, cptdir) # Take SimPoint checkpoints elif options.take_simpoint_checkpoints != None: takeSimpointCheckpoints(simpoints, interval_length, cptdir) # Restore from SimPoint checkpoints elif options.restore_simpoint_checkpoint != None: restoreSimpointCheckpoint() else: if options.fast_forward: m5.stats.reset() print "**** REAL SIMULATION ****" # If checkpoints are being taken, then the checkpoint instruction # will occur in the benchmark code it self. if options.repeat_switch and maxtick > options.repeat_switch: exit_event = repeatSwitch(testsys, repeat_switch_cpu_list, maxtick, options.repeat_switch) else: exit_event = benchCheckpoints(options, maxtick, cptdir) print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()) if options.checkpoint_at_end: m5.checkpoint(joinpath(cptdir, "cpt.%d")) if not m5.options.interactive: sys.exit(exit_event.getCode())
import SimpleOpts from system import MySystem SimpleOpts.add_option("--script", default='', help="Script to execute in the simulated system") if __name__ == "__m5_main__": (opts, args) = SimpleOpts.parse_args() # create the system we are going to simulate system = MySystem(opts) # Read in the script file passed in via an option. # This file gets read and executed by the simulated system after boot. # Note: The disk image needs to be configured to do this. system.readfile = opts.script # set up the root SimObject and start the simulation root = Root(full_system=True, system=system) # instantiate all of the objects we've created above m5.instantiate() # Keep running until we are done. print "Running the simulation" exit_event = m5.simulate() print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())
tester.port = xbar.slave else: # Single tester testers[0].port = next_cache.cpu_side # Top level call to create the cache hierarchy, bottom up make_cache_level(cachespec, cache_proto, len(cachespec), None) # Connect the lowest level crossbar to the memory last_subsys = getattr(system, "l%dsubsys0" % len(cachespec)) last_subsys.xbar.master = system.physmem.port root = Root(full_system=False, system=system) if options.atomic: root.system.mem_mode = "atomic" else: root.system.mem_mode = "timing" # The system port is never used in the tester so merely connect it # to avoid problems root.system.system_port = last_subsys.xbar.slave # Instantiate configuration m5.instantiate() # Simulate until program terminates exit_event = m5.simulate(options.maxtick) print "Exiting @ tick", m5.curTick(), "because", exit_event.getCause()
def run(options, root, testsys, cpu_class): if options.checkpoint_dir: cptdir = options.checkpoint_dir elif m5.options.outdir: cptdir = m5.options.outdir else: cptdir = getcwd() if options.fast_forward and options.checkpoint_restore != None: fatal("Can't specify both --fast-forward and --checkpoint-restore") if options.standard_switch and not options.caches: fatal("Must specify --caches when using --standard-switch") if options.standard_switch and options.repeat_switch: fatal("Can't specify both --standard-switch and --repeat-switch") if options.repeat_switch and options.take_checkpoints: fatal("Can't specify both --repeat-switch and --take-checkpoints") np = options.num_cpus switch_cpus = None if options.prog_interval: for i in xrange(np): testsys.cpu[i].progress_interval = options.prog_interval if options.maxinsts: for i in xrange(np): testsys.cpu[i].max_insts_any_thread = options.maxinsts if cpu_class: switch_cpus = [ cpu_class(switched_out=True, cpu_id=(i)) for i in xrange(np) ] for i in xrange(np): if options.fast_forward: testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) switch_cpus[i].system = testsys switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain # simulation period if options.maxinsts: switch_cpus[i].max_insts_any_thread = options.maxinsts # Add checker cpu if selected if options.checker: switch_cpus[i].addCheckerCpu() testsys.switch_cpus = switch_cpus switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] if options.repeat_switch: switch_class = getCPUClass(options.cpu_type)[0] if switch_class.require_caches() and \ not options.caches: print "%s: Must be used with caches" % str(switch_class) sys.exit(1) if not switch_class.support_take_over(): print "%s: CPU switching not supported" % str(switch_class) sys.exit(1) repeat_switch_cpus = [switch_class(switched_out=True, \ cpu_id=(i)) for i in xrange(np)] for i in xrange(np): repeat_switch_cpus[i].system = testsys repeat_switch_cpus[i].workload = testsys.cpu[i].workload repeat_switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain if options.maxinsts: repeat_switch_cpus[i].max_insts_any_thread = options.maxinsts if options.checker: repeat_switch_cpus[i].addCheckerCpu() testsys.repeat_switch_cpus = repeat_switch_cpus if cpu_class: repeat_switch_cpu_list = [(switch_cpus[i], repeat_switch_cpus[i]) for i in xrange(np)] else: repeat_switch_cpu_list = [(testsys.cpu[i], repeat_switch_cpus[i]) for i in xrange(np)] if options.standard_switch: switch_cpus = [ TimingSimpleCPU(switched_out=True, cpu_id=(i)) for i in xrange(np) ] switch_cpus_1 = [ DerivO3CPU(switched_out=True, cpu_id=(i)) for i in xrange(np) ] for i in xrange(np): switch_cpus[i].system = testsys switch_cpus_1[i].system = testsys switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus_1[i].workload = testsys.cpu[i].workload switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain switch_cpus_1[i].clk_domain = testsys.cpu[i].clk_domain # if restoring, make atomic cpu simulate only a few instructions if options.checkpoint_restore != None: testsys.cpu[i].max_insts_any_thread = 1 # Fast forward to specified location if we are not restoring elif options.fast_forward: testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) # Fast forward to a simpoint (warning: time consuming) elif options.simpoint: if testsys.cpu[i].workload[0].simpoint == 0: fatal('simpoint not found') testsys.cpu[i].max_insts_any_thread = \ testsys.cpu[i].workload[0].simpoint # No distance specified, just switch else: testsys.cpu[i].max_insts_any_thread = 1 # warmup period if options.warmup_insts: switch_cpus[i].max_insts_any_thread = options.warmup_insts # simulation period if options.maxinsts: switch_cpus_1[i].max_insts_any_thread = options.maxinsts # attach the checker cpu if selected if options.checker: switch_cpus[i].addCheckerCpu() switch_cpus_1[i].addCheckerCpu() testsys.switch_cpus = switch_cpus testsys.switch_cpus_1 = switch_cpus_1 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] # set the checkpoint in the cpu before m5.instantiate is called if options.take_checkpoints != None and \ (options.simpoint or options.at_instruction): offset = int(options.take_checkpoints) # Set an instruction break point if options.simpoint: for i in xrange(np): if testsys.cpu[i].workload[0].simpoint == 0: fatal('no simpoint for testsys.cpu[%d].workload[0]', i) checkpoint_inst = int( testsys.cpu[i].workload[0].simpoint) + offset testsys.cpu[i].max_insts_any_thread = checkpoint_inst # used for output below options.take_checkpoints = checkpoint_inst else: options.take_checkpoints = offset # Set all test cpus with the right number of instructions # for the upcoming simulation for i in xrange(np): testsys.cpu[i].max_insts_any_thread = offset checkpoint_dir = None if options.checkpoint_restore: cpt_starttick, checkpoint_dir = findCptDir(options, cptdir, testsys) m5.instantiate(checkpoint_dir) # Handle the max tick settings now that tick frequency was resolved # during system instantiation # NOTE: the maxtick variable here is in absolute ticks, so it must # include any simulated ticks before a checkpoint explicit_maxticks = 0 maxtick_from_abs = m5.MaxTick maxtick_from_rel = m5.MaxTick maxtick_from_maxtime = m5.MaxTick if options.abs_max_tick: maxtick_from_abs = options.abs_max_tick explicit_maxticks += 1 if options.rel_max_tick: maxtick_from_rel = options.rel_max_tick if options.checkpoint_restore: # NOTE: this may need to be updated if checkpoints ever store # the ticks per simulated second maxtick_from_rel += cpt_starttick if options.at_instruction or options.simpoint: warn("Relative max tick specified with --at-instruction or" \ " --simpoint\n These options don't specify the " \ "checkpoint start tick, so assuming\n you mean " \ "absolute max tick") explicit_maxticks += 1 if options.maxtime: maxtick_from_maxtime = m5.ticks.fromSeconds(options.maxtime) explicit_maxticks += 1 if explicit_maxticks > 1: warn("Specified multiple of --abs-max-tick, --rel-max-tick, --maxtime."\ " Using least") maxtick = min([maxtick_from_abs, maxtick_from_rel, maxtick_from_maxtime]) if options.checkpoint_restore != None and maxtick < cpt_starttick: fatal("Bad maxtick (%d) specified: " \ "Checkpoint starts starts from tick: %d", maxtick, cpt_starttick) if options.standard_switch or cpu_class: if options.standard_switch: print "Switch at instruction count:%s" % \ str(testsys.cpu[0].max_insts_any_thread) exit_event = m5.simulate() elif cpu_class and options.fast_forward: print "Switch at instruction count:%s" % \ str(testsys.cpu[0].max_insts_any_thread) exit_event = m5.simulate() else: print "Switch at curTick count:%s" % str(10000) exit_event = m5.simulate(10000) print "Switched CPUS @ tick %s" % (m5.curTick()) m5.switchCpus(testsys, switch_cpu_list) if options.standard_switch: print "Switch at instruction count:%d" % \ (testsys.switch_cpus[0].max_insts_any_thread) #warmup instruction count may have already been set if options.warmup_insts: exit_event = m5.simulate() else: exit_event = m5.simulate(options.standard_switch) print "Switching CPUS @ tick %s" % (m5.curTick()) print "Simulation ends instruction count:%d" % \ (testsys.switch_cpus_1[0].max_insts_any_thread) m5.switchCpus(testsys, switch_cpu_list1) # If we're taking and restoring checkpoints, use checkpoint_dir # option only for finding the checkpoints to restore from. This # lets us test checkpointing by restoring from one set of # checkpoints, generating a second set, and then comparing them. if options.take_checkpoints and options.checkpoint_restore: if m5.options.outdir: cptdir = m5.options.outdir else: cptdir = getcwd() if options.take_checkpoints != None: # Checkpoints being taken via the command line at <when> and at # subsequent periods of <period>. Checkpoint instructions # received from the benchmark running are ignored and skipped in # favor of command line checkpoint instructions. exit_event = scriptCheckpoints(options, maxtick, cptdir) else: if options.fast_forward: m5.stats.reset() print "**** REAL SIMULATION ****" # If checkpoints are being taken, then the checkpoint instruction # will occur in the benchmark code it self. if options.repeat_switch and maxtick > options.repeat_switch: exit_event = repeatSwitch(testsys, repeat_switch_cpu_list, maxtick, options.repeat_switch) else: exit_event = benchCheckpoints(options, maxtick, cptdir) print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()) if options.checkpoint_at_end: m5.checkpoint(joinpath(cptdir, "cpt.%d")) if not m5.options.interactive: sys.exit(exit_event.getCode())