def convert_axis_to_fifo(self, axis_name: str) -> str:
assert len(self.get_fifo_directions(axis_name)) == 1, \
"axis interfaces should have one direction"
direction_axis = {
'consumed_by': 'produced_by',
'produced_by': 'consumed_by',
}[self.get_fifo_directions(axis_name)[0]]
data_width = self.ports[axis_name].width
# add FIFO registerings to provide timing isolation
fifo_name = 'tapa_fifo_' + axis_name
self.module.add_fifo_instance(name=fifo_name,
width=data_width+1, depth=2)
# add FIFO's wires
for suffix in rtl.STREAM_PORT_DIRECTION:
wire_name = rtl.wire_name(fifo_name, suffix)
wire_width = rtl.get_stream_width(suffix, data_width)
self.module.add_signals([ast.Wire(name=wire_name, width=wire_width)])
# add constant outputs for AXIS output ports
if direction_axis == 'consumed_by':
for axis_suffix, bit in rtl.AXIS_CONSTANTS.items():
port_name = self.module.find_port(axis_name, axis_suffix)
width = rtl.get_axis_port_width_int(axis_suffix, data_width)
self.module.add_logics([
ast.Assign(left=ast.Identifier(port_name),
right=ast.IntConst("%d'b%s"%(width, str(bit)*width)))])
# connect the FIFO to the AXIS interface
for suffix in self.get_fifo_suffixes(direction_axis):
wire_name = rtl.wire_name(fifo_name, suffix)
offset = 0
for axis_suffix in rtl.STREAM_TO_AXIS[suffix]:
port_name = self.module.find_port(axis_name, axis_suffix)
width = rtl.get_axis_port_width_int(axis_suffix, data_width)
if len(rtl.STREAM_TO_AXIS[suffix]) > 1:
wire = ast.Partselect(ast.Identifier(wire_name),
ast.IntConst(str(offset + width - 1)),
ast.IntConst(str(offset)))
else:
wire = ast.Identifier(wire_name)
self.assign_directional(
ast.Identifier(port_name), wire,
rtl.STREAM_PORT_DIRECTION[suffix])
offset += width
return fifo_name
Union)
import toposort
from haoda.backend import xilinx as hls
import tapa.autobridge as autobridge
from tapa import util
from tapa.verilog import ast
from tapa.verilog import xilinx as rtl
from .instance import Instance, Port
from .task import Task
_logger = logging.getLogger().getChild(__name__)
STATE00 = ast.IntConst("2'b00")
STATE01 = ast.IntConst("2'b01")
STATE11 = ast.IntConst("2'b11")
STATE10 = ast.IntConst("2'b10")
class InputError(Exception):
pass
class Program:
"""Describes a TAPA program.
Attributes:
top: Name of the top-level module.
work_dir: Working directory.
HANDSHAKE_RST_N,
HANDSHAKE_START,
)
HANDSHAKE_OUTPUT_PORTS = (
HANDSHAKE_DONE,
HANDSHAKE_IDLE,
HANDSHAKE_READY,
)
# const ast nodes
START = ast.Identifier(HANDSHAKE_START)
DONE = ast.Identifier(HANDSHAKE_DONE)
IDLE = ast.Identifier(HANDSHAKE_IDLE)
READY = ast.Identifier(HANDSHAKE_READY)
TRUE = ast.IntConst("1'b1")
FALSE = ast.IntConst("1'b0")
SENS_TYPE = 'posedge'
CLK = ast.Identifier(HANDSHAKE_CLK)
RST = ast.Identifier(HANDSHAKE_RST)
RST_N = ast.Identifier(HANDSHAKE_RST_N)
CLK_SENS_LIST = ast.SensList((ast.Sens(CLK, type=SENS_TYPE), ))
ALL_SENS_LIST = ast.SensList((ast.Sens(None, type='all'), ))
STATE = ast.Identifier('tapa_state')
BUILTIN_INSTANCES = {'hmss_0'}
OTHER_MODULES = {
'fifo_bram':
haoda.backend.xilinx.BRAM_FIFO_TEMPLATE.format(
name='fifo_bram',