def main(argv):
simscript = ''
testbenchfile = ''
wrapper = ''
stitchup = ''
original = ''
try:
opts, args = getopt.getopt(
argv, "hw:t:s:u:i",
["wrapper=", "tb=", "simscript=", "stitchup=", "orig="])
except getopt.GetoptError:
print 'Usage: python generateTB.py --wrapper stitchup_orig_wrapper.v --tb testbench.v --simscript vsim_script --stitchup stitchup.v --orig original.v'
sys.exit(2)
for opt, arg in opts:
if opt == '-h':
print 'Usage: python generateTB.py --wrapper stitchup_orig_wrapper.v --tb testbench.v --simscript vsim_script --stitchup stitchup.v --orig original.v'
sys.exit()
if opt in ("-w", "--wrapper"):
wrapper = arg
if opt in ("-t", "--tb"):
testbenchfile = arg
if opt in ("-s", "--simscript"):
simscript = arg
if opt in ("-u", "--stitchup"):
stitchup = arg
if opt in ("-i", "--orig"):
original = arg
infile = open(wrapper, 'r')
tboutfile = open(testbenchfile, 'w')
workoutfile = open(simscript + '_worklib', 'w')
simoutfile = open(simscript, 'w')
inString = infile.read()
signals = wH.getSignals(inString, 'topmost')
(inputlist, outputlist) = wH.gatherIOLists(wrapper, signals)
testbench = "//Testbench file for the stitchup wrapped project.\n"
testbench += "`timescale 1 ns / 1 ns\n"
testbench += "\nmodule tbtop (\n);\n\n"
#Instantiate a register for each input
for i in inputlist:
testbench += 'reg [' + str(i[1]) + ':' + str(
i[2]) + '] ' + i[0] + ';\n'
#Instantiate a wire for each output
for o in outputlist:
testbench += 'wire [' + str(o[1]) + ':' + str(
o[2]) + '] ' + o[0] + ';\n'
if o[0] == "check_state":
check_MSB = str(o[1]) #This is needed for the assertion check.
testbench += 'integer log;\n'
testbench += '\n\n'
#Clock generation
testbench += 'initial\n\tclk = 0;\nalways @(clk)\n\tclk <= #10 ~clk;\n\n'
#Initial conditions for clock and reset signals
#Pulses the reset condition
testbench += 'initial begin\n\tlog = $fopen(\"res.log\",\"w\");\n//$monitor("At t=%t clk=%b %b %b %b %d", $time, clk, reset, start, finish, return_val);\n@(negedge clk);\nreset <= 1;\n@(negedge clk);\nreset <= 0;\nstart <= 1;\n@(negedge clk);\nstart <= 0;\nend\n\n'
#Assert statement to makesure that the Error flag has never been signalled
testbench += 'always @(negedge clk) begin\n'
testbench += '\tif (check_state != 0) begin\n'
testbench += '\t\t$fwrite(log, "%d,\t%d,\t%d,\t%d,\t1",($time-50)/20, finish, return_val, check_state);\n'
testbench += '\t\t$display(\"CONFIGURATION MISMATCH, CFG ERROR DETECTED! %d\", check_state);\n'
testbench += '\t\t$fclose(log);\n'
testbench += '\t\t$finish;\n'
testbench += '\tend\n'
testbench += 'end\n\n'
#End condition
testbench += 'always @(finish) begin\n'
testbench += '\tif (finish == 1) begin\n'
testbench += '\t\t$fwrite(log, "%d,\t%d,\t%d,\t%d,\t0",($time-50)/20, finish, return_val, check_state);\n'
testbench += '\t\t$display("At t=%t clk=%b finish=%b return_val=%d", $time, clk, finish, return_val);\n'
testbench += '\t\t$display("Cycles: %d", ($time-50)/20);\n'
testbench += '\t\t$fclose(log);\n'
testbench += '\t\t$finish;\n'
testbench += '\tend\n'
testbench += 'end\n\n'
#Memory
testbench += 'initial begin\nwaitrequest <= 1;\n@(negedge clk);\n@(negedge clk);\nwaitrequest <= 0;\nend\n\n'
#Instantiate the wrapper module
testbench += 'topmost dut(\n'
for s in signals:
testbench += '\t.' + s + '( ' + s + ' ),\n'
testbench = testbench[:-2]
testbench += '\n);\n'
testbench += '\n\nendmodule\n'
tboutfile.write(testbench)
tboutfile.close()
#Build the file to compile the work libs
worklibs = 'rm -r -f work\n'
worklibs += 'source ./modelsim.config\n'
worklibs += 'vlib work\n'
worklibs += 'vlog ${GENERIC_DIVIDER_LIBS}*.v\n'
worklibs += 'vlog ${VERILOG_LIBS}*.v ./' + wrapper + ' ./' + testbenchfile + ' ./' + stitchup + ' ./' + original + '\n'
worklibs += 'vlog ${SYSTEMVERILOG_LIBS}*.v\n'
workoutfile.write(worklibs)
workoutfile.close()
sim = 'source ./modelsim.config\n'
sim += 'vlog ./' + wrapper + ' ./' + testbenchfile + ' ./' + stitchup + ' ./' + original + '\n'
sim += 'vsim -c tbtop -do \"run 10000000000 ; echo [simstats]; quit -f;\"\n'
simoutfile.write(sim)
simoutfile.close()
def main(argv):
original = ''
stitchup = ''
wrapper = ''
dmrflag = False
noProtect = False
try:
opts, args = getopt.getopt(
argv, "ho:i:w:n:d",
["orig=", "stitchup=", "wrapper=", "np", "dmr"])
except getopt.GetoptError:
print 'Usage: python generateWrapper.py --origi original.v --stitchup stitchup.v --wrapper=protected.v --np --dmr'
sys.exit(2)
for opt, arg in opts:
if opt == '-h':
print 'Usage: python generateWrapper.py --origi original.v --stitchup stitchup.v --wrapper=protected.v --np --dmr'
sys.exit()
if opt in ("-o", "--orig"):
original = arg
if opt in ("-s", "--stitchup"):
stitchup = arg
if opt in ("-w", "--wrapper"):
wrapper = arg
if opt in ("--np"):
noProtect = True
if opt in ("--dmr"):
dmrflag = True
outfile = open(wrapper, 'w')
origString = open(original, 'r').read()
wrapperString = "//Stitchup toplevel wrapper for" + original + ", will flag an error on CFG faults.\n"
signals = wH.getSignals(origString, 'top')
#Declare the port list of the topmost module
wrapperString += "\nmodule topmost(\n"
for s in signals:
wrapperString += '\t' + s + ',\n'
if dmrflag:
wrapperString += '\tstart_dmr,\n'
wrapperString += '\tfinish_dmr,\n'
wrapperString += '\treturn_val_dmr,\n'
wrapperString = wrapperString[:-2]
wrapperString += '\n);\n\n'
#Instantiate the signals that are used in the I/O top level ports
#For this we need to grab the direction
(inputlist, outputlist) = wH.gatherIOLists(original, signals)
#Instantiate the input/output with the correct widths
for i in inputlist:
wrapperString += 'input [' + str(i[1]) + ':' + str(
i[2]) + '] ' + i[0] + ';\n'
if i[0] == 'start' and dmrflag:
wrapperString += 'input start_dmr;\n'
for o in outputlist:
if o[0] == 'finish' or o[0] == 'return_val':
wrapperString += 'output reg[' + str(o[1]) + ':' + str(
o[2]) + '] ' + o[0] + ';\n'
if dmrflag:
wrapperString += 'output reg[' + str(o[1]) + ':' + str(
o[2]) + '] ' + o[0] + '_dmr;\n'
elif o[0] == 'check_state':
wrapperString += 'output reg[31:0] check_state;\n'
else:
wrapperString += 'output wire [' + str(o[1]) + ':' + str(
o[2]) + '] ' + o[0] + ';\n'
wrapperString += 'wire [31:0] result;\n\n'
if dmrflag:
wrapperString += 'wire [31:0] result_dmr;\n\n'
wrapperString += '\nwire finish_orig, finish_stitchup;\n'
wrapperString += 'always @ (posedge clk)\nbegin\n'
wrapperString += '\tif(reset==1)\n'
wrapperString += '\tbegin\n'
wrapperString += '\t\treturn_val <= 0;\n'
wrapperString += '\t\tfinish <= 0;\n'
wrapperString += '\tend\n'
if noProtect == False:
wrapperString += '\tif(finish_orig==1 || errorFlag==1)\n'
else:
wrapperString += '\tif(finish_orig==1)\n'
wrapperString += '\tbegin\n'
wrapperString += '\t\treturn_val <= result;\n'
wrapperString += '\t\tfinish <= 1;\n'
wrapperString += '\tend\n'
wrapperString += 'end\n'
if dmrflag:
wrapperString += 'always @ (posedge clk)\nbegin\n'
wrapperString += '\tif(reset==1)\n'
wrapperString += '\tbegin\n'
wrapperString += '\t\treturn_val_dmr <= 0;\n'
wrapperString += '\t\tfinish_dmr <= 0;\n'
wrapperString += '\tend\n'
wrapperString += '\tif(finish_stitchup==1)\n'
wrapperString += '\tbegin\n'
wrapperString += '\t\treturn_val_dmr <= result_dmr;\n'
wrapperString += '\t\tfinish_dmr <= 1;\n'
wrapperString += '\tend\n'
wrapperString += 'end\n'
if noProtect == False:
#Instantiate the check_state XOR checking logic
#Get the bit width for the check_state register
for s in outputlist:
if s[0] == "check_state":
checkStateMSB = str(s[1])
checkStateLSB = str(s[2])
wrapperString += '\nwire [' + checkStateMSB + ':' + checkStateLSB + '] orig_check_state;\n'
wrapperString += 'wire [' + checkStateMSB + ':' + checkStateLSB + '] stitchup_check_state;\n'
wrapperString += 'reg [0:0] errorFlag;\n'
wrapperString += '\nalways @(posedge clk) begin\n'
wrapperString += '\tif(reset==1)\n'
wrapperString += '\tbegin\n'
wrapperString += '\t\terrorFlag <= 0;\n'
wrapperString += '\t\tcheck_state <= 0;\n'
wrapperString += '\tend\n'
wrapperString += '$display(\"%t, su=%d, orig=%d\",$time, stitchup_check_state, orig_check_state);\n'
wrapperString += '\tif ((orig_check_state != stitchup_check_state) && errorFlag == 0)\n'
wrapperString += '\tbegin\n'
wrapperString += '\t\tcheck_state <= 1 + stitchup_check_state;\n'
wrapperString += '\t\terrorFlag <= 1;\n'
wrapperString += '\tend\n'
if dmrflag == True:
wrapperString += '\tif ((result != result_dmr) && errorFlag == 0)\n'
wrapperString += '\tbegin\n'
wrapperString += '\t\terrorFlag <= 1;\n'
wrapperString += '\tend\n'
wrapperString += 'end\n'
#Instantiate the original LegUp component
wrapperString += '\ntop top_inst(\n'
for s in signals:
if s == "check_state":
wrapperString += '\t.check_state( orig_check_state )\n'
elif s == "finish":
wrapperString += '\t.finish( finish_orig ),\n'
elif s == "return_val":
wrapperString += '\t.return_val( result ),\n'
else:
wrapperString += '\t.' + s + '(' + s + '),\n'
wrapperString += ');\n'
if noProtect == False:
#Instantiate the StitchUp component
if dmrflag == True:
wrapperString += '\ntop stitchup_top_inst(\n'
else:
wrapperString += '\nstitchup_top stitchup_top_inst(\n'
for s in signals:
if s == "check_state":
wrapperString += '\t.check_state( stitchup_check_state )\n'
elif s == "return_val":
if dmrflag:
wrapperString += '\t.return_val( result_dmr ),\n'
else:
wrapperString += '\t.return_val( open ),\n'
elif s == "finish":
wrapperString += '\t.finish( finish_stitchup ),\n'
elif s == "start" and dmrflag:
wrapperString += '\t.start( start_dmr ),\n'
else:
wrapperString += '\t.' + s + '(' + s + '),\n'
wrapperString += ');\n'
wrapperString += 'endmodule\n'
outfile.write(wrapperString)
outfile.close()
def main(argv):
original = ''
stitchup = ''
wrapper = ''
dmrflag = False
noProtect = False
try:
opts, args = getopt.getopt(argv, "ho:i:w:n:d", ["orig=", "stitchup=", "wrapper=", "np", "dmr"])
except getopt.GetoptError:
print 'Usage: python generateWrapper.py --origi original.v --stitchup stitchup.v --wrapper=protected.v --np --dmr'
sys.exit(2)
for opt, arg in opts:
if opt == '-h':
print 'Usage: python generateWrapper.py --origi original.v --stitchup stitchup.v --wrapper=protected.v --np --dmr'
sys.exit()
if opt in ("-o", "--orig"):
original = arg
if opt in ("-s", "--stitchup"):
stitchup = arg
if opt in ("-w", "--wrapper"):
wrapper = arg
if opt in ("--np"):
noProtect = True
if opt in ("--dmr"):
dmrflag = True
outfile = open(wrapper, 'w')
origString = open(original, 'r').read()
wrapperString = "//Stitchup toplevel wrapper for" + original + ", will flag an error on CFG faults.\n"
signals = wH.getSignals(origString, 'top')
#Declare the port list of the topmost module
wrapperString += "\nmodule topmost(\n"
for s in signals:
wrapperString += '\t' + s +',\n'
if dmrflag:
wrapperString += '\tstart_dmr,\n'
wrapperString += '\tfinish_dmr,\n'
wrapperString += '\treturn_val_dmr,\n';
wrapperString = wrapperString[:-2]
wrapperString += '\n);\n\n'
#Instantiate the signals that are used in the I/O top level ports
#For this we need to grab the direction
(inputlist, outputlist) = wH.gatherIOLists(original, signals)
#Instantiate the input/output with the correct widths
for i in inputlist:
wrapperString += 'input [' + str(i[1]) + ':' + str(i[2]) +'] ' + i[0] + ';\n'
if i[0] == 'start' and dmrflag:
wrapperString += 'input start_dmr;\n'
for o in outputlist:
if o[0] == 'finish' or o[0] == 'return_val':
wrapperString += 'output reg[' + str(o[1]) + ':' + str(o[2]) + '] ' + o[0] + ';\n'
if dmrflag:
wrapperString += 'output reg[' + str(o[1]) + ':' + str(o[2]) + '] ' + o[0] + '_dmr;\n'
elif o[0] == 'check_state':
wrapperString += 'output reg[31:0] check_state;\n'
else:
wrapperString += 'output wire [' + str(o[1]) + ':' + str(o[2]) + '] ' + o[0] + ';\n'
wrapperString += 'wire [31:0] result;\n\n'
if dmrflag:
wrapperString += 'wire [31:0] result_dmr;\n\n'
wrapperString += '\nwire finish_orig, finish_stitchup;\n'
wrapperString += 'always @ (posedge clk)\nbegin\n'
wrapperString += '\tif(reset==1)\n'
wrapperString += '\tbegin\n'
wrapperString += '\t\treturn_val <= 0;\n'
wrapperString += '\t\tfinish <= 0;\n'
wrapperString += '\tend\n'
if noProtect == False:
wrapperString += '\tif(finish_orig==1 || errorFlag==1)\n'
else:
wrapperString += '\tif(finish_orig==1)\n'
wrapperString += '\tbegin\n'
wrapperString += '\t\treturn_val <= result;\n'
wrapperString += '\t\tfinish <= 1;\n'
wrapperString += '\tend\n'
wrapperString += 'end\n'
if dmrflag:
wrapperString += 'always @ (posedge clk)\nbegin\n'
wrapperString += '\tif(reset==1)\n'
wrapperString += '\tbegin\n'
wrapperString += '\t\treturn_val_dmr <= 0;\n'
wrapperString += '\t\tfinish_dmr <= 0;\n'
wrapperString += '\tend\n'
wrapperString += '\tif(finish_stitchup==1)\n'
wrapperString += '\tbegin\n'
wrapperString += '\t\treturn_val_dmr <= result_dmr;\n'
wrapperString += '\t\tfinish_dmr <= 1;\n'
wrapperString += '\tend\n'
wrapperString += 'end\n'
if noProtect == False :
#Instantiate the check_state XOR checking logic
#Get the bit width for the check_state register
for s in outputlist:
if s[0] == "check_state":
checkStateMSB = str(s[1])
checkStateLSB = str(s[2])
wrapperString += '\nwire [' + checkStateMSB + ':' + checkStateLSB + '] orig_check_state;\n'
wrapperString += 'wire [' + checkStateMSB + ':' + checkStateLSB + '] stitchup_check_state;\n'
wrapperString += 'reg [0:0] errorFlag;\n'
wrapperString += '\nalways @(posedge clk) begin\n'
wrapperString += '\tif(reset==1)\n'
wrapperString += '\tbegin\n'
wrapperString += '\t\terrorFlag <= 0;\n'
wrapperString += '\t\tcheck_state <= 0;\n'
wrapperString += '\tend\n'
wrapperString += '$display(\"%t, su=%d, orig=%d\",$time, stitchup_check_state, orig_check_state);\n'
wrapperString += '\tif ((orig_check_state != stitchup_check_state) && errorFlag == 0)\n'
wrapperString += '\tbegin\n'
wrapperString += '\t\tcheck_state <= 1 + stitchup_check_state;\n'
wrapperString += '\t\terrorFlag <= 1;\n'
wrapperString += '\tend\n'
if dmrflag == True:
wrapperString += '\tif ((result != result_dmr) && errorFlag == 0)\n'
wrapperString += '\tbegin\n'
wrapperString += '\t\terrorFlag <= 1;\n'
wrapperString += '\tend\n'
wrapperString += 'end\n'
#Instantiate the original LegUp component
wrapperString += '\ntop top_inst(\n'
for s in signals:
if s == "check_state":
wrapperString += '\t.check_state( orig_check_state )\n'
elif s == "finish":
wrapperString += '\t.finish( finish_orig ),\n'
elif s == "return_val":
wrapperString += '\t.return_val( result ),\n'
else:
wrapperString += '\t.' + s + '(' + s + '),\n'
wrapperString += ');\n'
if noProtect == False :
#Instantiate the StitchUp component
if dmrflag == True:
wrapperString += '\ntop stitchup_top_inst(\n'
else:
wrapperString += '\nstitchup_top stitchup_top_inst(\n'
for s in signals:
if s == "check_state":
wrapperString += '\t.check_state( stitchup_check_state )\n'
elif s == "return_val":
if dmrflag:
wrapperString += '\t.return_val( result_dmr ),\n'
else:
wrapperString += '\t.return_val( open ),\n'
elif s == "finish":
wrapperString += '\t.finish( finish_stitchup ),\n'
elif s == "start" and dmrflag:
wrapperString += '\t.start( start_dmr ),\n'
else:
wrapperString += '\t.' + s + '(' + s + '),\n'
wrapperString += ');\n'
wrapperString += 'endmodule\n'
outfile.write(wrapperString)
outfile.close()
def main(argv):
simscript = ''
testbenchfile = ''
wrapper = ''
stitchup=''
original=''
try:
opts, args = getopt.getopt(argv, "hw:t:s:u:i", ["wrapper=", "tb=", "simscript=", "stitchup=", "orig="])
except getopt.GetoptError:
print 'Usage: python generateTB.py --wrapper stitchup_orig_wrapper.v --tb testbench.v --simscript vsim_script --stitchup stitchup.v --orig original.v'
sys.exit(2)
for opt, arg in opts:
if opt == '-h':
print 'Usage: python generateTB.py --wrapper stitchup_orig_wrapper.v --tb testbench.v --simscript vsim_script --stitchup stitchup.v --orig original.v'
sys.exit()
if opt in ("-w", "--wrapper"):
wrapper = arg
if opt in ("-t", "--tb"):
testbenchfile = arg
if opt in ("-s", "--simscript"):
simscript = arg
if opt in ("-u", "--stitchup"):
stitchup = arg
if opt in ("-i", "--orig"):
original = arg
infile = open(wrapper, 'r')
tboutfile = open(testbenchfile, 'w')
workoutfile = open(simscript + '_worklib', 'w')
simoutfile = open(simscript, 'w')
inString = infile.read();
signals = wH.getSignals(inString, 'topmost')
(inputlist, outputlist) = wH.gatherIOLists(wrapper, signals)
testbench = "//Testbench file for the stitchup wrapped project.\n"
testbench += "`timescale 1 ns / 1 ns\n"
testbench += "\nmodule tbtop (\n);\n\n"
#Instantiate a register for each input
for i in inputlist:
testbench += 'reg [' + str(i[1]) +':'+ str(i[2])+'] ' +i[0] + ';\n'
#Instantiate a wire for each output
for o in outputlist:
testbench += 'wire [' +str(o[1]) +':'+ str(o[2]) +'] ' + o[0] + ';\n'
if o[0] == "check_state":
check_MSB = str(o[1]) #This is needed for the assertion check.
testbench += 'integer log;\n'
testbench += '\n\n'
#Clock generation
testbench += 'initial\n\tclk = 0;\nalways @(clk)\n\tclk <= #10 ~clk;\n\n'
#Initial conditions for clock and reset signals
#Pulses the reset condition
testbench += 'initial begin\n\tlog = $fopen(\"res.log\",\"w\");\n//$monitor("At t=%t clk=%b %b %b %b %d", $time, clk, reset, start, finish, return_val);\n@(negedge clk);\nreset <= 1;\n@(negedge clk);\nreset <= 0;\nstart <= 1;\n@(negedge clk);\nstart <= 0;\nend\n\n'
#Assert statement to makesure that the Error flag has never been signalled
testbench += 'always @(negedge clk) begin\n'
testbench += '\tif (check_state != 0) begin\n'
testbench += '\t\t$fwrite(log, "%d,\t%d,\t%d,\t%d,\t1",($time-50)/20, finish, return_val, check_state);\n'
testbench += '\t\t$display(\"CONFIGURATION MISMATCH, CFG ERROR DETECTED! %d\", check_state);\n'
testbench += '\t\t$fclose(log);\n'
testbench += '\t\t$finish;\n'
testbench += '\tend\n'
testbench += 'end\n\n'
#End condition
testbench += 'always @(finish) begin\n'
testbench += '\tif (finish == 1) begin\n'
testbench += '\t\t$fwrite(log, "%d,\t%d,\t%d,\t%d,\t0",($time-50)/20, finish, return_val, check_state);\n'
testbench += '\t\t$display("At t=%t clk=%b finish=%b return_val=%d", $time, clk, finish, return_val);\n'
testbench += '\t\t$display("Cycles: %d", ($time-50)/20);\n'
testbench += '\t\t$fclose(log);\n'
testbench += '\t\t$finish;\n'
testbench += '\tend\n'
testbench += 'end\n\n'
#Memory
testbench += 'initial begin\nwaitrequest <= 1;\n@(negedge clk);\n@(negedge clk);\nwaitrequest <= 0;\nend\n\n'
#Instantiate the wrapper module
testbench += 'topmost dut(\n'
for s in signals:
testbench += '\t.' + s + '( '+ s + ' ),\n'
testbench = testbench[:-2]
testbench += '\n);\n'
testbench += '\n\nendmodule\n'
tboutfile.write(testbench)
tboutfile.close()
#Build the file to compile the work libs
worklibs = 'rm -r -f work\n'
worklibs += 'source ./modelsim.config\n'
worklibs += 'vlib work\n'
worklibs += 'vlog ${GENERIC_DIVIDER_LIBS}*.v\n'
worklibs += 'vlog ${VERILOG_LIBS}*.v ./'+wrapper+' ./'+testbenchfile+' ./'+stitchup+' ./'+original+'\n'
worklibs += 'vlog ${SYSTEMVERILOG_LIBS}*.v\n'
workoutfile.write(worklibs)
workoutfile.close()
sim = 'source ./modelsim.config\n'
sim += 'vlog ./'+wrapper+' ./'+testbenchfile+' ./'+stitchup+' ./'+original+'\n'
sim += 'vsim -c tbtop -do \"run 10000000000 ; echo [simstats]; quit -f;\"\n'
simoutfile.write(sim)
simoutfile.close()
def main(argv):
simscript = ''
testbenchfile = ''
cfslice = ''
original = ''
try:
opts, args = getopt.getopt(
argv, "ho:c:t:s", ["original=", "CFSlice=", "tb=", "simscript="])
except getopt.GetoptError:
print 'Usage: python generateTB.py --original original.v --CFSlice cfslice.v --tb testbench.v --simscript vsim_script'
sys.exit(2)
for opt, arg in opts:
if opt == '-h':
print 'Usage: python generateTB.py --original original.v --CFSlice cfslice.v --tb testbench.v --simscript vsim_script'
sys.exit()
if opt in ("-o", "--original"):
original = arg
if opt in ("-c", "--CFSlice"):
cfslice = arg
if opt in ("-t", "--tb"):
testbenchfile = arg
if opt in ("-s", "--simscript"):
simscript = arg
infile = open(original, 'r')
tboutfile = open(testbenchfile, 'w')
workoutfile = open(simscript + '_worklib', 'w')
simoutfile = open(simscript, 'w')
inString = infile.read()
signals = wH.getSignals(inString, 'top')
(inputlist, outputlist) = wH.gatherIOLists(original, signals)
testbench = "//Testbench file for the control runahead project.\n"
testbench += "`timescale 1 ns / 1 ns\n"
testbench += "\nmodule tbtop (\n);\n\n"
testbench += "reg[0:0] clk;\n"
testbench += "reg[0:0] reset;\n"
testbench += "reg[0:0] start;\n"
testbench += "wire[0:0] finish_o;\n"
testbench += "wire[0:0] finish_c;\n"
testbench += "reg[0:0] waitrequest;\n"
testbench += "reg[31:0] delta;\n"
testbench += "reg[0:0] cf_done;\n"
testbench += "wire[31:0] return_val;\n\n\n"
#Clock generation
testbench += 'initial\n\tclk = 0;\nalways @(clk)\n\tclk <= #10 ~clk;\n\n'
#instantiate the original circuit
#testbench += "top original(\n"
#testbench += "\t\t.clk(clk),\n"
#testbench += "\t\t.reset(reset),\n"
#testbench += "\t\t.start(start),\n"
#testbench += "\t\t.finish(finish_o),\n"
#testbench += "\t\t.waitrequest(waitrequest),\n"
#testbench += "\t\t.return_val(return_val)\n"
#testbench += ");\n\n\n"
#instantiate the original circuit
testbench += "cf_top cfslice(\n"
testbench += "\t\t.clk(clk),\n"
testbench += "\t\t.reset(reset),\n"
testbench += "\t\t.start(start),\n"
testbench += "\t\t.finish(finish_c),\n"
testbench += "\t\t.waitrequest(waitrequest),\n"
testbench += "\t\t.return_val(open)\n"
testbench += ");\n\n\n"
#Initial conditions for clock and reset signals
#Pulses the reset condition
testbench += 'initial begin\n@(negedge clk);\nreset <= 1;\n@(negedge clk);\nreset <= 0;\nstart <= 1;\n@(negedge clk);\nstart <= 0;\nend\n\n'
#Initialise Delta and Result
testbench += 'initial begin\ndelta <= 0;\ncf_done <= 0;\nend\n\n'
#Runahead done signal
testbench += 'always @(finish_c) begin\n'
testbench += '\tif(finish_c == 1) begin\n'
testbench += '\t\tcf_done <= 1;\n'
testbench += '\tend\n'
testbench += 'end\n\n'
#Accumulate the runahead counter
testbench += 'always @(negedge clk) begin\n'
testbench += '\tif(cf_done == 1) begin\n'
testbench += '\t\tdelta = delta + 1;\n'
testbench += '\tend\n'
testbench += 'end\n\n'
#End condition
testbench += 'always @(finish_o) begin\n'
testbench += '\tif (finish_o == 1) begin\n'
testbench += '\t\t$display("At t=%t clk=%b finish=%b return_val=%d runahead=%d", $time, clk, finish_o, return_val, delta);\n'
testbench += '\t\t$display("Cycles: %d", ($time-50)/20);\n'
testbench += '\t\t$finish;\n'
testbench += '\tend\n'
testbench += 'end\n\n'
#
# #Memory
testbench += 'initial begin\nwaitrequest <= 1;\n@(negedge clk);\n@(negedge clk);\nwaitrequest <= 0;\nend\n\n'
#
# #Instantiate the wrapper module
# testbench += 'topmost dut(\n'
# for s in signals:
# testbench += '\t.' + s + '( '+ s + ' ),\n'
# testbench = testbench[:-2]
# testbench += '\n);\n'
#
testbench += '\n\nendmodule\n'
tboutfile.write(testbench)
tboutfile.close()
#Build the file to compile the work libs
worklibs = '#!/bin/bash\n'
worklibs += 'rm -r -f work\n'
worklibs += 'source ./modelsim.config\n'
worklibs += 'vlib work\n'
worklibs += 'vlog ${GENERIC_DIVIDER_LIBS}*.v\n'
worklibs += 'vlog ${VERILOG_LIBS}*.v ./' + testbenchfile + ' ./rhBounded_' + cfslice + '\n'
worklibs += 'vlog ${SYSTEMVERILOG_LIBS}*.v\n'
workoutfile.write(worklibs)
workoutfile.close()
sim = '#!/bin/bash\n'
sim += 'source ./modelsim.config\n'
sim += 'vlog ./' + testbenchfile + ' ./rhBounded_' + cfslice + '\n'
sim += 'vsim -c tbtop -do \"run 10000000000 ; echo [simstats]; quit -f;\"\n'
simoutfile.write(sim)
simoutfile.close()
